2012-12-10 20:23:59 +04:00
|
|
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/*
|
|
|
|
* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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|
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*
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|
|
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* Derived from arch/arm/kvm/reset.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/errno.h>
|
2019-02-28 21:56:50 +03:00
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|
#include <linux/kernel.h>
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2012-12-10 20:23:59 +04:00
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#include <linux/kvm_host.h>
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|
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#include <linux/kvm.h>
|
2015-07-07 19:30:02 +03:00
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|
|
#include <linux/hw_breakpoint.h>
|
2019-02-28 21:46:44 +03:00
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|
|
#include <linux/slab.h>
|
2019-02-28 21:56:50 +03:00
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|
|
#include <linux/string.h>
|
2019-02-28 21:46:44 +03:00
|
|
|
#include <linux/types.h>
|
2012-12-10 20:23:59 +04:00
|
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|
|
2012-12-07 21:52:03 +04:00
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|
#include <kvm/arm_arch_timer.h>
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|
|
|
2018-09-26 19:32:43 +03:00
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|
|
#include <asm/cpufeature.h>
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2012-12-10 20:23:59 +04:00
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|
#include <asm/cputype.h>
|
2019-02-28 21:46:44 +03:00
|
|
|
#include <asm/fpsimd.h>
|
2012-12-10 20:23:59 +04:00
|
|
|
#include <asm/ptrace.h>
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|
|
|
#include <asm/kvm_arm.h>
|
arm64: kvm: allows kvm cpu hotplug
The current kvm implementation on arm64 does cpu-specific initialization
at system boot, and has no way to gracefully shutdown a core in terms of
kvm. This prevents kexec from rebooting the system at EL2.
This patch adds a cpu tear-down function and also puts an existing cpu-init
code into a separate function, kvm_arch_hardware_disable() and
kvm_arch_hardware_enable() respectively.
We don't need the arm64 specific cpu hotplug hook any more.
Since this patch modifies common code between arm and arm64, one stub
definition, __cpu_reset_hyp_mode(), is added on arm side to avoid
compilation errors.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
[Rebase, added separate VHE init/exit path, changed resets use of
kvm_call_hyp() to the __version, en/disabled hardware in init_subsystems(),
added icache maintenance to __kvm_hyp_reset() and removed lr restore, removed
guest-enter after teardown handling]
Signed-off-by: James Morse <james.morse@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-27 19:47:05 +03:00
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|
#include <asm/kvm_asm.h>
|
2012-12-10 20:23:59 +04:00
|
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|
#include <asm/kvm_coproc.h>
|
2018-12-20 14:36:07 +03:00
|
|
|
#include <asm/kvm_emulate.h>
|
arm64: kvm: allows kvm cpu hotplug
The current kvm implementation on arm64 does cpu-specific initialization
at system boot, and has no way to gracefully shutdown a core in terms of
kvm. This prevents kexec from rebooting the system at EL2.
This patch adds a cpu tear-down function and also puts an existing cpu-init
code into a separate function, kvm_arch_hardware_disable() and
kvm_arch_hardware_enable() respectively.
We don't need the arm64 specific cpu hotplug hook any more.
Since this patch modifies common code between arm and arm64, one stub
definition, __cpu_reset_hyp_mode(), is added on arm side to avoid
compilation errors.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
[Rebase, added separate VHE init/exit path, changed resets use of
kvm_call_hyp() to the __version, en/disabled hardware in init_subsystems(),
added icache maintenance to __kvm_hyp_reset() and removed lr restore, removed
guest-enter after teardown handling]
Signed-off-by: James Morse <james.morse@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-27 19:47:05 +03:00
|
|
|
#include <asm/kvm_mmu.h>
|
2019-02-28 21:56:50 +03:00
|
|
|
#include <asm/virt.h>
|
2012-12-10 20:23:59 +04:00
|
|
|
|
2018-09-26 19:32:52 +03:00
|
|
|
/* Maximum phys_shift supported for any VM on this host */
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|
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static u32 kvm_ipa_limit;
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|
2012-12-10 20:23:59 +04:00
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|
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/*
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* ARMv8 Reset Values
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|
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*/
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static const struct kvm_regs default_regs_reset = {
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.regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
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|
|
PSR_F_BIT | PSR_D_BIT),
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|
|
|
};
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|
|
|
|
2013-02-07 14:46:46 +04:00
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static const struct kvm_regs default_regs_reset32 = {
|
2018-07-05 17:16:53 +03:00
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|
|
.regs.pstate = (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT |
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|
|
PSR_AA32_I_BIT | PSR_AA32_F_BIT),
|
2013-02-07 14:46:46 +04:00
|
|
|
};
|
|
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|
|
static bool cpu_has_32bit_el1(void)
|
|
|
|
{
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|
|
|
u64 pfr0;
|
|
|
|
|
2017-03-23 18:14:39 +03:00
|
|
|
pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
|
2013-02-07 14:46:46 +04:00
|
|
|
return !!(pfr0 & 0x20);
|
|
|
|
}
|
|
|
|
|
2015-07-07 19:30:02 +03:00
|
|
|
/**
|
2018-10-12 19:12:48 +03:00
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|
|
* kvm_arch_vm_ioctl_check_extension
|
2015-07-07 19:30:02 +03:00
|
|
|
*
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|
|
* We currently assume that the number of HW registers is uniform
|
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|
|
* across all CPUs (see cpuinfo_sanity_check).
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|
|
*/
|
2018-10-12 19:12:48 +03:00
|
|
|
int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
|
2012-12-10 20:23:59 +04:00
|
|
|
{
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|
|
|
int r;
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|
|
|
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|
|
switch (ext) {
|
2013-02-07 14:46:46 +04:00
|
|
|
case KVM_CAP_ARM_EL1_32BIT:
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|
|
r = cpu_has_32bit_el1();
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|
|
break;
|
2015-07-07 19:30:02 +03:00
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|
case KVM_CAP_GUEST_DEBUG_HW_BPS:
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|
|
r = get_num_brps();
|
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|
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break;
|
|
|
|
case KVM_CAP_GUEST_DEBUG_HW_WPS:
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|
|
r = get_num_wrps();
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|
|
|
break;
|
2016-01-11 17:46:15 +03:00
|
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|
case KVM_CAP_ARM_PMU_V3:
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|
|
r = kvm_arm_support_pmu_v3();
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|
|
break;
|
2018-07-19 18:24:23 +03:00
|
|
|
case KVM_CAP_ARM_INJECT_SERROR_ESR:
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|
|
|
r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
|
|
|
|
break;
|
2015-07-07 19:30:02 +03:00
|
|
|
case KVM_CAP_SET_GUEST_DEBUG:
|
2016-01-11 15:56:17 +03:00
|
|
|
case KVM_CAP_VCPU_ATTRIBUTES:
|
2015-07-07 19:30:02 +03:00
|
|
|
r = 1;
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|
|
|
break;
|
2018-09-26 19:32:54 +03:00
|
|
|
case KVM_CAP_ARM_VM_IPA_SIZE:
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|
|
r = kvm_ipa_limit;
|
|
|
|
break;
|
2019-01-15 15:21:22 +03:00
|
|
|
case KVM_CAP_ARM_SVE:
|
|
|
|
r = system_supports_sve();
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|
|
break;
|
2012-12-10 20:23:59 +04:00
|
|
|
default:
|
|
|
|
r = 0;
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|
|
|
}
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|
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|
return r;
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|
|
|
}
|
|
|
|
|
2019-02-28 21:46:44 +03:00
|
|
|
unsigned int kvm_sve_max_vl;
|
|
|
|
|
2019-04-12 17:30:58 +03:00
|
|
|
int kvm_arm_init_sve(void)
|
2019-02-28 21:46:44 +03:00
|
|
|
{
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|
|
|
if (system_supports_sve()) {
|
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|
|
kvm_sve_max_vl = sve_max_virtualisable_vl;
|
|
|
|
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|
|
/*
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|
|
|
* The get_sve_reg()/set_sve_reg() ioctl interface will need
|
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|
|
* to be extended with multiple register slice support in
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|
|
* order to support vector lengths greater than
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|
|
* SVE_VL_ARCH_MAX:
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|
|
*/
|
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|
if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX))
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|
kvm_sve_max_vl = SVE_VL_ARCH_MAX;
|
|
|
|
|
|
|
|
/*
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|
|
|
* Don't even try to make use of vector lengths that
|
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|
|
* aren't available on all CPUs, for now:
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|
|
|
*/
|
|
|
|
if (kvm_sve_max_vl < sve_max_vl)
|
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|
|
pr_warn("KVM: SVE vector length for guests limited to %u bytes\n",
|
|
|
|
kvm_sve_max_vl);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-02-28 21:56:50 +03:00
|
|
|
static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
if (!system_supports_sve())
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Verify that KVM startup enforced this when SVE was detected: */
|
|
|
|
if (WARN_ON(!has_vhe()))
|
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|
|
return -EINVAL;
|
|
|
|
|
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|
|
vcpu->arch.sve_max_vl = kvm_sve_max_vl;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Userspace can still customize the vector lengths by writing
|
|
|
|
* KVM_REG_ARM64_SVE_VLS. Allocation is deferred until
|
|
|
|
* kvm_arm_vcpu_finalize(), which freezes the configuration.
|
|
|
|
*/
|
|
|
|
vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-02-28 21:46:44 +03:00
|
|
|
/*
|
|
|
|
* Finalize vcpu's maximum SVE vector length, allocating
|
|
|
|
* vcpu->arch.sve_state as necessary.
|
|
|
|
*/
|
|
|
|
static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
void *buf;
|
|
|
|
unsigned int vl;
|
|
|
|
|
|
|
|
vl = vcpu->arch.sve_max_vl;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Resposibility for these properties is shared between
|
|
|
|
* kvm_arm_init_arch_resources(), kvm_vcpu_enable_sve() and
|
|
|
|
* set_sve_vls(). Double-check here just to be sure:
|
|
|
|
*/
|
|
|
|
if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl ||
|
|
|
|
vl > SVE_VL_ARCH_MAX))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
buf = kzalloc(SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)), GFP_KERNEL);
|
|
|
|
if (!buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
vcpu->arch.sve_state = buf;
|
|
|
|
vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-04-10 19:17:37 +03:00
|
|
|
int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
|
2019-02-28 21:46:44 +03:00
|
|
|
{
|
2019-04-10 19:17:37 +03:00
|
|
|
switch (feature) {
|
2019-02-28 21:46:44 +03:00
|
|
|
case KVM_ARM_VCPU_SVE:
|
|
|
|
if (!vcpu_has_sve(vcpu))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (kvm_arm_vcpu_sve_finalized(vcpu))
|
|
|
|
return -EPERM;
|
|
|
|
|
|
|
|
return kvm_vcpu_finalize_sve(vcpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
kfree(vcpu->arch.sve_state);
|
|
|
|
}
|
|
|
|
|
2019-02-28 21:56:50 +03:00
|
|
|
static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
if (vcpu_has_sve(vcpu))
|
|
|
|
memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu));
|
|
|
|
}
|
|
|
|
|
2012-12-10 20:23:59 +04:00
|
|
|
/**
|
|
|
|
* kvm_reset_vcpu - sets core registers and sys_regs to reset value
|
|
|
|
* @vcpu: The VCPU pointer
|
|
|
|
*
|
|
|
|
* This function finds the right table above and sets the registers on
|
2016-05-21 14:53:14 +03:00
|
|
|
* the virtual CPU struct to their architecturally defined reset
|
2019-02-28 21:56:50 +03:00
|
|
|
* values, except for registers whose reset is deferred until
|
|
|
|
* kvm_arm_vcpu_finalize().
|
2018-12-20 14:44:05 +03:00
|
|
|
*
|
|
|
|
* Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
|
|
|
|
* ioctl or as part of handling a request issued by another VCPU in the PSCI
|
|
|
|
* handling code. In the first case, the VCPU will not be loaded, and in the
|
|
|
|
* second case the VCPU will be loaded. Because this function operates purely
|
|
|
|
* on the memory-backed valus of system registers, we want to do a full put if
|
|
|
|
* we were loaded (handling a request) and load the values back at the end of
|
|
|
|
* the function. Otherwise we leave the state alone. In both cases, we
|
|
|
|
* disable preemption around the vcpu reset as we would otherwise race with
|
|
|
|
* preempt notifiers which also call put/load.
|
2012-12-10 20:23:59 +04:00
|
|
|
*/
|
|
|
|
int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
const struct kvm_regs *cpu_reset;
|
2018-12-20 14:44:05 +03:00
|
|
|
int ret = -EINVAL;
|
|
|
|
bool loaded;
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
loaded = (vcpu->cpu != -1);
|
|
|
|
if (loaded)
|
|
|
|
kvm_arch_vcpu_put(vcpu);
|
2012-12-10 20:23:59 +04:00
|
|
|
|
2019-02-28 21:56:50 +03:00
|
|
|
if (!kvm_arm_vcpu_sve_finalized(vcpu)) {
|
|
|
|
if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) {
|
|
|
|
ret = kvm_vcpu_enable_sve(vcpu);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
kvm_vcpu_reset_sve(vcpu);
|
|
|
|
}
|
|
|
|
|
2012-12-10 20:23:59 +04:00
|
|
|
switch (vcpu->arch.target) {
|
|
|
|
default:
|
2013-02-07 14:46:46 +04:00
|
|
|
if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
|
|
|
|
if (!cpu_has_32bit_el1())
|
2018-12-20 14:44:05 +03:00
|
|
|
goto out;
|
2013-02-07 14:46:46 +04:00
|
|
|
cpu_reset = &default_regs_reset32;
|
|
|
|
} else {
|
|
|
|
cpu_reset = &default_regs_reset;
|
|
|
|
}
|
|
|
|
|
2012-12-10 20:23:59 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reset core registers */
|
|
|
|
memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset));
|
|
|
|
|
|
|
|
/* Reset system registers */
|
|
|
|
kvm_reset_sys_regs(vcpu);
|
|
|
|
|
2018-12-20 14:36:07 +03:00
|
|
|
/*
|
|
|
|
* Additional reset state handling that PSCI may have imposed on us.
|
|
|
|
* Must be done after all the sys_reg reset.
|
|
|
|
*/
|
|
|
|
if (vcpu->arch.reset_state.reset) {
|
|
|
|
unsigned long target_pc = vcpu->arch.reset_state.pc;
|
|
|
|
|
|
|
|
/* Gracefully handle Thumb2 entry point */
|
|
|
|
if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
|
|
|
|
target_pc &= ~1UL;
|
|
|
|
vcpu_set_thumb(vcpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Propagate caller endianness */
|
|
|
|
if (vcpu->arch.reset_state.be)
|
|
|
|
kvm_vcpu_set_be(vcpu);
|
|
|
|
|
|
|
|
*vcpu_pc(vcpu) = target_pc;
|
|
|
|
vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
|
|
|
|
|
|
|
|
vcpu->arch.reset_state.reset = false;
|
|
|
|
}
|
|
|
|
|
2015-09-11 06:30:22 +03:00
|
|
|
/* Reset PMU */
|
|
|
|
kvm_pmu_vcpu_reset(vcpu);
|
|
|
|
|
2018-05-29 15:11:18 +03:00
|
|
|
/* Default workaround setup is enabled (if supported) */
|
|
|
|
if (kvm_arm_have_ssbd() == KVM_SSBD_KERNEL)
|
|
|
|
vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
|
|
|
|
|
2012-12-07 21:52:03 +04:00
|
|
|
/* Reset timer */
|
2018-12-20 14:44:05 +03:00
|
|
|
ret = kvm_timer_vcpu_reset(vcpu);
|
|
|
|
out:
|
|
|
|
if (loaded)
|
|
|
|
kvm_arch_vcpu_load(vcpu, smp_processor_id());
|
|
|
|
preempt_enable();
|
|
|
|
return ret;
|
2012-12-10 20:23:59 +04:00
|
|
|
}
|
2018-09-26 19:32:42 +03:00
|
|
|
|
2018-09-26 19:32:52 +03:00
|
|
|
void kvm_set_ipa_limit(void)
|
|
|
|
{
|
|
|
|
unsigned int ipa_max, pa_max, va_max, parange;
|
|
|
|
|
|
|
|
parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7;
|
|
|
|
pa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
|
|
|
|
|
|
|
|
/* Clamp the IPA limit to the PA size supported by the kernel */
|
|
|
|
ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max;
|
|
|
|
/*
|
|
|
|
* Since our stage2 table is dependent on the stage1 page table code,
|
|
|
|
* we must always honor the following condition:
|
|
|
|
*
|
|
|
|
* Number of levels in Stage1 >= Number of levels in Stage2.
|
|
|
|
*
|
|
|
|
* So clamp the ipa limit further down to limit the number of levels.
|
|
|
|
* Since we can concatenate upto 16 tables at entry level, we could
|
|
|
|
* go upto 4bits above the maximum VA addressible with the current
|
|
|
|
* number of levels.
|
|
|
|
*/
|
|
|
|
va_max = PGDIR_SHIFT + PAGE_SHIFT - 3;
|
|
|
|
va_max += 4;
|
|
|
|
|
|
|
|
if (va_max < ipa_max)
|
|
|
|
ipa_max = va_max;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the final limit is lower than the real physical address
|
|
|
|
* limit of the CPUs, report the reason.
|
|
|
|
*/
|
|
|
|
if (ipa_max < pa_max)
|
|
|
|
pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n",
|
|
|
|
(va_max < pa_max) ? "Virtual" : "Physical");
|
|
|
|
|
|
|
|
WARN(ipa_max < KVM_PHYS_SHIFT,
|
|
|
|
"KVM IPA limit (%d bit) is smaller than default size\n", ipa_max);
|
|
|
|
kvm_ipa_limit = ipa_max;
|
|
|
|
kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit);
|
|
|
|
}
|
|
|
|
|
2018-09-26 19:32:43 +03:00
|
|
|
/*
|
|
|
|
* Configure the VTCR_EL2 for this VM. The VTCR value is common
|
|
|
|
* across all the physical CPUs on the system. We use system wide
|
|
|
|
* sanitised values to fill in different fields, except for Hardware
|
|
|
|
* Management of Access Flags. HA Flag is set unconditionally on
|
|
|
|
* all CPUs, as it is safe to run with or without the feature and
|
|
|
|
* the bit is RES0 on CPUs that don't support it.
|
|
|
|
*/
|
2018-10-01 15:40:36 +03:00
|
|
|
int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
|
2018-09-26 19:32:42 +03:00
|
|
|
{
|
2018-09-26 19:32:43 +03:00
|
|
|
u64 vtcr = VTCR_EL2_FLAGS;
|
|
|
|
u32 parange, phys_shift;
|
2018-09-26 19:32:53 +03:00
|
|
|
u8 lvls;
|
2018-09-26 19:32:43 +03:00
|
|
|
|
2018-09-26 19:32:54 +03:00
|
|
|
if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK)
|
2018-09-26 19:32:42 +03:00
|
|
|
return -EINVAL;
|
2018-09-26 19:32:43 +03:00
|
|
|
|
2018-09-26 19:32:54 +03:00
|
|
|
phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type);
|
|
|
|
if (phys_shift) {
|
|
|
|
if (phys_shift > kvm_ipa_limit ||
|
|
|
|
phys_shift < 32)
|
|
|
|
return -EINVAL;
|
|
|
|
} else {
|
|
|
|
phys_shift = KVM_PHYS_SHIFT;
|
|
|
|
}
|
|
|
|
|
2018-09-26 19:32:43 +03:00
|
|
|
parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 7;
|
|
|
|
if (parange > ID_AA64MMFR0_PARANGE_MAX)
|
|
|
|
parange = ID_AA64MMFR0_PARANGE_MAX;
|
|
|
|
vtcr |= parange << VTCR_EL2_PS_SHIFT;
|
|
|
|
|
|
|
|
vtcr |= VTCR_EL2_T0SZ(phys_shift);
|
2018-09-26 19:32:53 +03:00
|
|
|
/*
|
|
|
|
* Use a minimum 2 level page table to prevent splitting
|
|
|
|
* host PMD huge pages at stage2.
|
|
|
|
*/
|
|
|
|
lvls = stage2_pgtable_levels(phys_shift);
|
|
|
|
if (lvls < 2)
|
|
|
|
lvls = 2;
|
|
|
|
vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls);
|
2018-09-26 19:32:43 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable the Hardware Access Flag management, unconditionally
|
|
|
|
* on all CPUs. The features is RES0 on CPUs without the support
|
|
|
|
* and must be ignored by the CPUs.
|
|
|
|
*/
|
|
|
|
vtcr |= VTCR_EL2_HA;
|
|
|
|
|
|
|
|
/* Set the vmid bits */
|
|
|
|
vtcr |= (kvm_get_vmid_bits() == 16) ?
|
|
|
|
VTCR_EL2_VS_16BIT :
|
|
|
|
VTCR_EL2_VS_8BIT;
|
|
|
|
kvm->arch.vtcr = vtcr;
|
2018-09-26 19:32:42 +03:00
|
|
|
return 0;
|
|
|
|
}
|