2012-06-13 21:01:28 +04:00
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/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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2015-07-08 00:11:46 +03:00
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#include <linux/irqchip.h>
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2014-02-11 00:00:02 +04:00
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#include <linux/irqchip/chained_irq.h>
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2014-04-14 17:54:02 +04:00
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#include <linux/cpu.h>
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2012-06-13 21:01:28 +04:00
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2013-08-10 00:27:11 +04:00
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#include <linux/of_pci.h>
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2012-06-13 21:01:28 +04:00
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#include <linux/irqdomain.h>
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2013-08-10 00:27:11 +04:00
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#include <linux/slab.h>
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2014-11-21 19:00:00 +03:00
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#include <linux/syscore_ops.h>
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2013-08-10 00:27:11 +04:00
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#include <linux/msi.h>
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2012-06-13 21:01:28 +04:00
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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2012-08-02 12:19:12 +04:00
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#include <asm/smp_plat.h>
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2013-04-10 01:26:15 +04:00
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#include <asm/mach/irq.h>
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2017-05-18 11:07:38 +03:00
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/*
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* Overall diagram of the Armada XP interrupt controller:
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*
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* To CPU 0 To CPU 1
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*
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* /\ /\
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* || ||
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* +---------------+ +---------------+
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* | | | |
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* | per-CPU | | per-CPU |
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* | mask/unmask | | mask/unmask |
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* | CPU0 | | CPU1 |
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* | | | |
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* +---------------+ +---------------+
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* /\ /\
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* || ||
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* \\_______________________//
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* ||
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* +-------------------+
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* | |
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* | Global interrupt |
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* | mask/unmask |
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* | |
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* +-------------------+
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* /\
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* ||
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* interrupt from
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* device
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*
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* The "global interrupt mask/unmask" is modified using the
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* ARMADA_370_XP_INT_SET_ENABLE_OFFS and
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* ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
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* to "main_int_base".
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*
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* The "per-CPU mask/unmask" is modified using the
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* ARMADA_370_XP_INT_SET_MASK_OFFS and
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* ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
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* "per_cpu_int_base". This base address points to a special address,
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* which automatically accesses the registers of the current CPU.
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*
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* The per-CPU mask/unmask can also be adjusted using the global
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* per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
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* to configure interrupt affinity.
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*
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* Due to this model, all interrupts need to be mask/unmasked at two
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* different levels: at the global level and at the per-CPU level.
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*
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* This driver takes the following approach to deal with this:
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*
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* - For global interrupts:
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*
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* At ->map() time, a global interrupt is unmasked at the per-CPU
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* mask/unmask level. It is therefore unmasked at this level for
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* the current CPU, running the ->map() code. This allows to have
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* the interrupt unmasked at this level in non-SMP
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* configurations. In SMP configurations, the ->set_affinity()
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* callback is called, which using the
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* ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
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* for the interrupt.
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*
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* The ->mask() and ->unmask() operations only mask/unmask the
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* interrupt at the "global" level.
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*
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* So, a global interrupt is enabled at the per-CPU level as soon
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* as it is mapped. At run time, the masking/unmasking takes place
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* at the global level.
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*
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* - For per-CPU interrupts
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*
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* At ->map() time, a per-CPU interrupt is unmasked at the global
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* mask/unmask level.
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*
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* The ->mask() and ->unmask() operations mask/unmask the interrupt
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* at the per-CPU level.
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*
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* So, a per-CPU interrupt is enabled at the global level as soon
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* as it is mapped. At run time, the masking/unmasking takes place
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* at the per-CPU level.
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*/
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2012-06-13 21:01:28 +04:00
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2017-05-18 11:07:37 +03:00
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/* Registers relative to main_int_base */
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2012-06-04 20:50:12 +04:00
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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2017-05-18 11:07:37 +03:00
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#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04)
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2012-06-13 21:01:28 +04:00
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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2012-12-06 00:43:23 +04:00
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#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
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2014-03-05 00:43:41 +04:00
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#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
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2014-09-25 15:17:19 +04:00
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#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
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2012-06-13 21:01:28 +04:00
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2017-05-18 11:07:37 +03:00
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/* Registers relative to per_cpu_int_base */
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#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08)
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#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c)
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2014-02-11 00:00:02 +04:00
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#define ARMADA_375_PPI_CAUSE (0x10)
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2017-05-18 11:07:37 +03:00
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
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#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
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2012-08-02 12:19:12 +04:00
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2012-12-06 00:43:23 +04:00
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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2013-04-10 01:26:17 +04:00
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#define IPI_DOORBELL_START (0)
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#define IPI_DOORBELL_END (8)
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#define IPI_DOORBELL_MASK 0xFF
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2013-08-10 00:27:11 +04:00
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#define PCI_MSI_DOORBELL_START (16)
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#define PCI_MSI_DOORBELL_NR (16)
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#define PCI_MSI_DOORBELL_END (32)
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#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
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2012-08-02 12:19:12 +04:00
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2012-06-13 21:01:28 +04:00
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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2014-11-21 19:00:00 +03:00
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static u32 doorbell_mask_reg;
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irqchip: armada-370-xp: Fix chained per-cpu interrupts
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt
controller. Yet, it still has to handle some per-cpu interrupt.
To do so, it is chained with the GIC using a per-cpu interrupt. However, the
current code only call irq_set_chained_handler, which is called and enable that
interrupt only on the boot CPU, which means that the parent per-CPU interrupt
is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to
actually work as expected.
This was not seen until now since the only MPIC PPI users were the Marvell
timers that were not working, but not used either since the system use the ARM
TWD by default, and the ethernet controllers, that are faking there interrupts
as SPI, and don't really expect to have interrupts on the secondary cores
anyway.
Add a CPU notifier that will enable the PPI on the secondary cores when they
are brought up.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03 13:27:23 +03:00
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static int parent_irq;
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2013-08-10 00:27:11 +04:00
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#ifdef CONFIG_PCI_MSI
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static struct irq_domain *armada_370_xp_msi_domain;
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2016-02-10 17:46:57 +03:00
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static struct irq_domain *armada_370_xp_msi_inner_domain;
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2013-08-10 00:27:11 +04:00
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static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
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static DEFINE_MUTEX(msi_used_lock);
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static phys_addr_t msi_doorbell_addr;
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#endif
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2012-06-13 21:01:28 +04:00
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2015-03-03 13:43:15 +03:00
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static inline bool is_percpu_irq(irq_hw_number_t irq)
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{
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2015-09-25 19:09:34 +03:00
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if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
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2015-03-03 13:43:15 +03:00
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return true;
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2015-09-25 19:09:34 +03:00
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return false;
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2015-03-03 13:43:15 +03:00
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}
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2012-12-06 00:43:23 +04:00
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/*
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* In SMP mode:
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* For shared global interrupts, mask/unmask global enable bit
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2013-03-16 02:34:04 +04:00
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* For CPU interrupts, mask/unmask the calling CPU's bit
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2012-12-06 00:43:23 +04:00
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*/
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2012-06-13 21:01:28 +04:00
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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2012-12-06 00:43:23 +04:00
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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2015-03-03 13:43:15 +03:00
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if (!is_percpu_irq(hwirq))
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2012-12-06 00:43:23 +04:00
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_SET_MASK_OFFS);
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2012-06-13 21:01:28 +04:00
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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2012-12-06 00:43:23 +04:00
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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2015-03-03 13:43:15 +03:00
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if (!is_percpu_irq(hwirq))
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2012-12-06 00:43:23 +04:00
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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2012-06-13 21:01:28 +04:00
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}
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2013-08-10 00:27:11 +04:00
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#ifdef CONFIG_PCI_MSI
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2016-02-10 17:46:57 +03:00
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static struct irq_chip armada_370_xp_msi_irq_chip = {
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2016-02-10 17:46:59 +03:00
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.name = "MPIC MSI",
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2016-02-10 17:46:57 +03:00
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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2013-08-10 00:27:11 +04:00
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2016-02-10 17:46:57 +03:00
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static struct msi_domain_info armada_370_xp_msi_domain_info = {
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2016-02-10 17:47:00 +03:00
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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2017-08-18 15:59:26 +03:00
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
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2016-02-10 17:46:57 +03:00
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.chip = &armada_370_xp_msi_irq_chip,
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};
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2013-08-10 00:27:11 +04:00
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2016-02-10 17:46:57 +03:00
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static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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2013-08-10 00:27:11 +04:00
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{
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2016-02-10 17:46:57 +03:00
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msg->address_lo = lower_32_bits(msi_doorbell_addr);
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msg->address_hi = upper_32_bits(msi_doorbell_addr);
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msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
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2013-08-10 00:27:11 +04:00
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}
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2016-02-10 17:46:57 +03:00
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static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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2013-08-10 00:27:11 +04:00
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{
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2016-02-10 17:46:57 +03:00
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return -EINVAL;
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}
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2013-08-10 00:27:11 +04:00
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2016-02-10 17:46:57 +03:00
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static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
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2016-02-10 17:46:59 +03:00
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.name = "MPIC MSI",
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2016-02-10 17:46:57 +03:00
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.irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
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.irq_set_affinity = armada_370_xp_msi_set_affinity,
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};
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2014-09-07 22:57:54 +04:00
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2016-02-10 17:46:57 +03:00
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static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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2016-02-10 17:47:00 +03:00
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int hwirq, i;
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2013-08-10 00:27:11 +04:00
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2016-02-10 17:46:57 +03:00
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mutex_lock(&msi_used_lock);
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2016-02-10 17:47:00 +03:00
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hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR,
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0, nr_irqs, 0);
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2016-02-10 17:46:57 +03:00
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if (hwirq >= PCI_MSI_DOORBELL_NR) {
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mutex_unlock(&msi_used_lock);
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return -ENOSPC;
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2013-08-10 00:27:11 +04:00
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}
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2016-02-10 17:47:00 +03:00
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bitmap_set(msi_used, hwirq, nr_irqs);
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2016-02-10 17:46:57 +03:00
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mutex_unlock(&msi_used_lock);
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2013-08-10 00:27:11 +04:00
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2016-02-10 17:47:00 +03:00
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for (i = 0; i < nr_irqs; i++) {
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&armada_370_xp_msi_bottom_irq_chip,
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domain->host_data, handle_simple_irq,
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NULL, NULL);
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}
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2013-08-10 00:27:11 +04:00
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2016-02-10 17:46:57 +03:00
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return hwirq;
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2013-08-10 00:27:11 +04:00
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}
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2016-02-10 17:46:57 +03:00
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static void armada_370_xp_msi_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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2013-08-10 00:27:11 +04:00
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{
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2016-02-10 17:46:57 +03:00
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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2013-08-10 00:27:11 +04:00
|
|
|
|
2016-02-10 17:46:57 +03:00
|
|
|
mutex_lock(&msi_used_lock);
|
2016-02-10 17:47:00 +03:00
|
|
|
bitmap_clear(msi_used, d->hwirq, nr_irqs);
|
2016-02-10 17:46:57 +03:00
|
|
|
mutex_unlock(&msi_used_lock);
|
2013-08-10 00:27:11 +04:00
|
|
|
}
|
|
|
|
|
2016-02-10 17:46:57 +03:00
|
|
|
static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
|
|
|
|
.alloc = armada_370_xp_msi_alloc,
|
|
|
|
.free = armada_370_xp_msi_free,
|
2013-08-10 00:27:11 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
static int armada_370_xp_msi_init(struct device_node *node,
|
|
|
|
phys_addr_t main_int_phys_base)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
msi_doorbell_addr = main_int_phys_base +
|
|
|
|
ARMADA_370_XP_SW_TRIG_INT_OFFS;
|
|
|
|
|
2016-02-10 17:46:57 +03:00
|
|
|
armada_370_xp_msi_inner_domain =
|
|
|
|
irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
|
|
|
|
&armada_370_xp_msi_domain_ops, NULL);
|
|
|
|
if (!armada_370_xp_msi_inner_domain)
|
2013-08-10 00:27:11 +04:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
armada_370_xp_msi_domain =
|
2016-02-10 17:46:57 +03:00
|
|
|
pci_msi_create_irq_domain(of_node_to_fwnode(node),
|
|
|
|
&armada_370_xp_msi_domain_info,
|
|
|
|
armada_370_xp_msi_inner_domain);
|
2013-08-10 00:27:11 +04:00
|
|
|
if (!armada_370_xp_msi_domain) {
|
2016-02-10 17:46:57 +03:00
|
|
|
irq_domain_remove(armada_370_xp_msi_inner_domain);
|
2013-08-10 00:27:11 +04:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
|
|
|
|
| PCI_MSI_DOORBELL_MASK;
|
|
|
|
|
|
|
|
writel(reg, per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
|
|
|
|
/* Unmask IPI interrupt */
|
|
|
|
writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int armada_370_xp_msi_init(struct device_node *node,
|
|
|
|
phys_addr_t main_int_phys_base)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-08-02 12:19:12 +04:00
|
|
|
#ifdef CONFIG_SMP
|
2014-01-21 01:52:05 +04:00
|
|
|
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
|
|
|
|
|
2012-08-02 12:19:12 +04:00
|
|
|
static int armada_xp_set_affinity(struct irq_data *d,
|
|
|
|
const struct cpumask *mask_val, bool force)
|
|
|
|
{
|
2012-12-06 00:43:23 +04:00
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2014-03-05 00:43:41 +04:00
|
|
|
unsigned long reg, mask;
|
2012-12-06 00:43:23 +04:00
|
|
|
int cpu;
|
|
|
|
|
2014-03-05 00:43:41 +04:00
|
|
|
/* Select a single core from the affinity mask which is online */
|
|
|
|
cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
|
|
|
mask = 1UL << cpu_logical_map(cpu);
|
2012-12-06 00:43:23 +04:00
|
|
|
|
|
|
|
raw_spin_lock(&irq_controller_lock);
|
|
|
|
reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
|
2014-03-05 00:43:41 +04:00
|
|
|
reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
|
2012-12-06 00:43:23 +04:00
|
|
|
writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
|
|
|
|
raw_spin_unlock(&irq_controller_lock);
|
|
|
|
|
2017-08-18 11:39:19 +03:00
|
|
|
irq_data_update_effective_affinity(d, cpumask_of(cpu));
|
|
|
|
|
2014-10-24 15:59:16 +04:00
|
|
|
return IRQ_SET_MASK_OK;
|
2012-08-02 12:19:12 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-06-13 21:01:28 +04:00
|
|
|
static struct irq_chip armada_370_xp_irq_chip = {
|
2016-02-10 17:46:59 +03:00
|
|
|
.name = "MPIC",
|
2012-06-13 21:01:28 +04:00
|
|
|
.irq_mask = armada_370_xp_irq_mask,
|
|
|
|
.irq_mask_ack = armada_370_xp_irq_mask,
|
|
|
|
.irq_unmask = armada_370_xp_irq_unmask,
|
2012-08-02 12:19:12 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
.irq_set_affinity = armada_xp_set_affinity,
|
|
|
|
#endif
|
2015-03-30 17:04:37 +03:00
|
|
|
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
|
2012-06-13 21:01:28 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
|
|
|
|
unsigned int virq, irq_hw_number_t hw)
|
|
|
|
{
|
|
|
|
armada_370_xp_irq_mask(irq_get_irq_data(virq));
|
2015-03-03 13:43:15 +03:00
|
|
|
if (!is_percpu_irq(hw))
|
2013-04-05 16:32:52 +04:00
|
|
|
writel(hw, per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
else
|
|
|
|
writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
2012-06-13 21:01:28 +04:00
|
|
|
irq_set_status_flags(virq, IRQ_LEVEL);
|
2013-01-25 21:32:41 +04:00
|
|
|
|
2015-03-03 13:43:15 +03:00
|
|
|
if (is_percpu_irq(hw)) {
|
2013-01-25 21:32:41 +04:00
|
|
|
irq_set_percpu_devid(virq);
|
|
|
|
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
|
|
|
handle_percpu_devid_irq);
|
|
|
|
} else {
|
|
|
|
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
|
|
|
handle_level_irq);
|
2017-08-18 11:39:19 +03:00
|
|
|
irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
|
2013-01-25 21:32:41 +04:00
|
|
|
}
|
2015-08-30 02:01:22 +03:00
|
|
|
irq_set_probe(virq);
|
2012-06-13 21:01:28 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-14 17:54:02 +04:00
|
|
|
static void armada_xp_mpic_smp_cpu_init(void)
|
2012-08-02 12:19:12 +04:00
|
|
|
{
|
2014-05-31 00:18:18 +04:00
|
|
|
u32 control;
|
|
|
|
int nr_irqs, i;
|
|
|
|
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
|
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
|
|
writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
|
|
|
|
|
2012-08-02 12:19:12 +04:00
|
|
|
/* Clear pending IPIs */
|
|
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
|
|
|
|
/* Enable first 8 IPIs */
|
2013-04-10 01:26:17 +04:00
|
|
|
writel(IPI_DOORBELL_MASK, per_cpu_int_base +
|
2012-08-02 12:19:12 +04:00
|
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
|
|
|
|
/* Unmask IPI interrupt */
|
|
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
}
|
2014-04-14 17:54:02 +04:00
|
|
|
|
2015-03-03 13:43:16 +03:00
|
|
|
static void armada_xp_mpic_perf_init(void)
|
|
|
|
{
|
|
|
|
unsigned long cpuid = cpu_logical_map(smp_processor_id());
|
|
|
|
|
|
|
|
/* Enable Performance Counter Overflow interrupts */
|
|
|
|
writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
|
|
|
|
per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
|
|
|
|
}
|
|
|
|
|
2015-03-03 13:43:14 +03:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static void armada_mpic_send_doorbell(const struct cpumask *mask,
|
|
|
|
unsigned int irq)
|
|
|
|
{
|
|
|
|
int cpu;
|
|
|
|
unsigned long map = 0;
|
|
|
|
|
|
|
|
/* Convert our logical CPU mask into a physical one. */
|
|
|
|
for_each_cpu(cpu, mask)
|
|
|
|
map |= 1 << cpu_logical_map(cpu);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure that stores to Normal memory are visible to the
|
|
|
|
* other CPUs before issuing the IPI.
|
|
|
|
*/
|
|
|
|
dsb();
|
|
|
|
|
|
|
|
/* submit softirq */
|
|
|
|
writel((map << 8) | irq, main_int_base +
|
|
|
|
ARMADA_370_XP_SW_TRIG_INT_OFFS);
|
|
|
|
}
|
|
|
|
|
irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time
Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().
While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this commit:
the IRQ_NOAUTOEN flag is no longer cleared. This functional change
caused a regression on Armada XP, which no longer works properly after
suspend/resume because per-CPU interrupts remain disabled. This
regression was temporarly worked around in commit
353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing
IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit
implements the solution that was initially discussed with Thomas
Gleixner.
Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make sure
that the interrupts remain in the same state after resuming. Therefore,
it relies on the kernel to say whether the interrupt is disabled or not,
using the irqd_irq_disabled() function. This was all working fine while
the IRQ_NOAUTOEN flag was cleared.
With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.
This commit fixes that by using irqd_irq_disabled() only for global
interrupts, and using the newly introduced irq_percpu_is_enabled() for
per-CPU interrupts.
Also, it fixes a related problems that per-CPU interrupts were only
re-enabled on the boot CPU and not other CPUs. Until now this wasn't a
problem since on this platform, only the local timers are using per-CPU
interrupts and the local timers of secondary CPUs are turned off/on
during CPU hotplug before suspend, after after resume. However, since
Linux 4.4, we are also be using per-CPU interrupts for the network
controller, so we need to properly restore the per-CPU interrupts on
secondary CPUs as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-18 11:07:39 +03:00
|
|
|
static void armada_xp_mpic_reenable_percpu(void)
|
|
|
|
{
|
|
|
|
unsigned int irq;
|
|
|
|
|
|
|
|
/* Re-enable per-CPU interrupts that were enabled before suspend */
|
|
|
|
for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
|
|
|
|
struct irq_data *data;
|
|
|
|
int virq;
|
|
|
|
|
|
|
|
virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
|
|
|
|
if (virq == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
data = irq_get_irq_data(virq);
|
|
|
|
|
|
|
|
if (!irq_percpu_is_enabled(virq))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
armada_370_xp_irq_unmask(data);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-13 20:16:07 +03:00
|
|
|
static int armada_xp_mpic_starting_cpu(unsigned int cpu)
|
2014-04-14 17:54:02 +04:00
|
|
|
{
|
2016-07-13 20:16:07 +03:00
|
|
|
armada_xp_mpic_perf_init();
|
|
|
|
armada_xp_mpic_smp_cpu_init();
|
irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time
Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().
While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this commit:
the IRQ_NOAUTOEN flag is no longer cleared. This functional change
caused a regression on Armada XP, which no longer works properly after
suspend/resume because per-CPU interrupts remain disabled. This
regression was temporarly worked around in commit
353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing
IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit
implements the solution that was initially discussed with Thomas
Gleixner.
Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make sure
that the interrupts remain in the same state after resuming. Therefore,
it relies on the kernel to say whether the interrupt is disabled or not,
using the irqd_irq_disabled() function. This was all working fine while
the IRQ_NOAUTOEN flag was cleared.
With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.
This commit fixes that by using irqd_irq_disabled() only for global
interrupts, and using the newly introduced irq_percpu_is_enabled() for
per-CPU interrupts.
Also, it fixes a related problems that per-CPU interrupts were only
re-enabled on the boot CPU and not other CPUs. Until now this wasn't a
problem since on this platform, only the local timers are using per-CPU
interrupts and the local timers of secondary CPUs are turned off/on
during CPU hotplug before suspend, after after resume. However, since
Linux 4.4, we are also be using per-CPU interrupts for the network
controller, so we need to properly restore the per-CPU interrupts on
secondary CPUs as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-18 11:07:39 +03:00
|
|
|
armada_xp_mpic_reenable_percpu();
|
2016-07-13 20:16:07 +03:00
|
|
|
return 0;
|
2014-04-14 17:54:02 +04:00
|
|
|
}
|
|
|
|
|
2016-07-13 20:16:07 +03:00
|
|
|
static int mpic_cascaded_starting_cpu(unsigned int cpu)
|
irqchip: armada-370-xp: Fix chained per-cpu interrupts
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt
controller. Yet, it still has to handle some per-cpu interrupt.
To do so, it is chained with the GIC using a per-cpu interrupt. However, the
current code only call irq_set_chained_handler, which is called and enable that
interrupt only on the boot CPU, which means that the parent per-CPU interrupt
is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to
actually work as expected.
This was not seen until now since the only MPIC PPI users were the Marvell
timers that were not working, but not used either since the system use the ARM
TWD by default, and the ethernet controllers, that are faking there interrupts
as SPI, and don't really expect to have interrupts on the secondary cores
anyway.
Add a CPU notifier that will enable the PPI on the secondary cores when they
are brought up.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03 13:27:23 +03:00
|
|
|
{
|
2016-07-13 20:16:07 +03:00
|
|
|
armada_xp_mpic_perf_init();
|
irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time
Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().
While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this commit:
the IRQ_NOAUTOEN flag is no longer cleared. This functional change
caused a regression on Armada XP, which no longer works properly after
suspend/resume because per-CPU interrupts remain disabled. This
regression was temporarly worked around in commit
353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing
IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit
implements the solution that was initially discussed with Thomas
Gleixner.
Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make sure
that the interrupts remain in the same state after resuming. Therefore,
it relies on the kernel to say whether the interrupt is disabled or not,
using the irqd_irq_disabled() function. This was all working fine while
the IRQ_NOAUTOEN flag was cleared.
With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.
This commit fixes that by using irqd_irq_disabled() only for global
interrupts, and using the newly introduced irq_percpu_is_enabled() for
per-CPU interrupts.
Also, it fixes a related problems that per-CPU interrupts were only
re-enabled on the boot CPU and not other CPUs. Until now this wasn't a
problem since on this platform, only the local timers are using per-CPU
interrupts and the local timers of secondary CPUs are turned off/on
during CPU hotplug before suspend, after after resume. However, since
Linux 4.4, we are also be using per-CPU interrupts for the network
controller, so we need to properly restore the per-CPU interrupts on
secondary CPUs as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-18 11:07:39 +03:00
|
|
|
armada_xp_mpic_reenable_percpu();
|
2016-07-13 20:16:07 +03:00
|
|
|
enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
|
|
|
|
return 0;
|
irqchip: armada-370-xp: Fix chained per-cpu interrupts
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt
controller. Yet, it still has to handle some per-cpu interrupt.
To do so, it is chained with the GIC using a per-cpu interrupt. However, the
current code only call irq_set_chained_handler, which is called and enable that
interrupt only on the boot CPU, which means that the parent per-CPU interrupt
is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to
actually work as expected.
This was not seen until now since the only MPIC PPI users were the Marvell
timers that were not working, but not used either since the system use the ARM
TWD by default, and the ethernet controllers, that are faking there interrupts
as SPI, and don't really expect to have interrupts on the secondary cores
anyway.
Add a CPU notifier that will enable the PPI on the secondary cores when they
are brought up.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03 13:27:23 +03:00
|
|
|
}
|
2016-07-18 19:03:21 +03:00
|
|
|
#endif
|
2012-08-02 12:19:12 +04:00
|
|
|
|
2015-04-27 15:54:24 +03:00
|
|
|
static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
|
2012-06-13 21:01:28 +04:00
|
|
|
.map = armada_370_xp_mpic_irq_map,
|
|
|
|
.xlate = irq_domain_xlate_onecell,
|
|
|
|
};
|
|
|
|
|
2014-02-11 00:00:01 +04:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
2014-02-11 00:00:02 +04:00
|
|
|
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
|
2014-02-11 00:00:01 +04:00
|
|
|
{
|
|
|
|
u32 msimask, msinr;
|
|
|
|
|
|
|
|
msimask = readl_relaxed(per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
|
|
|
& PCI_MSI_DOORBELL_MASK;
|
|
|
|
|
|
|
|
writel(~msimask, per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
|
|
|
|
for (msinr = PCI_MSI_DOORBELL_START;
|
|
|
|
msinr < PCI_MSI_DOORBELL_END; msinr++) {
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
if (!(msimask & BIT(msinr)))
|
|
|
|
continue;
|
|
|
|
|
2014-08-26 14:03:21 +04:00
|
|
|
if (is_chained) {
|
2016-02-10 17:46:57 +03:00
|
|
|
irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
|
2016-02-10 17:46:58 +03:00
|
|
|
msinr - PCI_MSI_DOORBELL_START);
|
2014-02-11 00:00:02 +04:00
|
|
|
generic_handle_irq(irq);
|
2014-08-26 14:03:21 +04:00
|
|
|
} else {
|
2016-02-10 17:46:58 +03:00
|
|
|
irq = msinr - PCI_MSI_DOORBELL_START;
|
2016-02-10 17:46:57 +03:00
|
|
|
handle_domain_irq(armada_370_xp_msi_inner_domain,
|
2014-08-26 14:03:21 +04:00
|
|
|
irq, regs);
|
|
|
|
}
|
2014-02-11 00:00:01 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
2014-02-11 00:00:02 +04:00
|
|
|
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
|
2014-02-11 00:00:01 +04:00
|
|
|
#endif
|
|
|
|
|
2015-09-14 11:42:37 +03:00
|
|
|
static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
|
2014-02-11 00:00:02 +04:00
|
|
|
{
|
2015-06-04 07:13:20 +03:00
|
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
2014-09-25 15:17:19 +04:00
|
|
|
unsigned long irqmap, irqn, irqsrc, cpuid;
|
2014-02-11 00:00:02 +04:00
|
|
|
unsigned int cascade_irq;
|
|
|
|
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
|
|
|
|
irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
|
2014-09-25 15:17:19 +04:00
|
|
|
cpuid = cpu_logical_map(smp_processor_id());
|
2014-02-11 00:00:02 +04:00
|
|
|
|
|
|
|
for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
|
2014-09-25 15:17:19 +04:00
|
|
|
irqsrc = readl_relaxed(main_int_base +
|
|
|
|
ARMADA_370_XP_INT_SOURCE_CTL(irqn));
|
|
|
|
|
|
|
|
/* Check if the interrupt is not masked on current CPU.
|
|
|
|
* Test IRQ (0-1) and FIQ (8-9) mask bits.
|
|
|
|
*/
|
|
|
|
if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (irqn == 1) {
|
|
|
|
armada_370_xp_handle_msi_irq(NULL, true);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-02-11 00:00:02 +04:00
|
|
|
cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
|
|
|
|
generic_handle_irq(cascade_irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
chained_irq_exit(chip, desc);
|
|
|
|
}
|
|
|
|
|
2014-03-05 04:40:30 +04:00
|
|
|
static void __exception_irq_entry
|
2013-04-10 01:26:15 +04:00
|
|
|
armada_370_xp_handle_irq(struct pt_regs *regs)
|
2012-06-13 21:01:28 +04:00
|
|
|
{
|
|
|
|
u32 irqstat, irqnr;
|
|
|
|
|
|
|
|
do {
|
|
|
|
irqstat = readl_relaxed(per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_CPU_INTACK_OFFS);
|
|
|
|
irqnr = irqstat & 0x3FF;
|
|
|
|
|
2012-08-02 12:19:12 +04:00
|
|
|
if (irqnr > 1022)
|
|
|
|
break;
|
|
|
|
|
2013-08-10 00:27:11 +04:00
|
|
|
if (irqnr > 1) {
|
2014-08-26 14:03:21 +04:00
|
|
|
handle_domain_irq(armada_370_xp_mpic_domain,
|
|
|
|
irqnr, regs);
|
2012-06-13 21:01:28 +04:00
|
|
|
continue;
|
|
|
|
}
|
2013-08-10 00:27:11 +04:00
|
|
|
|
|
|
|
/* MSI handling */
|
2014-02-11 00:00:01 +04:00
|
|
|
if (irqnr == 1)
|
2014-02-11 00:00:02 +04:00
|
|
|
armada_370_xp_handle_msi_irq(regs, false);
|
2013-08-10 00:27:11 +04:00
|
|
|
|
2012-08-02 12:19:12 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/* IPI Handling */
|
|
|
|
if (irqnr == 0) {
|
|
|
|
u32 ipimask, ipinr;
|
|
|
|
|
|
|
|
ipimask = readl_relaxed(per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
2013-04-10 01:26:17 +04:00
|
|
|
& IPI_DOORBELL_MASK;
|
2012-08-02 12:19:12 +04:00
|
|
|
|
2013-11-25 20:26:44 +04:00
|
|
|
writel(~ipimask, per_cpu_int_base +
|
2012-08-02 12:19:12 +04:00
|
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
|
|
|
|
/* Handle all pending doorbells */
|
2013-04-10 01:26:17 +04:00
|
|
|
for (ipinr = IPI_DOORBELL_START;
|
|
|
|
ipinr < IPI_DOORBELL_END; ipinr++) {
|
2012-08-02 12:19:12 +04:00
|
|
|
if (ipimask & (0x1 << ipinr))
|
|
|
|
handle_IPI(ipinr, regs);
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
#endif
|
2012-06-13 21:01:28 +04:00
|
|
|
|
|
|
|
} while (1);
|
|
|
|
}
|
|
|
|
|
2014-11-21 19:00:00 +03:00
|
|
|
static int armada_370_xp_mpic_suspend(void)
|
|
|
|
{
|
|
|
|
doorbell_mask_reg = readl(per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void armada_370_xp_mpic_resume(void)
|
|
|
|
{
|
|
|
|
int nirqs;
|
|
|
|
irq_hw_number_t irq;
|
|
|
|
|
|
|
|
/* Re-enable interrupts */
|
|
|
|
nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
|
|
|
|
for (irq = 0; irq < nirqs; irq++) {
|
|
|
|
struct irq_data *data;
|
|
|
|
int virq;
|
|
|
|
|
|
|
|
virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
|
|
|
|
if (virq == 0)
|
|
|
|
continue;
|
|
|
|
|
irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time
Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().
While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this commit:
the IRQ_NOAUTOEN flag is no longer cleared. This functional change
caused a regression on Armada XP, which no longer works properly after
suspend/resume because per-CPU interrupts remain disabled. This
regression was temporarly worked around in commit
353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing
IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit
implements the solution that was initially discussed with Thomas
Gleixner.
Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make sure
that the interrupts remain in the same state after resuming. Therefore,
it relies on the kernel to say whether the interrupt is disabled or not,
using the irqd_irq_disabled() function. This was all working fine while
the IRQ_NOAUTOEN flag was cleared.
With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.
This commit fixes that by using irqd_irq_disabled() only for global
interrupts, and using the newly introduced irq_percpu_is_enabled() for
per-CPU interrupts.
Also, it fixes a related problems that per-CPU interrupts were only
re-enabled on the boot CPU and not other CPUs. Until now this wasn't a
problem since on this platform, only the local timers are using per-CPU
interrupts and the local timers of secondary CPUs are turned off/on
during CPU hotplug before suspend, after after resume. However, since
Linux 4.4, we are also be using per-CPU interrupts for the network
controller, so we need to properly restore the per-CPU interrupts on
secondary CPUs as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-18 11:07:39 +03:00
|
|
|
data = irq_get_irq_data(virq);
|
|
|
|
|
|
|
|
if (!is_percpu_irq(irq)) {
|
|
|
|
/* Non per-CPU interrupts */
|
2014-11-21 19:00:00 +03:00
|
|
|
writel(irq, per_cpu_int_base +
|
|
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time
Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().
While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this commit:
the IRQ_NOAUTOEN flag is no longer cleared. This functional change
caused a regression on Armada XP, which no longer works properly after
suspend/resume because per-CPU interrupts remain disabled. This
regression was temporarly worked around in commit
353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing
IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit
implements the solution that was initially discussed with Thomas
Gleixner.
Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make sure
that the interrupts remain in the same state after resuming. Therefore,
it relies on the kernel to say whether the interrupt is disabled or not,
using the irqd_irq_disabled() function. This was all working fine while
the IRQ_NOAUTOEN flag was cleared.
With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.
This commit fixes that by using irqd_irq_disabled() only for global
interrupts, and using the newly introduced irq_percpu_is_enabled() for
per-CPU interrupts.
Also, it fixes a related problems that per-CPU interrupts were only
re-enabled on the boot CPU and not other CPUs. Until now this wasn't a
problem since on this platform, only the local timers are using per-CPU
interrupts and the local timers of secondary CPUs are turned off/on
during CPU hotplug before suspend, after after resume. However, since
Linux 4.4, we are also be using per-CPU interrupts for the network
controller, so we need to properly restore the per-CPU interrupts on
secondary CPUs as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-18 11:07:39 +03:00
|
|
|
if (!irqd_irq_disabled(data))
|
|
|
|
armada_370_xp_irq_unmask(data);
|
|
|
|
} else {
|
|
|
|
/* Per-CPU interrupts */
|
2014-11-21 19:00:00 +03:00
|
|
|
writel(irq, main_int_base +
|
|
|
|
ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
|
|
|
irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time
Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().
While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this commit:
the IRQ_NOAUTOEN flag is no longer cleared. This functional change
caused a regression on Armada XP, which no longer works properly after
suspend/resume because per-CPU interrupts remain disabled. This
regression was temporarly worked around in commit
353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing
IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit
implements the solution that was initially discussed with Thomas
Gleixner.
Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make sure
that the interrupts remain in the same state after resuming. Therefore,
it relies on the kernel to say whether the interrupt is disabled or not,
using the irqd_irq_disabled() function. This was all working fine while
the IRQ_NOAUTOEN flag was cleared.
With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.
This commit fixes that by using irqd_irq_disabled() only for global
interrupts, and using the newly introduced irq_percpu_is_enabled() for
per-CPU interrupts.
Also, it fixes a related problems that per-CPU interrupts were only
re-enabled on the boot CPU and not other CPUs. Until now this wasn't a
problem since on this platform, only the local timers are using per-CPU
interrupts and the local timers of secondary CPUs are turned off/on
during CPU hotplug before suspend, after after resume. However, since
Linux 4.4, we are also be using per-CPU interrupts for the network
controller, so we need to properly restore the per-CPU interrupts on
secondary CPUs as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-18 11:07:39 +03:00
|
|
|
/*
|
|
|
|
* Re-enable on the current CPU,
|
|
|
|
* armada_xp_mpic_reenable_percpu() will take
|
|
|
|
* care of secondary CPUs when they come up.
|
|
|
|
*/
|
|
|
|
if (irq_percpu_is_enabled(virq))
|
|
|
|
armada_370_xp_irq_unmask(data);
|
|
|
|
}
|
2014-11-21 19:00:00 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Reconfigure doorbells for IPIs and MSIs */
|
|
|
|
writel(doorbell_mask_reg,
|
|
|
|
per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
if (doorbell_mask_reg & IPI_DOORBELL_MASK)
|
|
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
|
|
|
|
writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
}
|
|
|
|
|
2016-06-08 20:55:33 +03:00
|
|
|
static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
|
2014-11-21 19:00:00 +03:00
|
|
|
.suspend = armada_370_xp_mpic_suspend,
|
|
|
|
.resume = armada_370_xp_mpic_resume,
|
|
|
|
};
|
|
|
|
|
2013-04-10 01:26:16 +04:00
|
|
|
static int __init armada_370_xp_mpic_of_init(struct device_node *node,
|
|
|
|
struct device_node *parent)
|
2012-06-13 21:01:28 +04:00
|
|
|
{
|
2013-08-10 00:27:10 +04:00
|
|
|
struct resource main_int_res, per_cpu_int_res;
|
irqchip: armada-370-xp: Fix chained per-cpu interrupts
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt
controller. Yet, it still has to handle some per-cpu interrupt.
To do so, it is chained with the GIC using a per-cpu interrupt. However, the
current code only call irq_set_chained_handler, which is called and enable that
interrupt only on the boot CPU, which means that the parent per-CPU interrupt
is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to
actually work as expected.
This was not seen until now since the only MPIC PPI users were the Marvell
timers that were not working, but not used either since the system use the ARM
TWD by default, and the ethernet controllers, that are faking there interrupts
as SPI, and don't really expect to have interrupts on the secondary cores
anyway.
Add a CPU notifier that will enable the PPI on the secondary cores when they
are brought up.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03 13:27:23 +03:00
|
|
|
int nr_irqs, i;
|
2013-04-10 01:26:16 +04:00
|
|
|
u32 control;
|
|
|
|
|
2013-08-10 00:27:10 +04:00
|
|
|
BUG_ON(of_address_to_resource(node, 0, &main_int_res));
|
|
|
|
BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
|
2013-04-10 01:26:16 +04:00
|
|
|
|
2013-08-10 00:27:10 +04:00
|
|
|
BUG_ON(!request_mem_region(main_int_res.start,
|
|
|
|
resource_size(&main_int_res),
|
|
|
|
node->full_name));
|
|
|
|
BUG_ON(!request_mem_region(per_cpu_int_res.start,
|
|
|
|
resource_size(&per_cpu_int_res),
|
|
|
|
node->full_name));
|
|
|
|
|
|
|
|
main_int_base = ioremap(main_int_res.start,
|
|
|
|
resource_size(&main_int_res));
|
2013-04-10 01:26:16 +04:00
|
|
|
BUG_ON(!main_int_base);
|
2013-08-10 00:27:10 +04:00
|
|
|
|
|
|
|
per_cpu_int_base = ioremap(per_cpu_int_res.start,
|
|
|
|
resource_size(&per_cpu_int_res));
|
2013-04-10 01:26:16 +04:00
|
|
|
BUG_ON(!per_cpu_int_base);
|
|
|
|
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
2014-05-31 00:18:18 +04:00
|
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
|
|
writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
|
2013-04-10 01:26:16 +04:00
|
|
|
|
|
|
|
armada_370_xp_mpic_domain =
|
2014-05-31 00:18:18 +04:00
|
|
|
irq_domain_add_linear(node, nr_irqs,
|
2013-04-10 01:26:16 +04:00
|
|
|
&armada_370_xp_mpic_irq_ops, NULL);
|
2013-08-10 00:27:10 +04:00
|
|
|
BUG_ON(!armada_370_xp_mpic_domain);
|
2017-06-22 13:42:50 +03:00
|
|
|
irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
|
2013-04-10 01:26:16 +04:00
|
|
|
|
2015-03-03 13:43:14 +03:00
|
|
|
/* Setup for the boot CPU */
|
2015-03-03 13:43:16 +03:00
|
|
|
armada_xp_mpic_perf_init();
|
2013-04-10 01:26:16 +04:00
|
|
|
armada_xp_mpic_smp_cpu_init();
|
|
|
|
|
2013-08-10 00:27:11 +04:00
|
|
|
armada_370_xp_msi_init(node, main_int_res.start);
|
|
|
|
|
2014-02-11 00:00:02 +04:00
|
|
|
parent_irq = irq_of_parse_and_map(node, 0);
|
|
|
|
if (parent_irq <= 0) {
|
|
|
|
irq_set_default_host(armada_370_xp_mpic_domain);
|
|
|
|
set_handle_irq(armada_370_xp_handle_irq);
|
2014-04-14 17:54:01 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
set_smp_cross_call(armada_mpic_send_doorbell);
|
2016-07-13 20:16:07 +03:00
|
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
|
2016-12-21 22:19:54 +03:00
|
|
|
"irqchip/armada/ipi:starting",
|
2016-07-13 20:16:07 +03:00
|
|
|
armada_xp_mpic_starting_cpu, NULL);
|
2014-04-14 17:54:01 +04:00
|
|
|
#endif
|
2014-02-11 00:00:02 +04:00
|
|
|
} else {
|
irqchip: armada-370-xp: Fix chained per-cpu interrupts
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt
controller. Yet, it still has to handle some per-cpu interrupt.
To do so, it is chained with the GIC using a per-cpu interrupt. However, the
current code only call irq_set_chained_handler, which is called and enable that
interrupt only on the boot CPU, which means that the parent per-CPU interrupt
is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to
actually work as expected.
This was not seen until now since the only MPIC PPI users were the Marvell
timers that were not working, but not used either since the system use the ARM
TWD by default, and the ethernet controllers, that are faking there interrupts
as SPI, and don't really expect to have interrupts on the secondary cores
anyway.
Add a CPU notifier that will enable the PPI on the secondary cores when they
are brought up.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03 13:27:23 +03:00
|
|
|
#ifdef CONFIG_SMP
|
2016-12-21 22:19:57 +03:00
|
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
|
2016-12-21 22:19:54 +03:00
|
|
|
"irqchip/armada/cascade:starting",
|
2016-07-13 20:16:07 +03:00
|
|
|
mpic_cascaded_starting_cpu, NULL);
|
irqchip: armada-370-xp: Fix chained per-cpu interrupts
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt
controller. Yet, it still has to handle some per-cpu interrupt.
To do so, it is chained with the GIC using a per-cpu interrupt. However, the
current code only call irq_set_chained_handler, which is called and enable that
interrupt only on the boot CPU, which means that the parent per-CPU interrupt
is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to
actually work as expected.
This was not seen until now since the only MPIC PPI users were the Marvell
timers that were not working, but not used either since the system use the ARM
TWD by default, and the ethernet controllers, that are faking there interrupts
as SPI, and don't really expect to have interrupts on the secondary cores
anyway.
Add a CPU notifier that will enable the PPI on the secondary cores when they
are brought up.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03 13:27:23 +03:00
|
|
|
#endif
|
2014-02-11 00:00:02 +04:00
|
|
|
irq_set_chained_handler(parent_irq,
|
|
|
|
armada_370_xp_mpic_handle_cascade_irq);
|
|
|
|
}
|
2013-04-10 01:26:16 +04:00
|
|
|
|
2014-11-21 19:00:00 +03:00
|
|
|
register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
|
|
|
|
|
2013-04-10 01:26:16 +04:00
|
|
|
return 0;
|
2012-06-13 21:01:28 +04:00
|
|
|
}
|
2013-04-10 01:26:16 +04:00
|
|
|
|
2013-04-10 01:26:15 +04:00
|
|
|
IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
|