2012-10-31 13:41:15 +04:00
|
|
|
/*
|
|
|
|
* CPU idle driver for Tegra CPUs
|
|
|
|
*
|
|
|
|
* Copyright (c) 2010-2012, NVIDIA Corporation.
|
|
|
|
* Copyright (c) 2011 Google, Inc.
|
|
|
|
* Author: Colin Cross <ccross@android.com>
|
|
|
|
* Gary King <gking@nvidia.com>
|
|
|
|
*
|
|
|
|
* Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
* more details.
|
|
|
|
*/
|
|
|
|
|
2014-07-11 11:44:49 +04:00
|
|
|
#include <linux/clk/tegra.h>
|
2015-04-03 03:32:14 +03:00
|
|
|
#include <linux/tick.h>
|
2012-10-31 13:41:15 +04:00
|
|
|
#include <linux/cpuidle.h>
|
2013-01-16 02:10:38 +04:00
|
|
|
#include <linux/cpu_pm.h>
|
2014-07-11 11:44:49 +04:00
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/module.h>
|
2012-10-31 13:41:15 +04:00
|
|
|
|
2017-03-28 15:42:54 +03:00
|
|
|
#include <soc/tegra/flowctrl.h>
|
|
|
|
|
2012-10-31 13:41:15 +04:00
|
|
|
#include <asm/cpuidle.h>
|
2013-01-16 02:10:38 +04:00
|
|
|
#include <asm/smp_plat.h>
|
2014-07-11 11:44:49 +04:00
|
|
|
#include <asm/suspend.h>
|
2013-01-16 02:10:38 +04:00
|
|
|
|
2016-04-28 15:52:45 +03:00
|
|
|
#include "cpuidle.h"
|
2013-01-16 21:33:55 +04:00
|
|
|
#include "iomap.h"
|
|
|
|
#include "irq.h"
|
2014-07-11 11:44:49 +04:00
|
|
|
#include "pm.h"
|
2015-01-15 13:58:57 +03:00
|
|
|
#include "reset.h"
|
2014-07-11 11:44:49 +04:00
|
|
|
#include "sleep.h"
|
2013-01-16 02:10:38 +04:00
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2013-01-16 21:33:55 +04:00
|
|
|
static bool abort_flag;
|
|
|
|
static atomic_t abort_barrier;
|
|
|
|
static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
|
|
|
|
struct cpuidle_driver *drv,
|
|
|
|
int index);
|
2013-04-03 16:15:17 +04:00
|
|
|
#define TEGRA20_MAX_STATES 2
|
|
|
|
#else
|
|
|
|
#define TEGRA20_MAX_STATES 1
|
2013-01-16 02:10:38 +04:00
|
|
|
#endif
|
|
|
|
|
2012-10-31 13:41:15 +04:00
|
|
|
static struct cpuidle_driver tegra_idle_driver = {
|
|
|
|
.name = "tegra_idle",
|
|
|
|
.owner = THIS_MODULE,
|
2013-04-03 16:15:17 +04:00
|
|
|
.states = {
|
|
|
|
ARM_CPUIDLE_WFI_STATE_PWR(600),
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
{
|
|
|
|
.enter = tegra20_idle_lp2_coupled,
|
|
|
|
.exit_latency = 5000,
|
|
|
|
.target_residency = 10000,
|
|
|
|
.power_usage = 0,
|
2014-11-12 18:03:50 +03:00
|
|
|
.flags = CPUIDLE_FLAG_COUPLED,
|
2013-04-03 16:15:17 +04:00
|
|
|
.name = "powered-down",
|
|
|
|
.desc = "CPU power gated",
|
|
|
|
},
|
|
|
|
#endif
|
|
|
|
},
|
|
|
|
.state_count = TEGRA20_MAX_STATES,
|
|
|
|
.safe_state_index = 0,
|
2012-10-31 13:41:15 +04:00
|
|
|
};
|
|
|
|
|
2013-01-16 02:10:38 +04:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2013-01-16 21:33:55 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static int tegra20_reset_sleeping_cpu_1(void)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
tegra_pen_lock();
|
|
|
|
|
2015-01-15 13:58:57 +03:00
|
|
|
if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
|
2013-01-16 21:33:55 +04:00
|
|
|
tegra20_cpu_shutdown(1);
|
|
|
|
else
|
|
|
|
ret = -EINVAL;
|
|
|
|
|
|
|
|
tegra_pen_unlock();
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra20_wake_cpu1_from_reset(void)
|
|
|
|
{
|
|
|
|
tegra_pen_lock();
|
|
|
|
|
|
|
|
tegra20_cpu_clear_resettable();
|
|
|
|
|
|
|
|
/* enable cpu clock on cpu */
|
|
|
|
tegra_enable_cpu_clock(1);
|
|
|
|
|
|
|
|
/* take the CPU out of reset */
|
|
|
|
tegra_cpu_out_of_reset(1);
|
|
|
|
|
|
|
|
/* unhalt the cpu */
|
|
|
|
flowctrl_write_cpu_halt(1, 0);
|
|
|
|
|
|
|
|
tegra_pen_unlock();
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra20_reset_cpu_1(void)
|
|
|
|
{
|
|
|
|
if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
tegra20_wake_cpu1_from_reset();
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void tegra20_wake_cpu1_from_reset(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int tegra20_reset_cpu_1(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
|
|
|
|
struct cpuidle_driver *drv,
|
|
|
|
int index)
|
|
|
|
{
|
|
|
|
while (tegra20_cpu_is_resettable_soon())
|
|
|
|
cpu_relax();
|
|
|
|
|
|
|
|
if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
|
|
|
|
return false;
|
|
|
|
|
2015-04-03 03:32:14 +03:00
|
|
|
tick_broadcast_enter();
|
2013-01-16 21:33:55 +04:00
|
|
|
|
2013-04-02 05:20:50 +04:00
|
|
|
tegra_idle_lp2_last();
|
2013-01-16 21:33:55 +04:00
|
|
|
|
2015-04-03 03:32:14 +03:00
|
|
|
tick_broadcast_exit();
|
2013-01-16 21:33:55 +04:00
|
|
|
|
|
|
|
if (cpu_online(1))
|
|
|
|
tegra20_wake_cpu1_from_reset();
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-01-16 02:10:38 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
|
|
|
|
struct cpuidle_driver *drv,
|
|
|
|
int index)
|
|
|
|
{
|
2015-04-03 03:32:14 +03:00
|
|
|
tick_broadcast_enter();
|
2013-01-16 02:10:38 +04:00
|
|
|
|
|
|
|
cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
|
|
|
|
|
|
|
|
tegra20_cpu_clear_resettable();
|
|
|
|
|
2015-04-03 03:32:14 +03:00
|
|
|
tick_broadcast_exit();
|
2013-01-16 02:10:38 +04:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
|
|
|
|
struct cpuidle_driver *drv,
|
|
|
|
int index)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-01-16 21:33:55 +04:00
|
|
|
static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
|
|
|
|
struct cpuidle_driver *drv,
|
|
|
|
int index)
|
2013-01-16 02:10:38 +04:00
|
|
|
{
|
|
|
|
bool entered_lp2 = false;
|
|
|
|
|
2013-01-16 21:33:55 +04:00
|
|
|
if (tegra_pending_sgi())
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 00:07:29 +03:00
|
|
|
WRITE_ONCE(abort_flag, true);
|
2013-01-16 21:33:55 +04:00
|
|
|
|
|
|
|
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
|
|
|
|
|
|
|
|
if (abort_flag) {
|
|
|
|
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
|
|
|
|
abort_flag = false; /* clean flag for next coming */
|
|
|
|
return -EINTR;
|
|
|
|
}
|
|
|
|
|
2013-01-16 02:10:38 +04:00
|
|
|
local_fiq_disable();
|
|
|
|
|
2013-06-04 14:47:35 +04:00
|
|
|
tegra_set_cpu_in_lp2();
|
2013-01-16 02:10:38 +04:00
|
|
|
cpu_pm_enter();
|
|
|
|
|
2013-06-04 14:47:35 +04:00
|
|
|
if (dev->cpu == 0)
|
2013-01-16 21:33:55 +04:00
|
|
|
entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
|
2013-01-16 02:10:38 +04:00
|
|
|
else
|
|
|
|
entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
|
|
|
|
|
|
|
|
cpu_pm_exit();
|
2013-06-04 14:47:35 +04:00
|
|
|
tegra_clear_cpu_in_lp2();
|
2013-01-16 02:10:38 +04:00
|
|
|
|
|
|
|
local_fiq_enable();
|
|
|
|
|
|
|
|
smp_rmb();
|
|
|
|
|
|
|
|
return entered_lp2 ? index : 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-05-07 00:19:19 +04:00
|
|
|
/*
|
|
|
|
* Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
|
|
|
|
* they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
|
|
|
|
* this, simply disable LP2 if the PCI driver and DT node are both enabled.
|
|
|
|
*/
|
|
|
|
void tegra20_cpuidle_pcie_irqs_in_use(void)
|
|
|
|
{
|
|
|
|
pr_info_once(
|
|
|
|
"Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
|
|
|
|
tegra_idle_driver.states[1].disabled = true;
|
|
|
|
}
|
|
|
|
|
2012-10-31 13:41:15 +04:00
|
|
|
int __init tegra20_cpuidle_init(void)
|
|
|
|
{
|
2013-04-23 12:54:40 +04:00
|
|
|
return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
|
2012-10-31 13:41:15 +04:00
|
|
|
}
|