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WSL2-Linux-Kernel
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WSL2-Linux-Kernel/drivers/clk/tegra/clk-id.h

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clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
/*
* This header provides IDs for clocks common between several Tegra SoCs
*/
#ifndef _TEGRA_CLK_ID_H
#define _TEGRA_CLK_ID_H
enum clk_id {
tegra_clk_actmon,
tegra_clk_adx,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_adx1,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_afi,
tegra_clk_amx,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_amx1,
clk: tegra: Add the APB2APE audio clock on Tegra210 The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-28 19:33:50 +03:00
tegra_clk_apb2ape,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_apbdma,
tegra_clk_apbif,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_ape,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_audio0,
tegra_clk_audio0_2x,
tegra_clk_audio0_mux,
tegra_clk_audio1,
tegra_clk_audio1_2x,
tegra_clk_audio1_mux,
tegra_clk_audio2,
tegra_clk_audio2_2x,
tegra_clk_audio2_mux,
tegra_clk_audio3,
tegra_clk_audio3_2x,
tegra_clk_audio3_mux,
tegra_clk_audio4,
tegra_clk_audio4_2x,
tegra_clk_audio4_mux,
tegra_clk_blink,
tegra_clk_bsea,
tegra_clk_bsev,
tegra_clk_cclk_g,
tegra_clk_cclk_lp,
tegra_clk_cilab,
tegra_clk_cilcd,
tegra_clk_cile,
tegra_clk_clk_32k,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_clk72Mhz,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_clk72Mhz_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_clk_m,
tegra_clk_clk_m_div2,
tegra_clk_clk_m_div4,
tegra_clk_clk_out_1,
tegra_clk_clk_out_1_mux,
tegra_clk_clk_out_2,
tegra_clk_clk_out_2_mux,
tegra_clk_clk_out_3,
tegra_clk_clk_out_3_mux,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_cml0,
tegra_clk_cml1,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_csi,
tegra_clk_csite,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_csite_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_csus,
tegra_clk_cve,
tegra_clk_dam0,
tegra_clk_dam1,
tegra_clk_dam2,
tegra_clk_d_audio,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_dbgapb,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_dds,
tegra_clk_dfll_ref,
tegra_clk_dfll_soc,
tegra_clk_disp1,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_disp1_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_disp2,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_disp2_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_dp2,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_dpaux,
clk: tegra: Add dpaux1 clock This clock is of the same type as dpaux and is added to feed into the second DPAUX block used in conjunction with SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-20 16:05:33 +03:00
tegra_clk_dpaux1,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_dsialp,
tegra_clk_dsia_mux,
tegra_clk_dsiblp,
tegra_clk_dsib_mux,
tegra_clk_dtv,
tegra_clk_emc,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_entropy,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_entropy_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_epp,
tegra_clk_epp_8,
tegra_clk_extern1,
tegra_clk_extern2,
tegra_clk_extern3,
tegra_clk_fuse,
tegra_clk_fuse_burn,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_gpu,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_gr2d,
tegra_clk_gr2d_8,
tegra_clk_gr3d,
tegra_clk_gr3d_8,
tegra_clk_hclk,
tegra_clk_hda,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_hda_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_hda2codec_2x,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_hda2codec_2x_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_hda2hdmi,
tegra_clk_hdmi,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_hdmi_audio,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_host1x,
tegra_clk_host1x_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_host1x_9,
tegra_clk_hsic_trk,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_i2c1,
tegra_clk_i2c2,
tegra_clk_i2c3,
tegra_clk_i2c4,
tegra_clk_i2c5,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_i2c6,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_i2cslow,
tegra_clk_i2s0,
tegra_clk_i2s0_sync,
tegra_clk_i2s1,
tegra_clk_i2s1_sync,
tegra_clk_i2s2,
tegra_clk_i2s2_sync,
tegra_clk_i2s3,
tegra_clk_i2s3_sync,
tegra_clk_i2s4,
tegra_clk_i2s4_sync,
tegra_clk_isp,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_isp_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_isp_9,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_ispb,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_kbc,
tegra_clk_kfuse,
tegra_clk_la,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_maud,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_mipi,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_mipibif,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_mipi_cal,
tegra_clk_mpe,
tegra_clk_mselect,
tegra_clk_msenc,
tegra_clk_ndflash,
tegra_clk_ndflash_8,
tegra_clk_ndspeed,
tegra_clk_ndspeed_8,
tegra_clk_nor,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_nvdec,
tegra_clk_nvenc,
tegra_clk_nvjpg,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_owr,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_owr_8,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_pcie,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pclk,
tegra_clk_pll_a,
tegra_clk_pll_a_out0,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_pll_a1,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_c,
tegra_clk_pll_c2,
tegra_clk_pll_c3,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_pll_c4,
clk: tegra: Add support for Tegra210 clocks Implement clock support for Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:36 +03:00
tegra_clk_pll_c4_out0,
tegra_clk_pll_c4_out1,
tegra_clk_pll_c4_out2,
tegra_clk_pll_c4_out3,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_c_out1,
tegra_clk_pll_d,
tegra_clk_pll_d2,
tegra_clk_pll_d2_out0,
tegra_clk_pll_d_out0,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_pll_dp,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_e_out0,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_pll_g_ref,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_m,
tegra_clk_pll_m_out1,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_pll_mb,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_p,
tegra_clk_pll_p_out1,
tegra_clk_pll_p_out2,
tegra_clk_pll_p_out2_int,
tegra_clk_pll_p_out3,
tegra_clk_pll_p_out4,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_pll_p_out4_cpu,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_pll_p_out5,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_pll_p_out_hsio,
tegra_clk_pll_p_out_xusb,
tegra_clk_pll_p_out_cpu,
tegra_clk_pll_p_out_adsp,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_ref,
tegra_clk_pll_re_out,
tegra_clk_pll_re_vco,
tegra_clk_pll_u,
clk: tegra: Add support for Tegra210 clocks Implement clock support for Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:36 +03:00
tegra_clk_pll_u_out,
tegra_clk_pll_u_out1,
tegra_clk_pll_u_out2,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_pll_u_12m,
tegra_clk_pll_u_480m,
tegra_clk_pll_u_48m,
tegra_clk_pll_u_60m,
tegra_clk_pll_x,
tegra_clk_pll_x_out0,
tegra_clk_pwm,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_qspi,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_rtc,
tegra_clk_sata,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sata_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sata_cold,
tegra_clk_sata_oob,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sata_oob_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sbc1,
tegra_clk_sbc1_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sbc1_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sbc2,
tegra_clk_sbc2_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sbc2_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sbc3,
tegra_clk_sbc3_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sbc3_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sbc4,
tegra_clk_sbc4_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sbc4_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sbc5,
tegra_clk_sbc5_8,
tegra_clk_sbc6,
tegra_clk_sbc6_8,
tegra_clk_sclk,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sdmmc_legacy,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sdmmc1,
clk: tegra: fix sdmmc clks on Tegra1x4 The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2013-12-27 04:44:25 +04:00
tegra_clk_sdmmc1_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sdmmc1_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sdmmc2,
clk: tegra: fix sdmmc clks on Tegra1x4 The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2013-12-27 04:44:25 +04:00
tegra_clk_sdmmc2_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sdmmc2_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sdmmc3,
clk: tegra: fix sdmmc clks on Tegra1x4 The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2013-12-27 04:44:25 +04:00
tegra_clk_sdmmc3_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sdmmc3_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_sdmmc4,
clk: tegra: fix sdmmc clks on Tegra1x4 The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2013-12-27 04:44:25 +04:00
tegra_clk_sdmmc4_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sdmmc4_9,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_se,
tegra_clk_soc_therm,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_soc_therm_8,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_sor0,
tegra_clk_sor0_lvds,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_sor1,
tegra_clk_sor1_src,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_spdif,
tegra_clk_spdif_2x,
tegra_clk_spdif_in,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_spdif_in_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_spdif_in_sync,
tegra_clk_spdif_mux,
tegra_clk_spdif_out,
tegra_clk_timer,
tegra_clk_trace,
tegra_clk_tsec,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_tsec_8,
tegra_clk_tsecb,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_tsensor,
tegra_clk_tvdac,
tegra_clk_tvo,
tegra_clk_uarta,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_uarta_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_uartb,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_uartb_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_uartc,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_uartc_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_uartd,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_uartd_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_uarte,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_uarte_8,
tegra_clk_uartape,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_usb2,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_usb2_hsic_trk,
tegra_clk_usb2_trk,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_usb3,
tegra_clk_usbd,
tegra_clk_vcp,
tegra_clk_vde,
tegra_clk_vde_8,
tegra_clk_vfir,
tegra_clk_vi,
tegra_clk_vi_8,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_vi_9,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_vi_10,
tegra_clk_vi_i2c,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_vic03,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_vic03_8,
clk: tegra124: Add common clk IDs to clk-id.h Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-10-14 19:52:25 +04:00
tegra_clk_vim2_clk,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_vimclk_sync,
tegra_clk_vi_sensor,
tegra_clk_vi_sensor_8,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_vi_sensor_9,
tegra_clk_vi_sensor2,
tegra_clk_vi_sensor2_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_xusb_dev,
tegra_clk_xusb_dev_src,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_dev_src_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_xusb_falcon_src,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_falcon_src_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_xusb_fs_src,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_gate,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_xusb_host,
tegra_clk_xusb_host_src,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_host_src_8,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_xusb_hs_src,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_hs_src_4,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_xusb_ss,
tegra_clk_xusb_ss_src,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_ss_src_8,
clk: tegra: Fix xusb_hs_src clock hierarchy Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-15 04:32:59 +04:00
tegra_clk_xusb_ss_div2,
clk: tegra: periph: Add new periph clks and muxes for Tegra210 Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-19 00:28:18 +03:00
tegra_clk_xusb_ssp_src,
tegra_clk_sclk_mux,
clk: tegra: Add sor_safe clock The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It has a gate bit in the peripheral clock registers. While the SOR is being powered up, sor_safe can be used as the source until the SOR brick can generate its own clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-20 16:13:36 +03:00
tegra_clk_sor_safe,
clk: tegra: Fix ISP clock modelling The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-02-23 13:44:39 +03:00
tegra_clk_ispa,
clk: tegra: Add CEC clock This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-02-28 17:37:17 +03:00
tegra_clk_cec,
clk: tegra: Define Tegra210 DMIC sync clocks Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add a 3 new clocks similar to the audio* clocks which handle the same function for the I2S and SPDIF clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-02-28 17:37:18 +03:00
tegra_clk_dmic1_sync_clk,
tegra_clk_dmic2_sync_clk,
tegra_clk_dmic3_sync_clk,
tegra_clk_dmic1_sync_clk_mux,
tegra_clk_dmic2_sync_clk_mux,
tegra_clk_dmic3_sync_clk_mux,
clk: tegra: add header for common tegra clock IDs Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-09-02 16:09:08 +04:00
tegra_clk_max,
};
#endif /* _TEGRA_CLK_ID_H */