2019-05-19 15:08:20 +03:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-11-24 12:17:14 +03:00
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/*
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2021-05-17 17:03:49 +03:00
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* PCI glue driver for SPI PXA2xx compatible controllers.
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* CE4100's SPI device is more or less the same one as found on PXA.
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2010-11-24 12:17:14 +03:00
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*
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2021-05-17 17:03:49 +03:00
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* Copyright (C) 2016, 2021 Intel Corporation
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2010-11-24 12:17:14 +03:00
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*/
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2016-07-04 12:44:27 +03:00
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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2010-11-24 12:17:14 +03:00
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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2021-04-23 21:24:31 +03:00
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2010-11-24 12:17:14 +03:00
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#include <linux/spi/pxa2xx_spi.h>
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2014-08-19 21:29:19 +04:00
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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2022-02-25 20:23:46 +03:00
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000 0x0935
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#define PCI_DEVICE_ID_INTEL_BYT 0x0f0e
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#define PCI_DEVICE_ID_INTEL_MRFLD 0x1194
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#define PCI_DEVICE_ID_INTEL_BSW0 0x228e
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#define PCI_DEVICE_ID_INTEL_BSW1 0x2290
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#define PCI_DEVICE_ID_INTEL_BSW2 0x22ac
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#define PCI_DEVICE_ID_INTEL_CE4100 0x2e6a
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#define PCI_DEVICE_ID_INTEL_LPT0_0 0x9c65
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#define PCI_DEVICE_ID_INTEL_LPT0_1 0x9c66
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#define PCI_DEVICE_ID_INTEL_LPT1_0 0x9ce5
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#define PCI_DEVICE_ID_INTEL_LPT1_1 0x9ce6
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2014-04-17 20:26:06 +04:00
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struct pxa_spi_info {
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2022-02-25 20:23:49 +03:00
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int (*setup)(struct pci_dev *pdev, struct pxa2xx_spi_controller *c);
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2014-04-17 20:26:06 +04:00
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};
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2014-08-19 21:29:19 +04:00
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static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
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static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
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2017-01-02 14:47:31 +03:00
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static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
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static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
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static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
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static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
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static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
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static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
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2014-08-19 21:29:21 +04:00
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static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
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static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
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static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
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static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
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static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
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static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
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2021-02-08 19:38:15 +03:00
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static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
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static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
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static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
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static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
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2016-02-20 22:20:22 +03:00
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2022-02-25 20:23:48 +03:00
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static void pxa2xx_spi_pci_clk_unregister(void *clk)
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{
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clk_unregister(clk);
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}
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static int pxa2xx_spi_pci_clk_register(struct pci_dev *dev, struct ssp_device *ssp,
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unsigned long rate)
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{
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char buf[40];
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snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
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ssp->clk = clk_register_fixed_rate(&dev->dev, buf, NULL, 0, rate);
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if (IS_ERR(ssp->clk))
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return PTR_ERR(ssp->clk);
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return devm_add_action_or_reset(&dev->dev, pxa2xx_spi_pci_clk_unregister, ssp->clk);
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}
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2014-08-19 21:29:19 +04:00
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static bool lpss_dma_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_slave *dws = param;
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if (dws->dma_dev != chan->device->dev)
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return false;
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chan->private = dws;
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return true;
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}
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2022-02-23 22:16:37 +03:00
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static void lpss_dma_put_device(void *dma_dev)
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{
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pci_dev_put(dma_dev);
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}
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2022-02-25 20:23:49 +03:00
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static int lpss_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
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2016-07-04 12:44:24 +03:00
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{
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2022-02-25 20:23:49 +03:00
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struct ssp_device *ssp = &c->ssp;
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2022-02-25 20:23:47 +03:00
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struct dw_dma_slave *tx, *rx;
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2016-07-04 12:44:24 +03:00
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struct pci_dev *dma_dev;
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2022-02-23 22:16:37 +03:00
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int ret;
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2016-07-04 12:44:24 +03:00
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2022-02-25 20:23:46 +03:00
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switch (dev->device) {
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case PCI_DEVICE_ID_INTEL_BYT:
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2022-02-25 20:23:49 +03:00
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ssp->type = LPSS_BYT_SSP;
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ssp->port_id = 0;
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2022-02-25 20:23:46 +03:00
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c->tx_param = &byt_tx_param;
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c->rx_param = &byt_rx_param;
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break;
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case PCI_DEVICE_ID_INTEL_BSW0:
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2022-02-25 20:23:49 +03:00
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ssp->type = LPSS_BSW_SSP;
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ssp->port_id = 0;
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2022-02-25 20:23:46 +03:00
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c->tx_param = &bsw0_tx_param;
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c->rx_param = &bsw0_rx_param;
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break;
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case PCI_DEVICE_ID_INTEL_BSW1:
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2022-02-25 20:23:49 +03:00
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ssp->type = LPSS_BSW_SSP;
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ssp->port_id = 1;
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2022-02-25 20:23:46 +03:00
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c->tx_param = &bsw1_tx_param;
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c->rx_param = &bsw1_rx_param;
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break;
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case PCI_DEVICE_ID_INTEL_BSW2:
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2022-02-25 20:23:49 +03:00
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ssp->type = LPSS_BSW_SSP;
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ssp->port_id = 2;
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2022-02-25 20:23:46 +03:00
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c->tx_param = &bsw2_tx_param;
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c->rx_param = &bsw2_rx_param;
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break;
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case PCI_DEVICE_ID_INTEL_LPT0_0:
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case PCI_DEVICE_ID_INTEL_LPT1_0:
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2022-02-25 20:23:49 +03:00
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ssp->type = LPSS_LPT_SSP;
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ssp->port_id = 0;
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2022-02-25 20:23:46 +03:00
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c->tx_param = &lpt0_tx_param;
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c->rx_param = &lpt0_rx_param;
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break;
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case PCI_DEVICE_ID_INTEL_LPT0_1:
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case PCI_DEVICE_ID_INTEL_LPT1_1:
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2022-02-25 20:23:49 +03:00
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ssp->type = LPSS_LPT_SSP;
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ssp->port_id = 1;
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2022-02-25 20:23:46 +03:00
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c->tx_param = &lpt1_tx_param;
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c->rx_param = &lpt1_rx_param;
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break;
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default:
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return -ENODEV;
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}
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2016-07-04 12:44:24 +03:00
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c->num_chipselect = 1;
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2022-02-25 20:23:49 +03:00
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ret = pxa2xx_spi_pci_clk_register(dev, ssp, 50000000);
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if (ret)
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return ret;
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2016-07-04 12:44:24 +03:00
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dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
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2022-02-23 22:16:37 +03:00
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ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev);
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if (ret)
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return ret;
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2016-07-04 12:44:24 +03:00
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2022-02-25 20:23:47 +03:00
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tx = c->tx_param;
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tx->dma_dev = &dma_dev->dev;
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tx->m_master = 0;
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tx->p_master = 1;
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2016-07-04 12:44:24 +03:00
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2022-02-25 20:23:47 +03:00
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rx = c->rx_param;
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rx->dma_dev = &dma_dev->dev;
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rx->m_master = 0;
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rx->p_master = 1;
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2016-07-04 12:44:24 +03:00
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c->dma_filter = lpss_dma_filter;
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2022-02-25 20:23:44 +03:00
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c->dma_burst_size = 1;
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2022-02-25 20:23:49 +03:00
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c->enable_dma = 1;
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2016-07-04 12:44:24 +03:00
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return 0;
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}
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2022-02-25 20:23:50 +03:00
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static const struct pxa_spi_info lpss_info_config = {
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2022-02-25 20:23:46 +03:00
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.setup = lpss_spi_setup,
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};
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2022-02-25 20:23:49 +03:00
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static int ce4100_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
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2022-02-25 20:23:40 +03:00
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{
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2022-02-25 20:23:49 +03:00
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struct ssp_device *ssp = &c->ssp;
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ssp->type = PXA25x_SSP;
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ssp->port_id = dev->devfn;
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2022-02-25 20:23:40 +03:00
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c->num_chipselect = dev->devfn;
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2022-02-25 20:23:49 +03:00
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return pxa2xx_spi_pci_clk_register(dev, ssp, 3686400);
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2022-02-25 20:23:40 +03:00
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}
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2022-02-25 20:23:50 +03:00
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static const struct pxa_spi_info ce4100_info_config = {
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2022-02-25 20:23:46 +03:00
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.setup = ce4100_spi_setup,
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};
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2022-02-25 20:23:49 +03:00
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static int mrfld_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
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2016-07-04 12:44:25 +03:00
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{
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2022-02-25 20:23:49 +03:00
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struct ssp_device *ssp = &c->ssp;
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2017-01-02 14:47:31 +03:00
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struct dw_dma_slave *tx, *rx;
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2022-02-23 22:16:37 +03:00
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struct pci_dev *dma_dev;
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int ret;
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2017-01-02 14:47:31 +03:00
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2022-02-25 20:23:49 +03:00
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ssp->type = MRFLD_SSP;
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2016-07-04 12:44:25 +03:00
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switch (PCI_FUNC(dev->devfn)) {
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case 0:
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2022-02-25 20:23:49 +03:00
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ssp->port_id = 3;
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2016-07-04 12:44:25 +03:00
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c->num_chipselect = 1;
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2017-01-02 14:47:31 +03:00
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c->tx_param = &mrfld3_tx_param;
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c->rx_param = &mrfld3_rx_param;
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2016-07-04 12:44:25 +03:00
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break;
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case 1:
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2022-02-25 20:23:49 +03:00
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ssp->port_id = 5;
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2016-07-04 12:44:25 +03:00
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c->num_chipselect = 4;
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2017-01-02 14:47:31 +03:00
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c->tx_param = &mrfld5_tx_param;
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c->rx_param = &mrfld5_rx_param;
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2016-07-04 12:44:25 +03:00
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break;
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case 2:
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2022-02-25 20:23:49 +03:00
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ssp->port_id = 6;
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2016-07-04 12:44:25 +03:00
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c->num_chipselect = 1;
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2017-01-02 14:47:31 +03:00
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c->tx_param = &mrfld6_tx_param;
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c->rx_param = &mrfld6_rx_param;
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2016-07-04 12:44:25 +03:00
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break;
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default:
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return -ENODEV;
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}
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2017-01-02 14:47:31 +03:00
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2022-02-25 20:23:49 +03:00
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ret = pxa2xx_spi_pci_clk_register(dev, ssp, 25000000);
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if (ret)
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return ret;
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2022-02-25 20:23:45 +03:00
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2022-02-23 22:16:37 +03:00
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dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
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ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev);
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if (ret)
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return ret;
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2017-01-02 14:47:31 +03:00
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tx = c->tx_param;
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tx->dma_dev = &dma_dev->dev;
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rx = c->rx_param;
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rx->dma_dev = &dma_dev->dev;
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c->dma_filter = lpss_dma_filter;
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2019-03-19 18:48:42 +03:00
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c->dma_burst_size = 8;
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2022-02-25 20:23:49 +03:00
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c->enable_dma = 1;
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2016-07-04 12:44:25 +03:00
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return 0;
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}
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2022-02-25 20:23:50 +03:00
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static const struct pxa_spi_info mrfld_info_config = {
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2022-02-25 20:23:46 +03:00
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.setup = mrfld_spi_setup,
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};
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2022-02-25 20:23:49 +03:00
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static int qrk_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
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2022-02-25 20:23:41 +03:00
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{
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2022-02-25 20:23:49 +03:00
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struct ssp_device *ssp = &c->ssp;
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ssp->type = QUARK_X1000_SSP;
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ssp->port_id = dev->devfn;
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2022-02-25 20:23:41 +03:00
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c->num_chipselect = 1;
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2022-02-25 20:23:49 +03:00
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return pxa2xx_spi_pci_clk_register(dev, ssp, 50000000);
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2022-02-25 20:23:41 +03:00
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}
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2022-02-25 20:23:50 +03:00
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static const struct pxa_spi_info qrk_info_config = {
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2022-02-25 20:23:46 +03:00
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.setup = qrk_spi_setup,
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2014-04-17 20:26:06 +04:00
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};
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static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
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2010-11-24 12:17:14 +03:00
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const struct pci_device_id *ent)
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{
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2022-02-25 20:23:50 +03:00
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const struct pxa_spi_info *info;
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2013-01-07 14:44:32 +04:00
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struct platform_device_info pi;
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2010-11-24 12:17:14 +03:00
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int ret;
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struct platform_device *pdev;
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2019-01-16 18:13:31 +03:00
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struct pxa2xx_spi_controller spi_pdata;
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2010-11-24 12:17:14 +03:00
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struct ssp_device *ssp;
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2013-01-07 14:44:32 +04:00
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ret = pcim_enable_device(dev);
|
2010-11-24 12:17:14 +03:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-01-07 14:44:32 +04:00
|
|
|
ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
|
2013-03-05 14:05:16 +04:00
|
|
|
if (ret)
|
2010-11-24 12:17:14 +03:00
|
|
|
return ret;
|
|
|
|
|
2016-07-04 12:44:24 +03:00
|
|
|
memset(&spi_pdata, 0, sizeof(spi_pdata));
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2013-01-07 14:44:33 +04:00
|
|
|
ssp = &spi_pdata.ssp;
|
2021-04-23 21:24:30 +03:00
|
|
|
ssp->dev = &dev->dev;
|
2010-11-24 12:17:14 +03:00
|
|
|
ssp->phys_base = pci_resource_start(dev, 0);
|
2013-01-07 14:44:32 +04:00
|
|
|
ssp->mmio_base = pcim_iomap_table(dev)[0];
|
2022-02-25 20:23:49 +03:00
|
|
|
|
|
|
|
info = (struct pxa_spi_info *)ent->driver_data;
|
|
|
|
ret = info->setup(dev, &spi_pdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2017-01-21 12:06:39 +03:00
|
|
|
pci_set_master(dev);
|
|
|
|
|
|
|
|
ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
ssp->irq = pci_irq_vector(dev, 0);
|
|
|
|
|
2013-01-07 14:44:32 +04:00
|
|
|
memset(&pi, 0, sizeof(pi));
|
2022-02-23 22:19:48 +03:00
|
|
|
pi.fwnode = dev_fwnode(&dev->dev);
|
2013-01-07 14:44:32 +04:00
|
|
|
pi.parent = &dev->dev;
|
|
|
|
pi.name = "pxa2xx-spi";
|
|
|
|
pi.id = ssp->port_id;
|
|
|
|
pi.data = &spi_pdata;
|
|
|
|
pi.size_data = sizeof(spi_pdata);
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2013-01-07 14:44:32 +04:00
|
|
|
pdev = platform_device_register_full(&pi);
|
2022-02-25 20:23:48 +03:00
|
|
|
if (IS_ERR(pdev))
|
2013-02-22 06:52:35 +04:00
|
|
|
return PTR_ERR(pdev);
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2013-01-07 14:44:33 +04:00
|
|
|
pci_set_drvdata(dev, pdev);
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2013-01-07 14:44:32 +04:00
|
|
|
return 0;
|
2010-11-24 12:17:14 +03:00
|
|
|
}
|
|
|
|
|
2014-04-17 20:26:06 +04:00
|
|
|
static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
|
2010-11-24 12:17:14 +03:00
|
|
|
{
|
2013-01-07 14:44:33 +04:00
|
|
|
struct platform_device *pdev = pci_get_drvdata(dev);
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2013-01-07 14:44:33 +04:00
|
|
|
platform_device_unregister(pdev);
|
2010-11-24 12:17:14 +03:00
|
|
|
}
|
|
|
|
|
2014-04-17 20:26:06 +04:00
|
|
|
static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
|
2022-02-25 20:23:46 +03:00
|
|
|
{ PCI_DEVICE_DATA(INTEL, QUARK_X1000, &qrk_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, BYT, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, MRFLD, &mrfld_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, BSW0, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, BSW1, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, BSW2, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, CE4100, &ce4100_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, LPT0_0, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, LPT0_1, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, LPT1_0, &lpss_info_config) },
|
|
|
|
{ PCI_DEVICE_DATA(INTEL, LPT1_1, &lpss_info_config) },
|
2021-02-08 19:38:15 +03:00
|
|
|
{ }
|
2010-11-24 12:17:14 +03:00
|
|
|
};
|
2014-04-17 20:26:06 +04:00
|
|
|
MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2014-04-17 20:26:06 +04:00
|
|
|
static struct pci_driver pxa2xx_spi_pci_driver = {
|
|
|
|
.name = "pxa2xx_spi_pci",
|
|
|
|
.id_table = pxa2xx_spi_pci_devices,
|
|
|
|
.probe = pxa2xx_spi_pci_probe,
|
|
|
|
.remove = pxa2xx_spi_pci_remove,
|
2010-11-24 12:17:14 +03:00
|
|
|
};
|
|
|
|
|
2014-04-17 20:26:06 +04:00
|
|
|
module_pci_driver(pxa2xx_spi_pci_driver);
|
2010-11-24 12:17:14 +03:00
|
|
|
|
2014-04-17 20:26:06 +04:00
|
|
|
MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
|
2010-11-24 12:17:14 +03:00
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
|