2011-09-07 13:49:08 +04:00
|
|
|
/*
|
2013-06-24 14:50:26 +04:00
|
|
|
* exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
|
2011-09-07 13:49:08 +04:00
|
|
|
*
|
|
|
|
* Copyright (C) 2011 Samsung Electronics
|
|
|
|
* Donggeun Kim <dg77.kim@samsung.com>
|
2012-08-16 15:41:41 +04:00
|
|
|
* Amit Daniel Kachhap <amit.kachhap@linaro.org>
|
2011-09-07 13:49:08 +04:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/clk.h>
|
|
|
|
#include <linux/io.h>
|
2013-06-24 14:50:25 +04:00
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/module.h>
|
2012-08-16 15:41:42 +04:00
|
|
|
#include <linux/of.h>
|
2013-06-24 14:50:25 +04:00
|
|
|
#include <linux/platform_device.h>
|
|
|
|
|
|
|
|
#include "exynos_thermal_common.h"
|
2013-06-24 14:50:27 +04:00
|
|
|
#include "exynos_tmu.h"
|
2013-06-24 14:50:28 +04:00
|
|
|
#include "exynos_tmu_data.h"
|
2012-08-16 15:41:42 +04:00
|
|
|
|
|
|
|
struct exynos_tmu_data {
|
|
|
|
struct exynos_tmu_platform_data *pdata;
|
2011-09-07 13:49:08 +04:00
|
|
|
struct resource *mem;
|
|
|
|
void __iomem *base;
|
|
|
|
int irq;
|
2012-08-16 15:41:42 +04:00
|
|
|
enum soc_type soc;
|
2011-09-07 13:49:08 +04:00
|
|
|
struct work_struct irq_work;
|
|
|
|
struct mutex lock;
|
|
|
|
struct clk *clk;
|
|
|
|
u8 temp_error1, temp_error2;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TMU treats temperature as a mapped temperature code.
|
|
|
|
* The temperature is converted differently depending on the calibration type.
|
|
|
|
*/
|
2012-08-16 15:41:42 +04:00
|
|
|
static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
2011-09-07 13:49:08 +04:00
|
|
|
int temp_code;
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
if (data->soc == SOC_ARCH_EXYNOS4210)
|
|
|
|
/* temp should range between 25 and 125 */
|
|
|
|
if (temp < 25 || temp > 125) {
|
|
|
|
temp_code = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
switch (pdata->cal_type) {
|
|
|
|
case TYPE_TWO_POINT_TRIMMING:
|
2013-06-24 14:50:30 +04:00
|
|
|
temp_code = (temp - pdata->first_point_trim) *
|
|
|
|
(data->temp_error2 - data->temp_error1) /
|
|
|
|
(pdata->second_point_trim - pdata->first_point_trim) +
|
|
|
|
data->temp_error1;
|
2011-09-07 13:49:08 +04:00
|
|
|
break;
|
|
|
|
case TYPE_ONE_POINT_TRIMMING:
|
2013-06-24 14:50:30 +04:00
|
|
|
temp_code = temp + data->temp_error1 - pdata->first_point_trim;
|
2011-09-07 13:49:08 +04:00
|
|
|
break;
|
|
|
|
default:
|
2013-06-24 14:50:30 +04:00
|
|
|
temp_code = temp + pdata->default_temp_offset;
|
2011-09-07 13:49:08 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
return temp_code;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Calculate a temperature value from a temperature code.
|
|
|
|
* The unit of the temperature is degree Celsius.
|
|
|
|
*/
|
2012-08-16 15:41:42 +04:00
|
|
|
static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
2011-09-07 13:49:08 +04:00
|
|
|
int temp;
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
if (data->soc == SOC_ARCH_EXYNOS4210)
|
|
|
|
/* temp_code should range between 75 and 175 */
|
|
|
|
if (temp_code < 75 || temp_code > 175) {
|
|
|
|
temp = -ENODATA;
|
|
|
|
goto out;
|
|
|
|
}
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
switch (pdata->cal_type) {
|
|
|
|
case TYPE_TWO_POINT_TRIMMING:
|
2013-06-24 14:50:30 +04:00
|
|
|
temp = (temp_code - data->temp_error1) *
|
|
|
|
(pdata->second_point_trim - pdata->first_point_trim) /
|
|
|
|
(data->temp_error2 - data->temp_error1) +
|
|
|
|
pdata->first_point_trim;
|
2011-09-07 13:49:08 +04:00
|
|
|
break;
|
|
|
|
case TYPE_ONE_POINT_TRIMMING:
|
2013-06-24 14:50:30 +04:00
|
|
|
temp = temp_code - data->temp_error1 + pdata->first_point_trim;
|
2011-09-07 13:49:08 +04:00
|
|
|
break;
|
|
|
|
default:
|
2013-06-24 14:50:30 +04:00
|
|
|
temp = temp_code - pdata->default_temp_offset;
|
2011-09-07 13:49:08 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
return temp;
|
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static int exynos_tmu_initialize(struct platform_device *pdev)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
2013-06-24 14:50:31 +04:00
|
|
|
const struct exynos_tmu_registers *reg = pdata->registers;
|
2013-02-08 05:13:06 +04:00
|
|
|
unsigned int status, trim_info;
|
|
|
|
unsigned int rising_threshold = 0, falling_threshold = 0;
|
|
|
|
int ret = 0, threshold_code, i, trigger_levs = 0;
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
mutex_lock(&data->lock);
|
|
|
|
clk_enable(data->clk);
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
status = readb(data->base + reg->tmu_status);
|
2011-09-07 13:49:08 +04:00
|
|
|
if (!status) {
|
|
|
|
ret = -EBUSY;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
if (data->soc == SOC_ARCH_EXYNOS)
|
|
|
|
__raw_writel(1, data->base + reg->triminfo_ctrl);
|
|
|
|
|
2011-09-07 13:49:08 +04:00
|
|
|
/* Save trimming info in order to perform calibration */
|
2013-06-24 14:50:31 +04:00
|
|
|
trim_info = readl(data->base + reg->triminfo_data);
|
|
|
|
data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
|
|
|
|
data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
|
|
|
|
EXYNOS_TMU_TEMP_MASK);
|
2012-08-16 15:41:42 +04:00
|
|
|
|
2013-06-24 14:50:30 +04:00
|
|
|
if ((pdata->min_efuse_value > data->temp_error1) ||
|
|
|
|
(data->temp_error1 > pdata->max_efuse_value) ||
|
2012-08-16 15:41:42 +04:00
|
|
|
(data->temp_error2 != 0))
|
|
|
|
data->temp_error1 = pdata->efuse_value;
|
|
|
|
|
2013-02-08 05:13:06 +04:00
|
|
|
/* Count trigger levels to be enabled */
|
|
|
|
for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
|
|
|
|
if (pdata->trigger_levels[i])
|
|
|
|
trigger_levs++;
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
if (data->soc == SOC_ARCH_EXYNOS4210) {
|
|
|
|
/* Write temperature code for threshold */
|
|
|
|
threshold_code = temp_to_code(data, pdata->threshold);
|
|
|
|
if (threshold_code < 0) {
|
|
|
|
ret = threshold_code;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
writeb(threshold_code,
|
2013-06-24 14:50:31 +04:00
|
|
|
data->base + reg->threshold_temp);
|
2013-02-08 05:13:06 +04:00
|
|
|
for (i = 0; i < trigger_levs; i++)
|
2013-06-24 14:50:31 +04:00
|
|
|
writeb(pdata->trigger_levels[i], data->base +
|
|
|
|
reg->threshold_th0 + i * sizeof(reg->threshold_th0));
|
2012-08-16 15:41:42 +04:00
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
|
2012-08-16 15:41:42 +04:00
|
|
|
} else if (data->soc == SOC_ARCH_EXYNOS) {
|
2013-02-08 05:13:06 +04:00
|
|
|
/* Write temperature code for rising and falling threshold */
|
|
|
|
for (i = 0; i < trigger_levs; i++) {
|
|
|
|
threshold_code = temp_to_code(data,
|
|
|
|
pdata->trigger_levels[i]);
|
|
|
|
if (threshold_code < 0) {
|
|
|
|
ret = threshold_code;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
rising_threshold |= threshold_code << 8 * i;
|
|
|
|
if (pdata->threshold_falling) {
|
|
|
|
threshold_code = temp_to_code(data,
|
|
|
|
pdata->trigger_levels[i] -
|
|
|
|
pdata->threshold_falling);
|
|
|
|
if (threshold_code > 0)
|
|
|
|
falling_threshold |=
|
|
|
|
threshold_code << 8 * i;
|
|
|
|
}
|
2012-08-16 15:41:42 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
writel(rising_threshold,
|
2013-06-24 14:50:31 +04:00
|
|
|
data->base + reg->threshold_th0);
|
2013-02-08 05:13:06 +04:00
|
|
|
writel(falling_threshold,
|
2013-06-24 14:50:31 +04:00
|
|
|
data->base + reg->threshold_th1);
|
2012-08-16 15:41:42 +04:00
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
writel((reg->inten_rise_mask << reg->inten_rise_shift) |
|
|
|
|
(reg->inten_fall_mask << reg->inten_fall_shift),
|
|
|
|
data->base + reg->tmu_intclear);
|
2011-09-07 13:49:08 +04:00
|
|
|
}
|
|
|
|
out:
|
|
|
|
clk_disable(data->clk);
|
|
|
|
mutex_unlock(&data->lock);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static void exynos_tmu_control(struct platform_device *pdev, bool on)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
2013-06-24 14:50:31 +04:00
|
|
|
const struct exynos_tmu_registers *reg = pdata->registers;
|
2011-09-07 13:49:08 +04:00
|
|
|
unsigned int con, interrupt_en;
|
|
|
|
|
|
|
|
mutex_lock(&data->lock);
|
|
|
|
clk_enable(data->clk);
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
con = readl(data->base + reg->tmu_ctrl);
|
2012-08-16 15:41:42 +04:00
|
|
|
|
2013-06-24 14:50:29 +04:00
|
|
|
if (pdata->reference_voltage) {
|
2013-06-24 14:50:31 +04:00
|
|
|
con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
|
|
|
|
con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
|
2013-06-24 14:50:29 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->gain) {
|
2013-06-24 14:50:31 +04:00
|
|
|
con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
|
|
|
|
con |= (pdata->gain << reg->buf_slope_sel_shift);
|
2013-06-24 14:50:29 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->noise_cancel_mode) {
|
2013-06-24 14:50:31 +04:00
|
|
|
con &= ~(reg->therm_trip_mode_mask <<
|
|
|
|
reg->therm_trip_mode_shift);
|
|
|
|
con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
|
2012-08-16 15:41:42 +04:00
|
|
|
}
|
|
|
|
|
2011-09-07 13:49:08 +04:00
|
|
|
if (on) {
|
2013-06-24 14:50:31 +04:00
|
|
|
con |= (1 << reg->core_en_shift);
|
2013-06-24 14:50:29 +04:00
|
|
|
interrupt_en =
|
2013-06-24 14:50:31 +04:00
|
|
|
pdata->trigger_enable[3] << reg->inten_rise3_shift |
|
|
|
|
pdata->trigger_enable[2] << reg->inten_rise2_shift |
|
|
|
|
pdata->trigger_enable[1] << reg->inten_rise1_shift |
|
|
|
|
pdata->trigger_enable[0] << reg->inten_rise0_shift;
|
2013-02-08 05:13:06 +04:00
|
|
|
if (pdata->threshold_falling)
|
2013-06-24 14:50:29 +04:00
|
|
|
interrupt_en |=
|
2013-06-24 14:50:31 +04:00
|
|
|
interrupt_en << reg->inten_fall0_shift;
|
2011-09-07 13:49:08 +04:00
|
|
|
} else {
|
2013-06-24 14:50:31 +04:00
|
|
|
con &= ~(1 << reg->core_en_shift);
|
2011-09-07 13:49:08 +04:00
|
|
|
interrupt_en = 0; /* Disable all interrupts */
|
|
|
|
}
|
2013-06-24 14:50:31 +04:00
|
|
|
writel(interrupt_en, data->base + reg->tmu_inten);
|
|
|
|
writel(con, data->base + reg->tmu_ctrl);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
clk_disable(data->clk);
|
|
|
|
mutex_unlock(&data->lock);
|
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static int exynos_tmu_read(struct exynos_tmu_data *data)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2013-06-24 14:50:31 +04:00
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
|
|
|
const struct exynos_tmu_registers *reg = pdata->registers;
|
2011-09-07 13:49:08 +04:00
|
|
|
u8 temp_code;
|
|
|
|
int temp;
|
|
|
|
|
|
|
|
mutex_lock(&data->lock);
|
|
|
|
clk_enable(data->clk);
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
temp_code = readb(data->base + reg->tmu_cur_temp);
|
2011-09-07 13:49:08 +04:00
|
|
|
temp = code_to_temp(data, temp_code);
|
|
|
|
|
|
|
|
clk_disable(data->clk);
|
|
|
|
mutex_unlock(&data->lock);
|
|
|
|
|
|
|
|
return temp;
|
|
|
|
}
|
|
|
|
|
2013-02-11 07:54:23 +04:00
|
|
|
#ifdef CONFIG_THERMAL_EMULATION
|
|
|
|
static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
|
|
|
|
{
|
|
|
|
struct exynos_tmu_data *data = drv_data;
|
2013-06-24 14:50:31 +04:00
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
|
|
|
const struct exynos_tmu_registers *reg = pdata->registers;
|
|
|
|
unsigned int val;
|
2013-02-11 07:54:23 +04:00
|
|
|
int ret = -EINVAL;
|
|
|
|
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS4210)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (temp && temp < MCELSIUS)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
mutex_lock(&data->lock);
|
|
|
|
clk_enable(data->clk);
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
val = readl(data->base + reg->emul_con);
|
2013-02-11 07:54:23 +04:00
|
|
|
|
|
|
|
if (temp) {
|
|
|
|
temp /= MCELSIUS;
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) |
|
2013-02-11 07:54:23 +04:00
|
|
|
(temp_to_code(data, temp)
|
2013-06-24 14:50:31 +04:00
|
|
|
<< reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE;
|
2013-02-11 07:54:23 +04:00
|
|
|
} else {
|
2013-06-24 14:50:31 +04:00
|
|
|
val &= ~EXYNOS_EMUL_ENABLE;
|
2013-02-11 07:54:23 +04:00
|
|
|
}
|
|
|
|
|
2013-06-24 14:50:31 +04:00
|
|
|
writel(val, data->base + reg->emul_con);
|
2013-02-11 07:54:23 +04:00
|
|
|
|
|
|
|
clk_disable(data->clk);
|
|
|
|
mutex_unlock(&data->lock);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
|
|
|
|
{ return -EINVAL; }
|
|
|
|
#endif/*CONFIG_THERMAL_EMULATION*/
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static void exynos_tmu_work(struct work_struct *work)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_data *data = container_of(work,
|
|
|
|
struct exynos_tmu_data, irq_work);
|
2013-06-24 14:50:31 +04:00
|
|
|
struct exynos_tmu_platform_data *pdata = data->pdata;
|
|
|
|
const struct exynos_tmu_registers *reg = pdata->registers;
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2013-01-17 05:42:18 +04:00
|
|
|
exynos_report_trigger();
|
2011-09-07 13:49:08 +04:00
|
|
|
mutex_lock(&data->lock);
|
|
|
|
clk_enable(data->clk);
|
2013-06-24 14:50:31 +04:00
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
if (data->soc == SOC_ARCH_EXYNOS)
|
2013-06-24 14:50:31 +04:00
|
|
|
writel((reg->inten_rise_mask << reg->inten_rise_shift) |
|
|
|
|
(reg->inten_fall_mask << reg->inten_fall_shift),
|
|
|
|
data->base + reg->tmu_intclear);
|
2012-08-16 15:41:42 +04:00
|
|
|
else
|
2013-06-24 14:50:31 +04:00
|
|
|
writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
|
|
|
|
|
2011-09-07 13:49:08 +04:00
|
|
|
clk_disable(data->clk);
|
|
|
|
mutex_unlock(&data->lock);
|
2013-01-17 05:42:18 +04:00
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
enable_irq(data->irq);
|
2011-09-07 13:49:08 +04:00
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static irqreturn_t exynos_tmu_irq(int irq, void *id)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_data *data = id;
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
disable_irq_nosync(irq);
|
|
|
|
schedule_work(&data->irq_work);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2012-08-16 15:41:43 +04:00
|
|
|
static struct thermal_sensor_conf exynos_sensor_conf = {
|
|
|
|
.name = "exynos-therm",
|
|
|
|
.read_temperature = (int (*)(void *))exynos_tmu_read,
|
2013-02-11 07:54:23 +04:00
|
|
|
.write_emul_temp = exynos_tmu_set_emulation,
|
2012-08-16 15:41:44 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static const struct of_device_id exynos_tmu_match[] = {
|
|
|
|
{
|
|
|
|
.compatible = "samsung,exynos4210-tmu",
|
|
|
|
.data = (void *)EXYNOS4210_TMU_DRV_DATA,
|
|
|
|
},
|
2013-04-18 15:37:59 +04:00
|
|
|
{
|
|
|
|
.compatible = "samsung,exynos4412-tmu",
|
2013-06-24 14:50:28 +04:00
|
|
|
.data = (void *)EXYNOS5250_TMU_DRV_DATA,
|
2013-04-18 15:37:59 +04:00
|
|
|
},
|
2012-08-16 15:41:44 +04:00
|
|
|
{
|
|
|
|
.compatible = "samsung,exynos5250-tmu",
|
2013-06-24 14:50:28 +04:00
|
|
|
.data = (void *)EXYNOS5250_TMU_DRV_DATA,
|
2012-08-16 15:41:44 +04:00
|
|
|
},
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, exynos_tmu_match);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct platform_device_id exynos_tmu_driver_ids[] = {
|
|
|
|
{
|
|
|
|
.name = "exynos4210-tmu",
|
|
|
|
.driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "exynos5250-tmu",
|
2013-06-24 14:50:28 +04:00
|
|
|
.driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA,
|
2012-08-16 15:41:44 +04:00
|
|
|
},
|
|
|
|
{ },
|
|
|
|
};
|
2012-10-23 10:54:42 +04:00
|
|
|
MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
|
2012-08-16 15:41:44 +04:00
|
|
|
|
|
|
|
static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_OF
|
|
|
|
if (pdev->dev.of_node) {
|
|
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
|
|
|
|
if (!match)
|
|
|
|
return NULL;
|
|
|
|
return (struct exynos_tmu_platform_data *) match->data;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
return (struct exynos_tmu_platform_data *)
|
|
|
|
platform_get_device_id(pdev)->driver_data;
|
2012-08-16 15:41:43 +04:00
|
|
|
}
|
2012-11-21 08:31:01 +04:00
|
|
|
|
2012-12-22 01:15:52 +04:00
|
|
|
static int exynos_tmu_probe(struct platform_device *pdev)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_data *data;
|
|
|
|
struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
|
2012-08-16 15:41:43 +04:00
|
|
|
int ret, i;
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2012-08-16 15:41:44 +04:00
|
|
|
if (!pdata)
|
|
|
|
pdata = exynos_get_driver_data(pdev);
|
|
|
|
|
2011-09-07 13:49:08 +04:00
|
|
|
if (!pdata) {
|
|
|
|
dev_err(&pdev->dev, "No platform init data supplied.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2012-08-16 15:41:45 +04:00
|
|
|
data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
|
|
|
|
GFP_KERNEL);
|
2011-09-07 13:49:08 +04:00
|
|
|
if (!data) {
|
|
|
|
dev_err(&pdev->dev, "Failed to allocate driver structure\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
data->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (data->irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "Failed to get platform irq\n");
|
2012-08-16 15:41:45 +04:00
|
|
|
return data->irq;
|
2011-09-07 13:49:08 +04:00
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
INIT_WORK(&data->irq_work, exynos_tmu_work);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-01-21 14:09:20 +04:00
|
|
|
data->base = devm_ioremap_resource(&pdev->dev, data->mem);
|
|
|
|
if (IS_ERR(data->base))
|
|
|
|
return PTR_ERR(data->base);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2012-08-16 15:41:45 +04:00
|
|
|
ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
|
2012-08-16 15:41:42 +04:00
|
|
|
IRQF_TRIGGER_RISING, "exynos-tmu", data);
|
2011-09-07 13:49:08 +04:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
|
2012-08-16 15:41:45 +04:00
|
|
|
return ret;
|
2011-09-07 13:49:08 +04:00
|
|
|
}
|
|
|
|
|
2013-04-18 15:37:58 +04:00
|
|
|
data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
|
2011-09-07 13:49:08 +04:00
|
|
|
if (IS_ERR(data->clk)) {
|
|
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
2012-08-16 15:41:45 +04:00
|
|
|
return PTR_ERR(data->clk);
|
2011-09-07 13:49:08 +04:00
|
|
|
}
|
|
|
|
|
2013-04-18 15:37:58 +04:00
|
|
|
ret = clk_prepare(data->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
if (pdata->type == SOC_ARCH_EXYNOS ||
|
|
|
|
pdata->type == SOC_ARCH_EXYNOS4210)
|
|
|
|
data->soc = pdata->type;
|
|
|
|
else {
|
|
|
|
ret = -EINVAL;
|
|
|
|
dev_err(&pdev->dev, "Platform not supported\n");
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
2011-09-07 13:49:08 +04:00
|
|
|
data->pdata = pdata;
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
mutex_init(&data->lock);
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
ret = exynos_tmu_initialize(pdev);
|
2011-09-07 13:49:08 +04:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to initialize TMU\n");
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
exynos_tmu_control(pdev, true);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2012-08-16 15:41:43 +04:00
|
|
|
/* Register the sensor with thermal management interface */
|
|
|
|
(&exynos_sensor_conf)->private_data = data;
|
2013-06-24 14:50:30 +04:00
|
|
|
exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] +
|
|
|
|
pdata->trigger_enable[1] + pdata->trigger_enable[2]+
|
|
|
|
pdata->trigger_enable[3];
|
2012-08-16 15:41:43 +04:00
|
|
|
|
|
|
|
for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
|
|
|
|
exynos_sensor_conf.trip_data.trip_val[i] =
|
|
|
|
pdata->threshold + pdata->trigger_levels[i];
|
|
|
|
|
2013-02-08 05:13:06 +04:00
|
|
|
exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
|
|
|
|
|
2012-08-16 15:41:43 +04:00
|
|
|
exynos_sensor_conf.cooling_data.freq_clip_count =
|
|
|
|
pdata->freq_tab_count;
|
|
|
|
for (i = 0; i < pdata->freq_tab_count; i++) {
|
|
|
|
exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
|
|
|
|
pdata->freq_tab[i].freq_clip_max;
|
|
|
|
exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
|
|
|
|
pdata->freq_tab[i].temp_level;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = exynos_register_thermal(&exynos_sensor_conf);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to register thermal interface\n");
|
|
|
|
goto err_clk;
|
|
|
|
}
|
2012-11-21 08:31:01 +04:00
|
|
|
|
2011-09-07 13:49:08 +04:00
|
|
|
return 0;
|
|
|
|
err_clk:
|
2013-04-18 15:37:58 +04:00
|
|
|
clk_unprepare(data->clk);
|
2011-09-07 13:49:08 +04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-22 01:15:52 +04:00
|
|
|
static int exynos_tmu_remove(struct platform_device *pdev)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
exynos_tmu_control(pdev, false);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2012-08-16 15:41:43 +04:00
|
|
|
exynos_unregister_thermal();
|
|
|
|
|
2013-04-18 15:37:58 +04:00
|
|
|
clk_unprepare(data->clk);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-08 23:48:15 +04:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2012-08-16 15:41:42 +04:00
|
|
|
static int exynos_tmu_suspend(struct device *dev)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-08-16 15:41:42 +04:00
|
|
|
exynos_tmu_control(to_platform_device(dev), false);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static int exynos_tmu_resume(struct device *dev)
|
2011-09-07 13:49:08 +04:00
|
|
|
{
|
2012-07-08 23:48:15 +04:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
exynos_tmu_initialize(pdev);
|
|
|
|
exynos_tmu_control(pdev, true);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2012-07-08 23:48:15 +04:00
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
|
|
|
|
exynos_tmu_suspend, exynos_tmu_resume);
|
|
|
|
#define EXYNOS_TMU_PM (&exynos_tmu_pm)
|
2011-09-07 13:49:08 +04:00
|
|
|
#else
|
2012-08-16 15:41:42 +04:00
|
|
|
#define EXYNOS_TMU_PM NULL
|
2011-09-07 13:49:08 +04:00
|
|
|
#endif
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
static struct platform_driver exynos_tmu_driver = {
|
2011-09-07 13:49:08 +04:00
|
|
|
.driver = {
|
2012-08-16 15:41:42 +04:00
|
|
|
.name = "exynos-tmu",
|
2011-09-07 13:49:08 +04:00
|
|
|
.owner = THIS_MODULE,
|
2012-08-16 15:41:42 +04:00
|
|
|
.pm = EXYNOS_TMU_PM,
|
2012-12-12 14:24:24 +04:00
|
|
|
.of_match_table = of_match_ptr(exynos_tmu_match),
|
2011-09-07 13:49:08 +04:00
|
|
|
},
|
2012-08-16 15:41:42 +04:00
|
|
|
.probe = exynos_tmu_probe,
|
2012-12-22 01:15:52 +04:00
|
|
|
.remove = exynos_tmu_remove,
|
2012-08-16 15:41:44 +04:00
|
|
|
.id_table = exynos_tmu_driver_ids,
|
2011-09-07 13:49:08 +04:00
|
|
|
};
|
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
module_platform_driver(exynos_tmu_driver);
|
2011-09-07 13:49:08 +04:00
|
|
|
|
2012-08-16 15:41:42 +04:00
|
|
|
MODULE_DESCRIPTION("EXYNOS TMU Driver");
|
2011-09-07 13:49:08 +04:00
|
|
|
MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|
2012-08-16 15:41:42 +04:00
|
|
|
MODULE_ALIAS("platform:exynos-tmu");
|