2010-01-22 03:53:02 +03:00
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/*
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2011-12-14 19:03:17 +04:00
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* arch/arm/mach-tegra/common.c
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2010-01-22 03:53:02 +03:00
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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2010-04-06 00:16:42 +04:00
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#include <linux/clk.h>
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#include <linux/delay.h>
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2011-12-14 19:03:17 +04:00
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#include <linux/of_irq.h>
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2010-01-22 03:53:02 +03:00
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#include <asm/hardware/cache-l2x0.h>
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2011-12-14 19:03:17 +04:00
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#include <asm/hardware/gic.h>
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2010-01-22 03:53:02 +03:00
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2012-02-10 03:47:49 +04:00
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#include <mach/powergate.h>
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2010-01-22 03:53:02 +03:00
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#include "board.h"
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2010-01-29 03:40:29 +03:00
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#include "clock.h"
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2011-09-08 16:15:22 +04:00
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#include "common.h"
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2010-06-24 02:49:17 +04:00
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#include "fuse.h"
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2012-10-05 00:24:09 +04:00
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#include "iomap.h"
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2012-01-26 01:43:28 +04:00
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#include "pmc.h"
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2012-06-20 16:36:34 +04:00
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#include "apbio.h"
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2012-08-16 13:31:51 +04:00
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#include "sleep.h"
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2010-01-29 03:40:29 +03:00
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2012-01-06 14:43:22 +04:00
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/*
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* Storage for debug-macro.S's state.
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*
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* This must be in .data not .bss so that it gets initialized each time the
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* kernel is loaded. The data is declared here rather than debug-macro.S so
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* that multiple inclusions of debug-macro.S point at the same data.
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*/
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#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
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u32 tegra_uart_config[3] = {
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/* Debug UART initialization required */
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1,
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/* Debug UART physical address */
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(u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
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/* Debug UART virtual address */
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(u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
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};
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2010-01-29 03:40:29 +03:00
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2011-12-19 23:24:05 +04:00
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#ifdef CONFIG_OF
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2011-12-14 19:03:17 +04:00
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static const struct of_device_id tegra_dt_irq_match[] __initconst = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
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{ }
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};
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void __init tegra_dt_init_irq(void)
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{
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tegra_init_irq();
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of_irq_init(tegra_dt_irq_match);
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}
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2011-12-19 23:24:05 +04:00
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#endif
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2011-12-14 19:03:17 +04:00
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2010-08-24 05:37:25 +04:00
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void tegra_assert_system_reset(char mode, const char *cmd)
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{
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2011-12-14 19:03:19 +04:00
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void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
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2010-08-24 05:37:25 +04:00
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u32 reg;
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2011-02-17 19:13:57 +03:00
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reg = readl_relaxed(reset);
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2011-12-14 19:03:19 +04:00
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reg |= 0x10;
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2011-02-17 19:13:57 +03:00
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writel_relaxed(reg, reset);
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2010-08-24 05:37:25 +04:00
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}
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2011-12-14 19:03:17 +04:00
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
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2010-01-29 03:40:29 +03:00
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/* name parent rate enabled */
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{ "clk_m", NULL, 0, true },
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{ "pll_p", "clk_m", 216000000, true },
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{ "pll_p_out1", "pll_p", 28800000, true },
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{ "pll_p_out2", "pll_p", 48000000, true },
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{ "pll_p_out3", "pll_p", 72000000, true },
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2012-04-13 00:13:05 +04:00
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{ "pll_p_out4", "pll_p", 24000000, true },
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2012-04-13 00:09:39 +04:00
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{ "pll_c", "clk_m", 600000000, true },
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{ "pll_c_out1", "pll_c", 120000000, true },
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{ "sclk", "pll_c_out1", 120000000, true },
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{ "hclk", "sclk", 120000000, true },
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2012-04-21 02:58:18 +04:00
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{ "pclk", "hclk", 60000000, true },
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2011-02-22 04:05:36 +03:00
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{ "csite", NULL, 0, true },
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{ "emc", NULL, 0, true },
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{ "cpu", NULL, 0, true },
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2010-01-29 03:40:29 +03:00
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{ NULL, NULL, 0, 0},
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};
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2011-12-14 19:03:17 +04:00
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#endif
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2010-01-22 03:53:02 +03:00
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2012-04-23 12:31:49 +04:00
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
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/* name parent rate enabled */
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{ "clk_m", NULL, 0, true },
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{ "pll_p", "clk_m", 408000000, true },
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{ "pll_p_out1", "pll_p", 9600000, true },
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2012-10-29 14:25:29 +04:00
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{ "pll_p_out4", "pll_p", 102000000, true },
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{ "sclk", "pll_p_out4", 102000000, true },
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{ "hclk", "sclk", 102000000, true },
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{ "pclk", "hclk", 51000000, true },
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2012-04-23 12:31:49 +04:00
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{ NULL, NULL, 0, 0},
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};
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#endif
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2012-10-29 14:25:57 +04:00
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static void __init tegra_init_cache(void)
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2010-01-22 03:53:02 +03:00
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{
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
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2011-12-14 19:03:20 +04:00
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u32 aux_ctrl, cache_type;
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2010-01-22 03:53:02 +03:00
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2011-12-14 19:03:20 +04:00
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cache_type = readl(p + L2X0_CACHE_TYPE);
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aux_ctrl = (cache_type & 0x700) << (17-8);
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2012-11-14 18:27:23 +04:00
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aux_ctrl |= 0x7C400001;
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2011-12-14 19:03:20 +04:00
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2012-10-29 14:25:57 +04:00
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l2x0_of_init(aux_ctrl, 0x8200c3fe);
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2010-01-22 03:53:02 +03:00
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#endif
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2010-04-06 00:16:42 +04:00
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2010-01-22 03:53:02 +03:00
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}
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2011-12-14 19:03:17 +04:00
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void __init tegra20_init_early(void)
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2010-01-22 03:53:02 +03:00
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{
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2012-06-20 16:36:34 +04:00
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tegra_apb_io_init();
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2010-06-24 02:49:17 +04:00
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tegra_init_fuse();
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2011-12-14 19:03:17 +04:00
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tegra2_init_clocks();
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tegra_clk_init_from_table(tegra20_clk_init_table);
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2012-10-29 14:25:57 +04:00
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tegra_init_cache();
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2012-01-26 01:43:28 +04:00
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tegra_pmc_init();
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2012-02-10 03:47:49 +04:00
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tegra_powergate_init();
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2012-08-16 13:31:52 +04:00
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tegra20_hotplug_init();
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2010-01-22 03:53:02 +03:00
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}
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2011-12-14 19:03:17 +04:00
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#endif
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2011-12-14 19:03:25 +04:00
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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void __init tegra30_init_early(void)
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{
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2012-06-20 16:36:34 +04:00
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tegra_apb_io_init();
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2012-02-10 03:47:43 +04:00
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tegra_init_fuse();
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2012-01-09 09:35:13 +04:00
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tegra30_init_clocks();
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2012-04-23 12:31:49 +04:00
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tegra_clk_init_from_table(tegra30_clk_init_table);
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2012-10-29 14:25:57 +04:00
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tegra_init_cache();
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2012-01-26 01:43:28 +04:00
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tegra_pmc_init();
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2012-02-10 03:47:49 +04:00
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tegra_powergate_init();
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2012-08-16 13:31:51 +04:00
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tegra30_hotplug_init();
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2011-12-14 19:03:25 +04:00
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}
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#endif
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2012-05-02 13:08:06 +04:00
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void __init tegra_init_late(void)
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{
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tegra_powergate_debugfs_init();
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}
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