2005-04-17 02:20:36 +04:00
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/*
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* Intel AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 11:04:11 +03:00
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#include <linux/slab.h>
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2005-04-17 02:20:36 +04:00
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#include <linux/init.h>
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2007-02-06 19:08:28 +03:00
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#include <linux/kernel.h>
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2005-04-17 02:20:36 +04:00
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#include <linux/pagemap.h>
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#include <linux/agp_backend.h>
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2010-01-22 18:01:04 +03:00
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#include <asm/smp.h>
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2005-04-17 02:20:36 +04:00
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#include "agp.h"
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2010-04-14 02:29:51 +04:00
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#include "intel-agp.h"
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2006-09-06 19:57:18 +04:00
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2010-02-23 09:05:24 +03:00
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int intel_agp_enabled;
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EXPORT_SYMBOL(intel_agp_enabled);
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2005-04-17 02:20:36 +04:00
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static int intel_fetch_size(void)
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{
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int i;
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u16 temp;
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struct aper_size_info_16 *values;
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pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
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values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int __intel_8xx_fetch_size(u8 temp)
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{
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int i;
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struct aper_size_info_8 *values;
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values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int intel_8xx_fetch_size(void)
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{
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u8 temp;
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pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
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return __intel_8xx_fetch_size(temp);
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}
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static int intel_815_fetch_size(void)
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{
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u8 temp;
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/* Intel 815 chipsets have a _weird_ APSIZE register with only
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* one non-reserved bit, so mask the others out ... */
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pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
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temp &= (1 << 3);
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return __intel_8xx_fetch_size(temp);
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}
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static void intel_tlbflush(struct agp_memory *mem)
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{
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
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}
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static void intel_8xx_tlbflush(struct agp_memory *mem)
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{
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u32 temp;
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pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
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pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
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}
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static void intel_cleanup(void)
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{
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u16 temp;
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struct aper_size_info_16 *previous_size;
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previous_size = A_SIZE_16(agp_bridge->previous_size);
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
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pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
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}
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static void intel_8xx_cleanup(void)
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{
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u16 temp;
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struct aper_size_info_8 *previous_size;
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
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}
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static int intel_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_16 *current_size;
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current_size = A_SIZE_16(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
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/* paccfg/nbxcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
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(temp2 & ~(1 << 10)) | (1 << 9));
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/* clear any possible error conditions */
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pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
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return 0;
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}
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static int intel_815_configure(void)
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{
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u32 temp, addr;
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u8 temp2;
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struct aper_size_info_8 *current_size;
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/* attbase - aperture base */
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/* the Intel 815 chipset spec. says that bits 29-31 in the
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* ATTBASE register are reserved -> try not to write them */
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if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
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2008-07-30 23:26:51 +04:00
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dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
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2005-04-17 02:20:36 +04:00
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return -EINVAL;
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}
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
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current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
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addr &= INTEL_815_ATTBASE_MASK;
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addr |= agp_bridge->gatt_bus_addr;
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* apcont */
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pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
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pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
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/* clear any possible error conditions */
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/* Oddness : this chipset seems to have no ERRSTS register ! */
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return 0;
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}
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static void intel_820_tlbflush(struct agp_memory *mem)
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{
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return;
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}
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static void intel_820_cleanup(void)
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{
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u8 temp;
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struct aper_size_info_8 *previous_size;
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
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pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
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temp & ~(1 << 1));
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
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previous_size->size_value);
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}
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static int intel_820_configure(void)
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{
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u32 temp;
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u8 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* global enable aperture access */
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/* This flag is not accessed through MCHCFG register as in */
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/* i850 chipset. */
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pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
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pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
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/* clear any possible AGP-related error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
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return 0;
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}
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static int intel_840_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* mcgcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
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|
|
pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
|
|
|
|
|
/* clear any possible error conditions */
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int intel_845_configure(void)
|
|
|
|
|
{
|
|
|
|
|
u32 temp;
|
|
|
|
|
u8 temp2;
|
|
|
|
|
struct aper_size_info_8 *current_size;
|
|
|
|
|
|
|
|
|
|
current_size = A_SIZE_8(agp_bridge->current_size);
|
|
|
|
|
|
|
|
|
|
/* aperture size */
|
|
|
|
|
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
|
|
|
|
|
|
2005-07-30 01:03:39 +04:00
|
|
|
if (agp_bridge->apbase_config != 0) {
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
|
|
|
|
|
agp_bridge->apbase_config);
|
|
|
|
|
} else {
|
|
|
|
|
/* address to map to */
|
|
|
|
|
pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
|
|
|
|
|
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
|
agp_bridge->apbase_config = temp;
|
|
|
|
|
}
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
/* attbase - aperture base */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
|
|
|
|
|
|
|
|
|
|
/* agpctrl */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
|
|
|
|
|
|
|
|
|
|
/* agpm */
|
|
|
|
|
pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
|
|
|
|
|
pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
|
|
|
|
|
/* clear any possible error conditions */
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int intel_850_configure(void)
|
|
|
|
|
{
|
|
|
|
|
u32 temp;
|
|
|
|
|
u16 temp2;
|
|
|
|
|
struct aper_size_info_8 *current_size;
|
|
|
|
|
|
|
|
|
|
current_size = A_SIZE_8(agp_bridge->current_size);
|
|
|
|
|
|
|
|
|
|
/* aperture size */
|
|
|
|
|
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
|
|
|
|
|
|
|
|
|
|
/* address to map to */
|
|
|
|
|
pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
|
|
|
|
|
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
|
|
|
|
|
|
/* attbase - aperture base */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
|
|
|
|
|
|
|
|
|
|
/* agpctrl */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
|
|
|
|
|
|
|
|
|
|
/* mcgcfg */
|
|
|
|
|
pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
|
|
|
|
|
/* clear any possible AGP-related error conditions */
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int intel_860_configure(void)
|
|
|
|
|
{
|
|
|
|
|
u32 temp;
|
|
|
|
|
u16 temp2;
|
|
|
|
|
struct aper_size_info_8 *current_size;
|
|
|
|
|
|
|
|
|
|
current_size = A_SIZE_8(agp_bridge->current_size);
|
|
|
|
|
|
|
|
|
|
/* aperture size */
|
|
|
|
|
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
|
|
|
|
|
|
|
|
|
|
/* address to map to */
|
|
|
|
|
pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
|
|
|
|
|
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
|
|
|
|
|
|
/* attbase - aperture base */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
|
|
|
|
|
|
|
|
|
|
/* agpctrl */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
|
|
|
|
|
|
|
|
|
|
/* mcgcfg */
|
|
|
|
|
pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
|
|
|
|
|
/* clear any possible AGP-related error conditions */
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int intel_830mp_configure(void)
|
|
|
|
|
{
|
|
|
|
|
u32 temp;
|
|
|
|
|
u16 temp2;
|
|
|
|
|
struct aper_size_info_8 *current_size;
|
|
|
|
|
|
|
|
|
|
current_size = A_SIZE_8(agp_bridge->current_size);
|
|
|
|
|
|
|
|
|
|
/* aperture size */
|
|
|
|
|
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
|
|
|
|
|
|
|
|
|
|
/* address to map to */
|
|
|
|
|
pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
|
|
|
|
|
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
|
|
|
|
|
|
/* attbase - aperture base */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
|
|
|
|
|
|
|
|
|
|
/* agpctrl */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
|
|
|
|
|
|
|
|
|
|
/* gmch */
|
|
|
|
|
pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
|
|
|
|
|
/* clear any possible AGP-related error conditions */
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int intel_7505_configure(void)
|
|
|
|
|
{
|
|
|
|
|
u32 temp;
|
|
|
|
|
u16 temp2;
|
|
|
|
|
struct aper_size_info_8 *current_size;
|
|
|
|
|
|
|
|
|
|
current_size = A_SIZE_8(agp_bridge->current_size);
|
|
|
|
|
|
|
|
|
|
/* aperture size */
|
|
|
|
|
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
|
|
|
|
|
|
|
|
|
|
/* address to map to */
|
|
|
|
|
pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
|
|
|
|
|
agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
|
|
|
|
|
|
/* attbase - aperture base */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
|
|
|
|
|
|
|
|
|
|
/* agpctrl */
|
|
|
|
|
pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
|
|
|
|
|
|
|
|
|
|
/* mchcfg */
|
|
|
|
|
pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
|
|
|
|
|
pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Setup function */
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct gatt_mask intel_generic_masks[] =
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
{.mask = 0x00000017, .type = 0}
|
|
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct aper_size_info_8 intel_815_sizes[2] =
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
{64, 16384, 4, 0},
|
|
|
|
|
{32, 8192, 3, 8},
|
|
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct aper_size_info_8 intel_8xx_sizes[7] =
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
{256, 65536, 6, 0},
|
|
|
|
|
{128, 32768, 5, 32},
|
|
|
|
|
{64, 16384, 4, 48},
|
|
|
|
|
{32, 8192, 3, 56},
|
|
|
|
|
{16, 4096, 2, 60},
|
|
|
|
|
{8, 2048, 1, 62},
|
|
|
|
|
{4, 1024, 0, 63}
|
|
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct aper_size_info_16 intel_generic_sizes[7] =
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
{256, 65536, 6, 0},
|
|
|
|
|
{128, 32768, 5, 32},
|
|
|
|
|
{64, 16384, 4, 48},
|
|
|
|
|
{32, 8192, 3, 56},
|
|
|
|
|
{16, 4096, 2, 60},
|
|
|
|
|
{8, 2048, 1, 62},
|
|
|
|
|
{4, 1024, 0, 63}
|
|
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct aper_size_info_8 intel_830mp_sizes[4] =
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
{256, 65536, 6, 0},
|
|
|
|
|
{128, 32768, 5, 32},
|
|
|
|
|
{64, 16384, 4, 48},
|
|
|
|
|
{32, 8192, 3, 56}
|
|
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_generic_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_generic_sizes,
|
|
|
|
|
.size_type = U16_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_configure,
|
|
|
|
|
.fetch_size = intel_fetch_size,
|
|
|
|
|
.cleanup = intel_cleanup,
|
|
|
|
|
.tlb_flush = intel_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_815_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_815_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 2,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_815_configure,
|
|
|
|
|
.fetch_size = intel_815_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2008-06-19 08:27:53 +04:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_820_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_820_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_820_cleanup,
|
|
|
|
|
.tlb_flush = intel_820_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_830mp_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_830mp_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 4,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_830mp_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_840_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_840_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_845_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_845_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_850_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_850_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_860_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_860_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-02-23 02:41:28 +03:00
|
|
|
static const struct agp_bridge_driver intel_7505_driver = {
|
2005-04-17 02:20:36 +04:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
|
|
|
.size_type = U8_APER_SIZE,
|
|
|
|
|
.num_aperture_sizes = 7,
|
2010-04-20 19:43:34 +04:00
|
|
|
.needs_scratch_page = true,
|
2005-04-17 02:20:36 +04:00
|
|
|
.configure = intel_7505_configure,
|
|
|
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
|
|
|
.cleanup = intel_8xx_cleanup,
|
|
|
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
|
|
|
.mask_memory = agp_generic_mask_memory,
|
|
|
|
|
.masks = intel_generic_masks,
|
|
|
|
|
.agp_enable = agp_generic_enable,
|
|
|
|
|
.cache_flush = global_cache_flush,
|
|
|
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
|
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
|
|
|
.insert_memory = agp_generic_insert_memory,
|
|
|
|
|
.remove_memory = agp_generic_remove_memory,
|
|
|
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
|
|
|
.free_by_type = agp_generic_free_by_type,
|
|
|
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
2008-08-21 06:46:11 +04:00
|
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
2005-04-17 02:20:36 +04:00
|
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
2008-08-21 06:46:17 +04:00
|
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
2007-01-23 12:33:43 +03:00
|
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2007-05-30 05:45:58 +04:00
|
|
|
/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
|
|
|
|
|
* driver and gmch_driver must be non-null, and find_gmch will determine
|
|
|
|
|
* which one should be used if a gmch_chip_id is present.
|
|
|
|
|
*/
|
2010-08-24 21:39:48 +04:00
|
|
|
static const struct intel_agp_driver_description {
|
2007-05-30 05:45:58 +04:00
|
|
|
unsigned int chip_id;
|
|
|
|
|
char *name;
|
|
|
|
|
const struct agp_bridge_driver *driver;
|
|
|
|
|
} intel_agp_chipsets[] = {
|
2010-08-24 21:39:48 +04:00
|
|
|
{ PCI_DEVICE_ID_INTEL_82443LX_0, "440LX", &intel_generic_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82443BX_0, "440BX", &intel_generic_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82443GX_0, "440GX", &intel_generic_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82815_MC, "i815", &intel_815_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82820_HB, "i820", &intel_820_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
|
2010-06-20 01:08:37 +04:00
|
|
|
{ PCI_DEVICE_ID_INTEL_82845_HB, "i845", &intel_845_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82845G_HB, "845G", &intel_845_driver },
|
2010-08-24 21:39:48 +04:00
|
|
|
{ PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82855GM_HB, "855GM", &intel_845_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82860_HB, "i860", &intel_860_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82865_HB, "865", &intel_845_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_82875_HB, "i875", &intel_845_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_7505_0, "E7505", &intel_7505_driver },
|
|
|
|
|
{ PCI_DEVICE_ID_INTEL_7205_0, "E7205", &intel_7505_driver },
|
|
|
|
|
{ 0, NULL, NULL }
|
2007-05-30 05:45:58 +04:00
|
|
|
};
|
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
static int __devinit agp_intel_probe(struct pci_dev *pdev,
|
|
|
|
|
const struct pci_device_id *ent)
|
|
|
|
|
{
|
|
|
|
|
struct agp_bridge_data *bridge;
|
|
|
|
|
u8 cap_ptr = 0;
|
|
|
|
|
struct resource *r;
|
2010-02-23 09:05:24 +03:00
|
|
|
int i, err;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
|
|
|
|
|
|
|
|
|
|
bridge = agp_alloc_bridge();
|
|
|
|
|
if (!bridge)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2010-04-14 02:29:55 +04:00
|
|
|
bridge->capndx = cap_ptr;
|
|
|
|
|
|
|
|
|
|
if (intel_gmch_probe(pdev, bridge))
|
|
|
|
|
goto found_gmch;
|
|
|
|
|
|
2007-05-30 05:45:58 +04:00
|
|
|
for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
|
|
|
|
|
/* In case that multiple models of gfx chip may
|
|
|
|
|
stand on same host bridge type, this can be
|
|
|
|
|
sure we detect the right IGD. */
|
2007-06-14 06:01:04 +04:00
|
|
|
if (pdev->device == intel_agp_chipsets[i].chip_id) {
|
2010-04-14 02:29:55 +04:00
|
|
|
bridge->driver = intel_agp_chipsets[i].driver;
|
|
|
|
|
break;
|
2007-06-14 06:01:04 +04:00
|
|
|
}
|
2007-05-30 05:45:58 +04:00
|
|
|
}
|
|
|
|
|
|
2010-08-24 21:39:48 +04:00
|
|
|
if (!bridge->driver) {
|
2005-04-17 02:20:36 +04:00
|
|
|
if (cap_ptr)
|
2008-07-30 23:26:51 +04:00
|
|
|
dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
|
|
|
|
|
pdev->vendor, pdev->device);
|
2007-05-30 05:45:58 +04:00
|
|
|
agp_put_bridge(bridge);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
bridge->dev = pdev;
|
2010-04-14 02:29:55 +04:00
|
|
|
bridge->dev_private_data = NULL;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2008-07-30 23:26:51 +04:00
|
|
|
dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The following fixes the case where the BIOS has "forgotten" to
|
|
|
|
|
* provide an address range for the GART.
|
|
|
|
|
* 20030610 - hamish@zot.org
|
2011-02-01 01:25:43 +03:00
|
|
|
* This happens before pci_enable_device() intentionally;
|
|
|
|
|
* calling pci_enable_device() before assigning the resource
|
|
|
|
|
* will result in the GART being disabled on machines with such
|
|
|
|
|
* BIOSs (the GART ends up with a BAR starting at 0, which
|
|
|
|
|
* conflicts a lot of other devices).
|
2005-04-17 02:20:36 +04:00
|
|
|
*/
|
|
|
|
|
r = &pdev->resource[0];
|
|
|
|
|
if (!r->start && r->end) {
|
2006-02-28 08:54:25 +03:00
|
|
|
if (pci_assign_resource(pdev, 0)) {
|
2008-07-30 23:26:51 +04:00
|
|
|
dev_err(&pdev->dev, "can't assign resource 0\n");
|
2005-04-17 02:20:36 +04:00
|
|
|
agp_put_bridge(bridge);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-01 01:25:43 +03:00
|
|
|
/*
|
|
|
|
|
* If the device has not been properly setup, the following will catch
|
|
|
|
|
* the problem and should stop the system from crashing.
|
|
|
|
|
* 20030610 - hamish@zot.org
|
|
|
|
|
*/
|
|
|
|
|
if (pci_enable_device(pdev)) {
|
|
|
|
|
dev_err(&pdev->dev, "can't enable PCI device\n");
|
|
|
|
|
agp_put_bridge(bridge);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
/* Fill in the mode register */
|
|
|
|
|
if (cap_ptr) {
|
|
|
|
|
pci_read_config_dword(pdev,
|
|
|
|
|
bridge->capndx+PCI_AGP_STATUS,
|
|
|
|
|
&bridge->mode);
|
|
|
|
|
}
|
|
|
|
|
|
2010-04-14 02:29:55 +04:00
|
|
|
found_gmch:
|
2005-04-17 02:20:36 +04:00
|
|
|
pci_set_drvdata(pdev, bridge);
|
2010-02-23 09:05:24 +03:00
|
|
|
err = agp_add_bridge(bridge);
|
|
|
|
|
if (!err)
|
|
|
|
|
intel_agp_enabled = 1;
|
|
|
|
|
return err;
|
2005-04-17 02:20:36 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __devexit agp_intel_remove(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
agp_remove_bridge(bridge);
|
|
|
|
|
|
2010-08-24 21:39:48 +04:00
|
|
|
intel_gmch_remove(pdev);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
agp_put_bridge(bridge);
|
|
|
|
|
}
|
|
|
|
|
|
2006-08-12 02:02:02 +04:00
|
|
|
#ifdef CONFIG_PM
|
2005-04-17 02:20:36 +04:00
|
|
|
static int agp_intel_resume(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
|
|
2010-04-14 02:29:53 +04:00
|
|
|
bridge->driver->configure();
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2006-08-12 02:02:02 +04:00
|
|
|
#endif
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
static struct pci_device_id agp_intel_pci_table[] = {
|
|
|
|
|
#define ID(x) \
|
|
|
|
|
{ \
|
|
|
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8), \
|
|
|
|
|
.class_mask = ~0, \
|
|
|
|
|
.vendor = PCI_VENDOR_ID_INTEL, \
|
|
|
|
|
.device = x, \
|
|
|
|
|
.subvendor = PCI_ANY_ID, \
|
|
|
|
|
.subdevice = PCI_ANY_ID, \
|
|
|
|
|
}
|
2012-01-05 02:04:33 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82441), /* for HAS2 support */
|
2005-04-17 02:20:36 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82443LX_0),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82443BX_0),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82443GX_0),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82810_MC1),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82810_MC3),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82810E_MC),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82815_MC),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82820_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82830_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82840_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82845_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82845G_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82850_HB),
|
2009-04-14 01:40:10 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82854_HB),
|
2005-04-17 02:20:36 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82860_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82865_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82875_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_7505_0),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_7205_0),
|
2008-01-24 03:34:09 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_E7221_HB),
|
2005-04-17 02:20:36 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82915G_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
|
2005-05-31 22:50:49 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82945G_HB),
|
2006-01-19 17:08:40 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
|
2007-07-26 05:18:09 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
|
2009-12-04 01:14:41 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
|
2006-09-06 19:57:18 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
|
2008-01-23 08:49:26 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82G35_HB),
|
2006-09-06 19:57:18 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_82965G_HB),
|
2007-04-09 04:51:36 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
|
2007-07-26 05:18:09 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
|
2007-06-06 07:16:25 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_G33_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
|
2008-07-30 23:26:50 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_GM45_HB),
|
2009-12-04 01:14:41 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
|
2008-06-19 08:17:58 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_Q45_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_G45_HB),
|
2008-11-17 09:39:00 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_G41_HB),
|
2009-09-07 20:59:58 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_B43_HB),
|
2010-10-14 19:30:41 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
|
2009-12-04 01:14:41 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
|
2009-12-08 07:03:47 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
|
2009-10-23 03:10:52 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
|
2010-01-08 03:21:46 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
|
2010-09-07 09:45:32 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
|
2011-02-17 22:50:19 +03:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
|
2012-03-29 00:39:34 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB),
|
2012-05-09 22:37:32 +04:00
|
|
|
ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),
|
|
|
|
|
ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),
|
2005-04-17 02:20:36 +04:00
|
|
|
{ }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
|
|
|
|
|
|
|
|
|
|
static struct pci_driver agp_intel_pci_driver = {
|
|
|
|
|
.name = "agpgart-intel",
|
|
|
|
|
.id_table = agp_intel_pci_table,
|
|
|
|
|
.probe = agp_intel_probe,
|
|
|
|
|
.remove = __devexit_p(agp_intel_remove),
|
2006-08-12 02:02:02 +04:00
|
|
|
#ifdef CONFIG_PM
|
2005-04-17 02:20:36 +04:00
|
|
|
.resume = agp_intel_resume,
|
2006-08-12 02:02:02 +04:00
|
|
|
#endif
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init agp_intel_init(void)
|
|
|
|
|
{
|
|
|
|
|
if (agp_off)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
return pci_register_driver(&agp_intel_pci_driver);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit agp_intel_cleanup(void)
|
|
|
|
|
{
|
|
|
|
|
pci_unregister_driver(&agp_intel_pci_driver);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
module_init(agp_intel_init);
|
|
|
|
|
module_exit(agp_intel_cleanup);
|
|
|
|
|
|
2008-10-20 21:31:45 +04:00
|
|
|
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
2005-04-17 02:20:36 +04:00
|
|
|
MODULE_LICENSE("GPL and additional rights");
|
