2011-08-24 18:37:45 +04:00
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/*
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2014-04-11 22:09:36 +04:00
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* OMAP L3 Interconnect error handling driver header
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2011-08-24 18:37:45 +04:00
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*
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2014-04-11 22:15:43 +04:00
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* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
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2011-08-24 18:37:45 +04:00
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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2014-04-11 22:15:43 +04:00
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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2011-08-24 18:37:45 +04:00
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*
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2014-04-11 22:15:43 +04:00
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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2011-08-24 18:37:45 +04:00
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* GNU General Public License for more details.
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*/
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2014-04-11 22:09:36 +04:00
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#ifndef __OMAP_L3_NOC_H
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#define __OMAP_L3_NOC_H
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2011-03-07 18:23:10 +03:00
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2013-11-26 17:38:23 +04:00
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#define MAX_L3_MODULES 3
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2014-04-14 18:57:50 +04:00
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#define MAX_CLKDM_TARGETS 31
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2013-11-26 17:38:23 +04:00
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2011-03-07 18:23:10 +03:00
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#define CLEAR_STDERR_LOG (1 << 31)
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#define CUSTOM_ERROR 0x2
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#define STANDARD_ERROR 0x0
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#define INBAND_ERROR 0x0
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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2011-08-24 17:41:39 +04:00
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/* L3 TARG register offsets */
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2011-08-24 18:37:45 +04:00
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#define L3_TARG_STDERRLOG_MAIN 0x48
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#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
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2011-09-07 15:55:16 +04:00
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#define L3_TARG_STDERRLOG_MSTADDR 0x68
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2011-08-24 18:37:45 +04:00
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#define L3_FLAGMUX_REGERR0 0xc
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bus: omap_l3_noc: Add support for discountinous flag mux input numbers
On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used
to indicate the source of errors are not continous. Have a way in the
driver to catch these and WARN the user of the flag mux input thats
either undocumented or wrong.
In the similar vein, Timeout errors in AM43x can't be cleared per h/w
team, neither does it have a STDERRLOG_MAIN to clear the error.
Further, the mux bit offset might not even be indexed into our array
of known mux input description, in which case we'd have a abort.
So, define a static range check for bit description and any definition
which has target_name set to NULL (the ones that are not populated or
ones that are specifically marked in the case of discontinous input
numbers), can handle the same gracefully. Upon occurance of error from
such sources, mask it. Otherwise, we'd have an infinite interrupt
source without any means to clear it.
NOTE: follow on patch ensures that these masked bits are ignored.
[nm@ti.com: rebase, squash and improve]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
2014-04-10 20:31:33 +04:00
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#define L3_FLAGMUX_MASK0 0x8
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#define L3_TARGET_NOT_SUPPORTED NULL
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2014-04-11 19:11:59 +04:00
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/**
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* struct l3_masters_data - L3 Master information
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* @id: ID of the L3 Master
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* @name: master name
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*/
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struct l3_masters_data {
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u32 id;
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char *name;
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};
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2014-04-11 20:38:10 +04:00
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/**
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* struct l3_target_data - L3 Target information
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* @offset: Offset from base for L3 Target
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* @name: Target name
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*
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* Target information is organized indexed by bit field definitions.
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*/
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struct l3_target_data {
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u32 offset;
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char *name;
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};
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2014-04-14 18:57:50 +04:00
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/**
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* struct l3_flagmux_data - Flag Mux information
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* @offset: offset from base for flagmux register
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* @l3_targ: array indexed by flagmux index (bit offset) pointing to the
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* target data. unsupported ones are marked with
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* L3_TARGET_NOT_SUPPORTED
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* @num_targ_data: number of entries in target data
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*/
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struct l3_flagmux_data {
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u32 offset;
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struct l3_target_data *l3_targ;
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u8 num_targ_data;
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};
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2013-11-26 17:38:23 +04:00
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/**
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* struct omap_l3 - Description of data relevant for L3 bus.
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* @dev: device representing the bus (populated runtime)
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* @l3_base: base addresses of modules (populated runtime)
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2014-04-14 18:57:50 +04:00
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* @l3_flag_mux: array containing flag mux data per module
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2013-11-26 17:38:23 +04:00
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* offset from corresponding module base indexed per
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* module.
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* @num_modules: number of clock domains / modules.
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* @l3_masters: array pointing to master data containing name and register
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* offset for the master.
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* @num_master: number of masters
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2014-04-16 20:01:02 +04:00
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* @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
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2013-11-26 17:38:23 +04:00
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* @debug_irq: irq number of the debug interrupt (populated runtime)
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* @app_irq: irq number of the application interrupt (populated runtime)
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*/
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struct omap_l3 {
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struct device *dev;
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void __iomem *l3_base[MAX_L3_MODULES];
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2014-04-14 18:57:50 +04:00
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struct l3_flagmux_data **l3_flagmux;
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2013-11-26 17:38:23 +04:00
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int num_modules;
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struct l3_masters_data *l3_masters;
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int num_masters;
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2014-04-16 20:01:02 +04:00
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u32 mst_addr_mask;
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2013-11-26 17:38:23 +04:00
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int debug_irq;
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int app_irq;
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};
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2014-04-14 18:57:50 +04:00
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static struct l3_target_data omap_l3_target_data_clk1[] = {
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2014-04-11 20:38:10 +04:00
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{0x100, "DMM1",},
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{0x200, "DMM2",},
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{0x300, "ABE",},
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{0x400, "L4CFG",},
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{0x600, "CLK2PWRDISC",},
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{0x0, "HOSTCLK1",},
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{0x900, "L4WAKEUP",},
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2011-03-07 18:23:10 +03:00
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};
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2014-04-14 18:57:50 +04:00
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static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
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.offset = 0x500,
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.l3_targ = omap_l3_target_data_clk1,
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.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
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};
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static struct l3_target_data omap_l3_target_data_clk2[] = {
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2014-04-11 20:38:10 +04:00
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{0x500, "CORTEXM3",},
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{0x300, "DSS",},
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{0x100, "GPMC",},
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{0x400, "ISS",},
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{0x700, "IVAHD",},
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{0xD00, "AES1",},
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{0x900, "L4PER0",},
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{0x200, "OCMRAM",},
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{0x100, "GPMCsERROR",},
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{0x600, "SGX",},
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{0x800, "SL2",},
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{0x1600, "C2C",},
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{0x1100, "PWRDISCCLK1",},
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{0xF00, "SHA1",},
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{0xE00, "AES2",},
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{0xC00, "L4PER3",},
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{0xA00, "L4PER1",},
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{0xB00, "L4PER2",},
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{0x0, "HOSTCLK2",},
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{0x1800, "CAL",},
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{0x1700, "LLI",},
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2011-03-07 18:23:10 +03:00
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};
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2014-04-14 18:57:50 +04:00
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static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
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.offset = 0x1000,
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.l3_targ = omap_l3_target_data_clk2,
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.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
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};
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static struct l3_target_data omap_l3_target_data_clk3[] = {
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2014-04-11 20:38:10 +04:00
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{0x0100, "EMUSS",},
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{0x0300, "DEBUG SOURCE",},
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{0x0, "HOST CLK3",},
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2011-03-07 18:23:10 +03:00
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};
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2014-04-14 18:57:50 +04:00
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static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
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.offset = 0x0200,
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.l3_targ = omap_l3_target_data_clk3,
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.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
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};
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2013-11-26 17:38:23 +04:00
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static struct l3_masters_data omap_l3_masters[] = {
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2011-09-07 15:55:16 +04:00
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{ 0x0 , "MPU"},
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{ 0x10, "CS_ADP"},
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{ 0x14, "xxx"},
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{ 0x20, "DSP"},
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{ 0x30, "IVAHD"},
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{ 0x40, "ISS"},
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{ 0x44, "DucatiM3"},
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{ 0x48, "FaceDetect"},
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{ 0x50, "SDMA_Rd"},
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{ 0x54, "SDMA_Wr"},
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{ 0x58, "xxx"},
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{ 0x5C, "xxx"},
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{ 0x60, "SGX"},
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{ 0x70, "DSS"},
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{ 0x80, "C2C"},
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{ 0x88, "xxx"},
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{ 0x8C, "xxx"},
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{ 0x90, "HSI"},
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{ 0xA0, "MMC1"},
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{ 0xA4, "MMC2"},
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{ 0xA8, "MMC6"},
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{ 0xB0, "UNIPRO1"},
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{ 0xC0, "USBHOSTHS"},
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{ 0xC4, "USBOTGHS"},
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{ 0xC8, "USBHOSTFS"}
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};
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2014-04-14 18:57:50 +04:00
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static struct l3_flagmux_data *omap_l3_flagmux[] = {
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&omap_l3_flagmux_clk1,
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&omap_l3_flagmux_clk2,
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&omap_l3_flagmux_clk3,
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2011-03-07 18:23:10 +03:00
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};
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2013-11-26 17:38:23 +04:00
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static const struct omap_l3 omap_l3_data = {
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.l3_flagmux = omap_l3_flagmux,
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2014-04-14 18:57:50 +04:00
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.num_modules = ARRAY_SIZE(omap_l3_flagmux),
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2013-11-26 17:38:23 +04:00
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.l3_masters = omap_l3_masters,
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.num_masters = ARRAY_SIZE(omap_l3_masters),
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2014-04-16 20:01:02 +04:00
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/* The 6 MSBs of register field used to distinguish initiator */
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.mst_addr_mask = 0xFC,
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2011-03-07 18:23:10 +03:00
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};
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2014-04-11 22:09:36 +04:00
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#endif /* __OMAP_L3_NOC_H */
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