2018-03-20 11:15:41 +03:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Silicon Labs Si544 Programmable Oscillator
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* Copyright (C) 2018 Topic Embedded Products
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* Author: Mike Looijmans <mike.looijmans@topic.nl>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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2019-05-07 16:51:10 +03:00
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#include <linux/math64.h>
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2018-03-20 11:15:41 +03:00
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* I2C registers (decimal as in datasheet) */
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#define SI544_REG_CONTROL 7
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#define SI544_REG_OE_STATE 17
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#define SI544_REG_HS_DIV 23
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#define SI544_REG_LS_HS_DIV 24
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#define SI544_REG_FBDIV0 26
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#define SI544_REG_FBDIV8 27
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#define SI544_REG_FBDIV16 28
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#define SI544_REG_FBDIV24 29
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#define SI544_REG_FBDIV32 30
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#define SI544_REG_FBDIV40 31
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#define SI544_REG_FCAL_OVR 69
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#define SI544_REG_ADPLL_DELTA_M0 231
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#define SI544_REG_ADPLL_DELTA_M8 232
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#define SI544_REG_ADPLL_DELTA_M16 233
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#define SI544_REG_PAGE_SELECT 255
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/* Register values */
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#define SI544_CONTROL_RESET BIT(7)
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#define SI544_CONTROL_MS_ICAL2 BIT(3)
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#define SI544_OE_STATE_ODC_OE BIT(0)
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/* Max freq depends on speed grade */
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#define SI544_MIN_FREQ 200000U
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/* Si544 Internal oscilator runs at 55.05 MHz */
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#define FXO 55050000U
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/* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
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#define FVCO_MIN 10800000000ULL
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#define HS_DIV_MAX 2046
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#define HS_DIV_MAX_ODD 33
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/* Lowest frequency synthesizeable using only the HS divider */
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#define MIN_HSDIV_FREQ (FVCO_MIN / HS_DIV_MAX)
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2019-05-07 16:51:10 +03:00
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/* Range and interpretation of the adjustment value */
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#define DELTA_M_MAX 8161512
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#define DELTA_M_FRAC_NUM 19
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#define DELTA_M_FRAC_DEN 20000
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2018-03-20 11:15:41 +03:00
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enum si544_speed_grade {
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si544a,
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si544b,
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si544c,
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};
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struct clk_si544 {
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struct clk_hw hw;
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struct regmap *regmap;
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struct i2c_client *i2c_client;
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enum si544_speed_grade speed_grade;
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};
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#define to_clk_si544(_hw) container_of(_hw, struct clk_si544, hw)
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/**
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* struct clk_si544_muldiv - Multiplier/divider settings
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* @fb_div_frac: integer part of feedback divider (32 bits)
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* @fb_div_int: fractional part of feedback divider (11 bits)
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* @hs_div: 1st divider, 5..2046, must be even when >33
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* @ls_div_bits: 2nd divider, as 2^x, range 0..5
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* If ls_div_bits is non-zero, hs_div must be even
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2019-05-07 16:51:10 +03:00
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* @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
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2018-03-20 11:15:41 +03:00
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*/
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struct clk_si544_muldiv {
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u32 fb_div_frac;
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u16 fb_div_int;
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u16 hs_div;
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u8 ls_div_bits;
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s32 delta_m;
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2018-03-20 11:15:41 +03:00
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};
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/* Enables or disables the output driver */
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static int si544_enable_output(struct clk_si544 *data, bool enable)
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{
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return regmap_update_bits(data->regmap, SI544_REG_OE_STATE,
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SI544_OE_STATE_ODC_OE, enable ? SI544_OE_STATE_ODC_OE : 0);
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}
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2018-06-04 08:34:39 +03:00
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static int si544_prepare(struct clk_hw *hw)
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{
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struct clk_si544 *data = to_clk_si544(hw);
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return si544_enable_output(data, true);
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}
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static void si544_unprepare(struct clk_hw *hw)
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{
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struct clk_si544 *data = to_clk_si544(hw);
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si544_enable_output(data, false);
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}
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static int si544_is_prepared(struct clk_hw *hw)
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{
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struct clk_si544 *data = to_clk_si544(hw);
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unsigned int val;
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int err;
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err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val);
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if (err < 0)
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return err;
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return !!(val & SI544_OE_STATE_ODC_OE);
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}
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2018-03-20 11:15:41 +03:00
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/* Retrieve clock multiplier and dividers from hardware */
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static int si544_get_muldiv(struct clk_si544 *data,
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struct clk_si544_muldiv *settings)
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{
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int err;
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u8 reg[6];
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err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2);
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if (err)
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return err;
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settings->ls_div_bits = (reg[1] >> 4) & 0x07;
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settings->hs_div = (reg[1] & 0x07) << 8 | reg[0];
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err = regmap_bulk_read(data->regmap, SI544_REG_FBDIV0, reg, 6);
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if (err)
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return err;
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settings->fb_div_int = reg[4] | (reg[5] & 0x07) << 8;
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settings->fb_div_frac = reg[0] | reg[1] << 8 | reg[2] << 16 |
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reg[3] << 24;
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2019-05-07 16:51:10 +03:00
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err = regmap_bulk_read(data->regmap, SI544_REG_ADPLL_DELTA_M0, reg, 3);
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if (err)
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return err;
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/* Interpret as 24-bit signed number */
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settings->delta_m = reg[0] << 8 | reg[1] << 16 | reg[2] << 24;
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settings->delta_m >>= 8;
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2018-03-20 11:15:41 +03:00
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return 0;
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}
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2019-05-07 16:51:10 +03:00
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static int si544_set_delta_m(struct clk_si544 *data, s32 delta_m)
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{
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u8 reg[3];
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reg[0] = delta_m;
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reg[1] = delta_m >> 8;
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reg[2] = delta_m >> 16;
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return regmap_bulk_write(data->regmap, SI544_REG_ADPLL_DELTA_M0,
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reg, 3);
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}
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2018-03-20 11:15:41 +03:00
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static int si544_set_muldiv(struct clk_si544 *data,
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struct clk_si544_muldiv *settings)
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{
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int err;
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u8 reg[6];
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reg[0] = settings->hs_div;
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reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4;
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err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2);
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if (err < 0)
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return err;
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reg[0] = settings->fb_div_frac;
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reg[1] = settings->fb_div_frac >> 8;
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reg[2] = settings->fb_div_frac >> 16;
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reg[3] = settings->fb_div_frac >> 24;
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reg[4] = settings->fb_div_int;
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reg[5] = settings->fb_div_int >> 8;
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/*
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* Writing to SI544_REG_FBDIV40 triggers the clock change, so that
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* must be written last
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*/
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return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6);
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}
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static bool is_valid_frequency(const struct clk_si544 *data,
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unsigned long frequency)
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{
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unsigned long max_freq = 0;
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if (frequency < SI544_MIN_FREQ)
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return false;
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switch (data->speed_grade) {
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case si544a:
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max_freq = 1500000000;
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break;
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case si544b:
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max_freq = 800000000;
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break;
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case si544c:
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max_freq = 350000000;
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break;
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}
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return frequency <= max_freq;
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}
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/* Calculate divider settings for a given frequency */
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static int si544_calc_muldiv(struct clk_si544_muldiv *settings,
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unsigned long frequency)
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{
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u64 vco;
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u32 ls_freq;
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u32 tmp;
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u8 res;
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/* Determine the minimum value of LS_DIV and resulting target freq. */
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ls_freq = frequency;
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settings->ls_div_bits = 0;
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if (frequency >= MIN_HSDIV_FREQ) {
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settings->ls_div_bits = 0;
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} else {
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res = 1;
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tmp = 2 * HS_DIV_MAX;
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while (tmp <= (HS_DIV_MAX * 32)) {
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if (((u64)frequency * tmp) >= FVCO_MIN)
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break;
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++res;
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tmp <<= 1;
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}
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settings->ls_div_bits = res;
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ls_freq = frequency << res;
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}
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/* Determine minimum HS_DIV by rounding up */
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vco = FVCO_MIN + ls_freq - 1;
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do_div(vco, ls_freq);
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settings->hs_div = vco;
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/* round up to even number when required */
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if ((settings->hs_div & 1) &&
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(settings->hs_div > HS_DIV_MAX_ODD || settings->ls_div_bits))
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++settings->hs_div;
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/* Calculate VCO frequency (in 10..12GHz range) */
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vco = (u64)ls_freq * settings->hs_div;
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/* Calculate the integer part of the feedback divider */
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tmp = do_div(vco, FXO);
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settings->fb_div_int = vco;
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/* And the fractional bits using the remainder */
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vco = (u64)tmp << 32;
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vco += FXO / 2; /* Round to nearest multiple */
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do_div(vco, FXO);
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settings->fb_div_frac = vco;
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2019-05-07 16:51:10 +03:00
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/* Reset the frequency adjustment */
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settings->delta_m = 0;
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2018-03-20 11:15:41 +03:00
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return 0;
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}
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/* Calculate resulting frequency given the register settings */
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static unsigned long si544_calc_center_rate(
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const struct clk_si544_muldiv *settings)
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{
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u32 d = settings->hs_div * BIT(settings->ls_div_bits);
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u64 vco;
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/* Calculate VCO from the fractional part */
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vco = (u64)settings->fb_div_frac * FXO;
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vco += (FXO / 2);
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vco >>= 32;
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/* Add the integer part of the VCO frequency */
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vco += (u64)settings->fb_div_int * FXO;
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/* Apply divider to obtain the generated frequency */
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do_div(vco, d);
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return vco;
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}
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2019-05-07 16:51:10 +03:00
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static unsigned long si544_calc_rate(const struct clk_si544_muldiv *settings)
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{
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unsigned long rate = si544_calc_center_rate(settings);
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s64 delta = (s64)rate * (DELTA_M_FRAC_NUM * settings->delta_m);
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/*
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* The clock adjustment is much smaller than 1 Hz, round to the
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* nearest multiple. Apparently div64_s64 rounds towards zero, hence
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* check the sign and adjust into the proper direction.
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*/
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if (settings->delta_m < 0)
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delta -= ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN) / 2;
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else
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delta += ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN) / 2;
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delta = div64_s64(delta, ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN));
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return rate + delta;
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}
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2018-03-20 11:15:41 +03:00
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static unsigned long si544_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_si544 *data = to_clk_si544(hw);
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struct clk_si544_muldiv settings;
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int err;
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err = si544_get_muldiv(data, &settings);
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if (err)
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return 0;
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return si544_calc_rate(&settings);
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}
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static long si544_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_si544 *data = to_clk_si544(hw);
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if (!is_valid_frequency(data, rate))
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return -EINVAL;
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2019-05-07 16:51:10 +03:00
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/* The accuracy is less than 1 Hz, so any rate is possible */
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return rate;
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}
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2018-03-20 11:15:41 +03:00
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2019-05-07 16:51:10 +03:00
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/* Calculates the maximum "small" change, 950 * rate / 1000000 */
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static unsigned long si544_max_delta(unsigned long rate)
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{
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u64 num = rate;
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num *= DELTA_M_FRAC_NUM;
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do_div(num, DELTA_M_FRAC_DEN);
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return num;
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}
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static s32 si544_calc_delta(s32 delta, s32 max_delta)
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{
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s64 n = (s64)delta * DELTA_M_MAX;
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return div_s64(n, max_delta);
|
2018-03-20 11:15:41 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static int si544_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_si544 *data = to_clk_si544(hw);
|
|
|
|
struct clk_si544_muldiv settings;
|
2019-05-07 16:51:10 +03:00
|
|
|
unsigned long center;
|
|
|
|
long max_delta;
|
|
|
|
long delta;
|
2018-06-04 08:34:39 +03:00
|
|
|
unsigned int old_oe_state;
|
2018-03-20 11:15:41 +03:00
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!is_valid_frequency(data, rate))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2019-05-07 16:51:10 +03:00
|
|
|
/* Try using the frequency adjustment feature for a <= 950ppm change */
|
|
|
|
err = si544_get_muldiv(data, &settings);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
center = si544_calc_center_rate(&settings);
|
|
|
|
max_delta = si544_max_delta(center);
|
|
|
|
delta = rate - center;
|
|
|
|
|
|
|
|
if (abs(delta) <= max_delta)
|
|
|
|
return si544_set_delta_m(data,
|
|
|
|
si544_calc_delta(delta, max_delta));
|
|
|
|
|
|
|
|
/* Too big for the delta adjustment, need to reprogram */
|
2018-03-20 11:15:41 +03:00
|
|
|
err = si544_calc_muldiv(&settings, rate);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2018-06-04 08:34:39 +03:00
|
|
|
err = regmap_read(data->regmap, SI544_REG_OE_STATE, &old_oe_state);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2018-03-20 11:15:41 +03:00
|
|
|
si544_enable_output(data, false);
|
|
|
|
|
|
|
|
/* Allow FCAL for this frequency update */
|
|
|
|
err = regmap_write(data->regmap, SI544_REG_FCAL_OVR, 0);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
2019-05-07 16:51:10 +03:00
|
|
|
err = si544_set_delta_m(data, settings.delta_m);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2018-03-20 11:15:41 +03:00
|
|
|
|
|
|
|
err = si544_set_muldiv(data, &settings);
|
|
|
|
if (err < 0)
|
|
|
|
return err; /* Undefined state now, best to leave disabled */
|
|
|
|
|
|
|
|
/* Trigger calibration */
|
|
|
|
err = regmap_write(data->regmap, SI544_REG_CONTROL,
|
|
|
|
SI544_CONTROL_MS_ICAL2);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Applying a new frequency can take up to 10ms */
|
|
|
|
usleep_range(10000, 12000);
|
|
|
|
|
2018-06-04 08:34:39 +03:00
|
|
|
if (old_oe_state & SI544_OE_STATE_ODC_OE)
|
|
|
|
si544_enable_output(data, true);
|
2018-03-20 11:15:41 +03:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct clk_ops si544_clk_ops = {
|
2018-06-04 08:34:39 +03:00
|
|
|
.prepare = si544_prepare,
|
|
|
|
.unprepare = si544_unprepare,
|
|
|
|
.is_prepared = si544_is_prepared,
|
2018-03-20 11:15:41 +03:00
|
|
|
.recalc_rate = si544_recalc_rate,
|
|
|
|
.round_rate = si544_round_rate,
|
|
|
|
.set_rate = si544_set_rate,
|
|
|
|
};
|
|
|
|
|
|
|
|
static bool si544_regmap_is_volatile(struct device *dev, unsigned int reg)
|
|
|
|
{
|
|
|
|
switch (reg) {
|
|
|
|
case SI544_REG_CONTROL:
|
|
|
|
case SI544_REG_FCAL_OVR:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct regmap_config si544_regmap_config = {
|
|
|
|
.reg_bits = 8,
|
|
|
|
.val_bits = 8,
|
|
|
|
.cache_type = REGCACHE_RBTREE,
|
|
|
|
.max_register = SI544_REG_PAGE_SELECT,
|
|
|
|
.volatile_reg = si544_regmap_is_volatile,
|
|
|
|
};
|
|
|
|
|
2022-04-07 18:18:29 +03:00
|
|
|
static const struct i2c_device_id si544_id[] = {
|
|
|
|
{ "si544a", si544a },
|
|
|
|
{ "si544b", si544b },
|
|
|
|
{ "si544c", si544c },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, si544_id);
|
|
|
|
|
|
|
|
static int si544_probe(struct i2c_client *client)
|
2018-03-20 11:15:41 +03:00
|
|
|
{
|
|
|
|
struct clk_si544 *data;
|
|
|
|
struct clk_init_data init;
|
2022-04-07 18:18:29 +03:00
|
|
|
const struct i2c_device_id *id = i2c_match_id(si544_id, client);
|
2018-03-20 11:15:41 +03:00
|
|
|
int err;
|
|
|
|
|
|
|
|
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
|
|
|
|
if (!data)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
init.ops = &si544_clk_ops;
|
|
|
|
init.flags = 0;
|
|
|
|
init.num_parents = 0;
|
|
|
|
data->hw.init = &init;
|
|
|
|
data->i2c_client = client;
|
|
|
|
data->speed_grade = id->driver_data;
|
|
|
|
|
|
|
|
if (of_property_read_string(client->dev.of_node, "clock-output-names",
|
|
|
|
&init.name))
|
|
|
|
init.name = client->dev.of_node->name;
|
|
|
|
|
|
|
|
data->regmap = devm_regmap_init_i2c(client, &si544_regmap_config);
|
|
|
|
if (IS_ERR(data->regmap))
|
|
|
|
return PTR_ERR(data->regmap);
|
|
|
|
|
|
|
|
i2c_set_clientdata(client, data);
|
|
|
|
|
|
|
|
/* Select page 0, just to be sure, there appear to be no more */
|
|
|
|
err = regmap_write(data->regmap, SI544_REG_PAGE_SELECT, 0);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = devm_clk_hw_register(&client->dev, &data->hw);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&client->dev, "clock registration failed\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
err = devm_of_clk_add_hw_provider(&client->dev, of_clk_hw_simple_get,
|
|
|
|
&data->hw);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&client->dev, "unable to add clk provider\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id clk_si544_of_match[] = {
|
|
|
|
{ .compatible = "silabs,si544a" },
|
|
|
|
{ .compatible = "silabs,si544b" },
|
|
|
|
{ .compatible = "silabs,si544c" },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, clk_si544_of_match);
|
|
|
|
|
|
|
|
static struct i2c_driver si544_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "si544",
|
|
|
|
.of_match_table = clk_si544_of_match,
|
|
|
|
},
|
2022-04-07 18:18:29 +03:00
|
|
|
.probe_new = si544_probe,
|
2018-03-20 11:15:41 +03:00
|
|
|
.id_table = si544_id,
|
|
|
|
};
|
|
|
|
module_i2c_driver(si544_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
|
|
|
|
MODULE_DESCRIPTION("Si544 driver");
|
|
|
|
MODULE_LICENSE("GPL");
|