2008-09-23 19:35:38 +04:00
|
|
|
|
/*
|
2016-02-03 14:27:34 +03:00
|
|
|
|
* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
|
2008-09-23 19:35:38 +04:00
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
|
2016-02-03 14:27:34 +03:00
|
|
|
|
* Copyright (C) 2016 Freescale Semiconductor Inc.
|
2008-09-23 19:35:38 +04:00
|
|
|
|
*
|
|
|
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
|
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
|
|
|
* kind, whether express or implied.
|
|
|
|
|
*/
|
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
#include <linux/acpi.h>
|
2008-09-23 19:35:38 +04:00
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
|
#include <linux/spinlock.h>
|
|
|
|
|
#include <linux/io.h>
|
|
|
|
|
#include <linux/of.h>
|
|
|
|
|
#include <linux/of_gpio.h>
|
2016-02-03 14:27:34 +03:00
|
|
|
|
#include <linux/of_address.h>
|
2013-09-17 23:28:33 +04:00
|
|
|
|
#include <linux/of_irq.h>
|
2015-01-18 14:39:32 +03:00
|
|
|
|
#include <linux/of_platform.h>
|
2021-03-22 06:38:46 +03:00
|
|
|
|
#include <linux/property.h>
|
|
|
|
|
#include <linux/mod_devicetable.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 11:04:11 +03:00
|
|
|
|
#include <linux/slab.h>
|
2010-01-07 19:57:46 +03:00
|
|
|
|
#include <linux/irq.h>
|
2016-02-03 14:27:34 +03:00
|
|
|
|
#include <linux/gpio/driver.h>
|
2017-10-20 17:08:12 +03:00
|
|
|
|
#include <linux/bitops.h>
|
2019-10-11 03:56:43 +03:00
|
|
|
|
#include <linux/interrupt.h>
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
|
|
|
|
#define MPC8XXX_GPIO_PINS 32
|
|
|
|
|
|
|
|
|
|
#define GPIO_DIR 0x00
|
|
|
|
|
#define GPIO_ODR 0x04
|
|
|
|
|
#define GPIO_DAT 0x08
|
|
|
|
|
#define GPIO_IER 0x0c
|
|
|
|
|
#define GPIO_IMR 0x10
|
|
|
|
|
#define GPIO_ICR 0x14
|
2010-08-09 09:58:48 +04:00
|
|
|
|
#define GPIO_ICR2 0x18
|
2019-07-18 12:49:02 +03:00
|
|
|
|
#define GPIO_IBE 0x18
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
|
|
|
|
struct mpc8xxx_gpio_chip {
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct gpio_chip gc;
|
|
|
|
|
void __iomem *regs;
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spinlock_t lock;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2016-02-03 14:27:34 +03:00
|
|
|
|
int (*direction_output)(struct gpio_chip *chip,
|
|
|
|
|
unsigned offset, int value);
|
|
|
|
|
|
2012-02-15 01:06:50 +04:00
|
|
|
|
struct irq_domain *irq;
|
2022-01-19 04:04:32 +03:00
|
|
|
|
int irqn;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
};
|
|
|
|
|
|
2017-10-20 17:08:12 +03:00
|
|
|
|
/*
|
|
|
|
|
* This hardware has a big endian bit assignment such that GPIO line 0 is
|
|
|
|
|
* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
|
|
|
|
|
* This inline helper give the right bitmask for a certain line.
|
|
|
|
|
*/
|
|
|
|
|
static inline u32 mpc_pin2mask(unsigned int offset)
|
|
|
|
|
{
|
|
|
|
|
return BIT(31 - offset);
|
|
|
|
|
}
|
|
|
|
|
|
2009-08-12 09:57:39 +04:00
|
|
|
|
/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
|
|
|
|
|
* defined as output cannot be determined by reading GPDAT register,
|
|
|
|
|
* so we use shadow data register instead. The status of input pins
|
|
|
|
|
* is determined by reading GPDAT register.
|
|
|
|
|
*/
|
|
|
|
|
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
|
|
|
|
{
|
|
|
|
|
u32 val;
|
2015-12-07 12:34:28 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
2013-11-22 12:12:40 +04:00
|
|
|
|
u32 out_mask, out_shadow;
|
2009-08-12 09:57:39 +04:00
|
|
|
|
|
2016-02-22 10:24:01 +03:00
|
|
|
|
out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
|
|
|
|
|
val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
out_shadow = gc->bgpio_data & out_mask;
|
2013-11-22 12:12:40 +04:00
|
|
|
|
|
2017-10-20 17:08:12 +03:00
|
|
|
|
return !!((val | out_shadow) & mpc_pin2mask(gpio));
|
2009-08-12 09:57:39 +04:00
|
|
|
|
}
|
|
|
|
|
|
2016-02-03 14:27:34 +03:00
|
|
|
|
static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
|
|
|
|
|
unsigned int gpio, int val)
|
2008-09-23 19:35:38 +04:00
|
|
|
|
{
|
2015-12-07 12:34:28 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
2011-12-13 13:12:48 +04:00
|
|
|
|
/* GPIO 28..31 are input only on MPC5121 */
|
|
|
|
|
if (gpio >= 28)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2016-02-03 14:27:34 +03:00
|
|
|
|
return mpc8xxx_gc->direction_output(gc, gpio, val);
|
2011-12-13 13:12:48 +04:00
|
|
|
|
}
|
|
|
|
|
|
2016-02-03 14:27:34 +03:00
|
|
|
|
static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
|
|
|
|
|
unsigned int gpio, int val)
|
2015-07-16 22:08:23 +03:00
|
|
|
|
{
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
2015-07-16 22:08:23 +03:00
|
|
|
|
/* GPIO 0..3 are input only on MPC5125 */
|
|
|
|
|
if (gpio <= 3)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2016-02-03 14:27:34 +03:00
|
|
|
|
return mpc8xxx_gc->direction_output(gc, gpio, val);
|
2015-07-16 22:08:23 +03:00
|
|
|
|
}
|
|
|
|
|
|
2010-01-07 19:57:46 +03:00
|
|
|
|
static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
|
|
|
|
{
|
2015-12-07 12:34:28 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
|
|
|
|
if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
|
|
|
|
|
return irq_create_mapping(mpc8xxx_gc->irq, offset);
|
|
|
|
|
else
|
|
|
|
|
return -ENXIO;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-11 03:56:43 +03:00
|
|
|
|
static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
|
2010-01-07 19:57:46 +03:00
|
|
|
|
{
|
2019-10-11 03:56:43 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
|
2016-02-22 10:24:01 +03:00
|
|
|
|
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
2019-10-11 03:56:43 +03:00
|
|
|
|
unsigned long mask;
|
|
|
|
|
int i;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2016-02-22 10:24:01 +03:00
|
|
|
|
mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
|
|
|
|
|
& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
|
2019-10-11 03:56:43 +03:00
|
|
|
|
for_each_set_bit(i, &mask, 32)
|
2021-05-04 19:42:18 +03:00
|
|
|
|
generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
|
2019-10-11 03:56:43 +03:00
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 01:26:58 +03:00
|
|
|
|
static void mpc8xxx_irq_unmask(struct irq_data *d)
|
2010-01-07 19:57:46 +03:00
|
|
|
|
{
|
2011-03-09 01:26:58 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
|
|
|
|
|
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
|
2017-10-20 17:08:12 +03:00
|
|
|
|
| mpc_pin2mask(irqd_to_hwirq(d)));
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 01:26:58 +03:00
|
|
|
|
static void mpc8xxx_irq_mask(struct irq_data *d)
|
2010-01-07 19:57:46 +03:00
|
|
|
|
{
|
2011-03-09 01:26:58 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
|
|
|
|
|
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
|
2017-10-20 17:08:12 +03:00
|
|
|
|
& ~mpc_pin2mask(irqd_to_hwirq(d)));
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 01:26:58 +03:00
|
|
|
|
static void mpc8xxx_irq_ack(struct irq_data *d)
|
2010-01-07 19:57:46 +03:00
|
|
|
|
{
|
2011-03-09 01:26:58 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
|
2017-10-20 17:08:12 +03:00
|
|
|
|
mpc_pin2mask(irqd_to_hwirq(d)));
|
2010-01-07 19:57:46 +03:00
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 01:26:58 +03:00
|
|
|
|
static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
2010-01-07 19:57:46 +03:00
|
|
|
|
{
|
2011-03-09 01:26:58 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
switch (flow_type) {
|
|
|
|
|
case IRQ_TYPE_EDGE_FALLING:
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
|
|
|
|
|
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
|
2017-10-20 17:08:12 +03:00
|
|
|
|
| mpc_pin2mask(irqd_to_hwirq(d)));
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IRQ_TYPE_EDGE_BOTH:
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
|
|
|
|
|
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
|
2017-10-20 17:08:12 +03:00
|
|
|
|
& ~mpc_pin2mask(irqd_to_hwirq(d)));
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 01:26:58 +03:00
|
|
|
|
static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
2010-08-09 09:58:48 +04:00
|
|
|
|
{
|
2011-03-09 01:26:58 +03:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
2016-02-22 10:24:01 +03:00
|
|
|
|
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
2011-05-04 09:02:15 +04:00
|
|
|
|
unsigned long gpio = irqd_to_hwirq(d);
|
2010-08-09 09:58:48 +04:00
|
|
|
|
void __iomem *reg;
|
|
|
|
|
unsigned int shift;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
if (gpio < 16) {
|
2016-02-03 14:27:34 +03:00
|
|
|
|
reg = mpc8xxx_gc->regs + GPIO_ICR;
|
2010-08-09 09:58:48 +04:00
|
|
|
|
shift = (15 - gpio) * 2;
|
|
|
|
|
} else {
|
2016-02-03 14:27:34 +03:00
|
|
|
|
reg = mpc8xxx_gc->regs + GPIO_ICR2;
|
2010-08-09 09:58:48 +04:00
|
|
|
|
shift = (15 - (gpio % 16)) * 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (flow_type) {
|
|
|
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
|
|
|
case IRQ_TYPE_LEVEL_LOW:
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
|
2016-02-03 14:27:34 +03:00
|
|
|
|
| (2 << shift));
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-08-09 09:58:48 +04:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
|
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
|
2016-02-03 14:27:34 +03:00
|
|
|
|
| (1 << shift));
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-08-09 09:58:48 +04:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IRQ_TYPE_EDGE_BOTH:
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
2010-08-09 09:58:48 +04:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-01-07 19:57:46 +03:00
|
|
|
|
static struct irq_chip mpc8xxx_irq_chip = {
|
|
|
|
|
.name = "mpc8xxx-gpio",
|
2011-03-09 01:26:58 +03:00
|
|
|
|
.irq_unmask = mpc8xxx_irq_unmask,
|
|
|
|
|
.irq_mask = mpc8xxx_irq_mask,
|
|
|
|
|
.irq_ack = mpc8xxx_irq_ack,
|
2015-07-16 22:08:22 +03:00
|
|
|
|
/* this might get overwritten in mpc8xxx_probe() */
|
2011-03-09 01:26:58 +03:00
|
|
|
|
.irq_set_type = mpc8xxx_irq_set_type,
|
2010-01-07 19:57:46 +03:00
|
|
|
|
};
|
|
|
|
|
|
2013-10-11 21:37:30 +04:00
|
|
|
|
static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
|
|
|
|
|
irq_hw_number_t hwirq)
|
2010-01-07 19:57:46 +03:00
|
|
|
|
{
|
2013-10-11 21:37:30 +04:00
|
|
|
|
irq_set_chip_data(irq, h->host_data);
|
2016-10-21 10:31:28 +03:00
|
|
|
|
irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-04-27 15:54:07 +03:00
|
|
|
|
static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
|
2010-01-07 19:57:46 +03:00
|
|
|
|
.map = mpc8xxx_gpio_irq_map,
|
2012-01-25 04:09:13 +04:00
|
|
|
|
.xlate = irq_domain_xlate_twocell,
|
2010-01-07 19:57:46 +03:00
|
|
|
|
};
|
|
|
|
|
|
2015-07-16 22:08:22 +03:00
|
|
|
|
struct mpc8xxx_gpio_devtype {
|
|
|
|
|
int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
|
|
|
|
|
int (*gpio_get)(struct gpio_chip *, unsigned int);
|
|
|
|
|
int (*irq_set_type)(struct irq_data *, unsigned int);
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
|
|
|
|
|
.gpio_dir_out = mpc5121_gpio_dir_out,
|
|
|
|
|
.irq_set_type = mpc512x_irq_set_type,
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-16 22:08:23 +03:00
|
|
|
|
static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
|
|
|
|
|
.gpio_dir_out = mpc5125_gpio_dir_out,
|
|
|
|
|
.irq_set_type = mpc512x_irq_set_type,
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-16 22:08:22 +03:00
|
|
|
|
static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
|
|
|
|
|
.gpio_get = mpc8572_gpio_get,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
|
|
|
|
|
.irq_set_type = mpc8xxx_irq_set_type,
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-16 22:08:21 +03:00
|
|
|
|
static const struct of_device_id mpc8xxx_gpio_ids[] = {
|
2010-08-09 09:58:48 +04:00
|
|
|
|
{ .compatible = "fsl,mpc8349-gpio", },
|
2015-07-16 22:08:22 +03:00
|
|
|
|
{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
|
2010-08-09 09:58:48 +04:00
|
|
|
|
{ .compatible = "fsl,mpc8610-gpio", },
|
2015-07-16 22:08:22 +03:00
|
|
|
|
{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
|
2015-07-16 22:08:23 +03:00
|
|
|
|
{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
|
2011-10-23 01:20:42 +04:00
|
|
|
|
{ .compatible = "fsl,pq3-gpio", },
|
2020-09-30 10:42:11 +03:00
|
|
|
|
{ .compatible = "fsl,ls1028a-gpio", },
|
|
|
|
|
{ .compatible = "fsl,ls1088a-gpio", },
|
2011-01-08 18:51:16 +03:00
|
|
|
|
{ .compatible = "fsl,qoriq-gpio", },
|
2010-08-09 09:58:48 +04:00
|
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
|
2015-01-18 14:39:32 +03:00
|
|
|
|
static int mpc8xxx_probe(struct platform_device *pdev)
|
2008-09-23 19:35:38 +04:00
|
|
|
|
{
|
2015-01-18 14:39:32 +03:00
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
struct gpio_chip *gc;
|
2021-03-22 06:38:46 +03:00
|
|
|
|
const struct mpc8xxx_gpio_devtype *devtype = NULL;
|
|
|
|
|
struct fwnode_handle *fwnode;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
int ret;
|
|
|
|
|
|
2015-01-18 14:39:32 +03:00
|
|
|
|
mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
|
|
|
|
|
if (!mpc8xxx_gc)
|
|
|
|
|
return -ENOMEM;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2015-01-18 14:39:33 +03:00
|
|
|
|
platform_set_drvdata(pdev, mpc8xxx_gc);
|
|
|
|
|
|
2015-07-21 16:54:30 +03:00
|
|
|
|
raw_spin_lock_init(&mpc8xxx_gc->lock);
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
|
if (IS_ERR(mpc8xxx_gc->regs))
|
|
|
|
|
return PTR_ERR(mpc8xxx_gc->regs);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
|
|
|
|
|
gc = &mpc8xxx_gc->gc;
|
2019-11-26 09:51:11 +03:00
|
|
|
|
gc->parent = &pdev->dev;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
if (device_property_read_bool(&pdev->dev, "little-endian")) {
|
2016-02-03 14:27:34 +03:00
|
|
|
|
ret = bgpio_init(gc, &pdev->dev, 4,
|
|
|
|
|
mpc8xxx_gc->regs + GPIO_DAT,
|
|
|
|
|
NULL, NULL,
|
|
|
|
|
mpc8xxx_gc->regs + GPIO_DIR, NULL,
|
|
|
|
|
BGPIOF_BIG_ENDIAN);
|
|
|
|
|
if (ret)
|
2021-08-20 18:38:03 +03:00
|
|
|
|
return ret;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
|
|
|
|
|
} else {
|
|
|
|
|
ret = bgpio_init(gc, &pdev->dev, 4,
|
|
|
|
|
mpc8xxx_gc->regs + GPIO_DAT,
|
|
|
|
|
NULL, NULL,
|
|
|
|
|
mpc8xxx_gc->regs + GPIO_DIR, NULL,
|
|
|
|
|
BGPIOF_BIG_ENDIAN
|
|
|
|
|
| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
|
|
|
|
|
if (ret)
|
2021-08-20 18:38:03 +03:00
|
|
|
|
return ret;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
|
|
|
|
|
}
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2016-02-22 10:22:52 +03:00
|
|
|
|
mpc8xxx_gc->direction_output = gc->direction_output;
|
2015-07-16 22:08:22 +03:00
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
devtype = device_get_match_data(&pdev->dev);
|
2015-07-16 22:08:22 +03:00
|
|
|
|
if (!devtype)
|
|
|
|
|
devtype = &mpc8xxx_gpio_devtype_default;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* It's assumed that only a single type of gpio controller is available
|
|
|
|
|
* on the current machine, so overwriting global data is fine.
|
|
|
|
|
*/
|
gpio: mpc8xxx: Don't overwrite default irq_set_type callback
The per-SoC devtype structures can contain their own callbacks that
overwrite mpc8xxx_gpio_devtype_default.
The clear intention is that mpc8xxx_irq_set_type is used in case the SoC
does not specify a more specific callback. But what happens is that if
the SoC doesn't specify one, its .irq_set_type is de-facto NULL, and
this overwrites mpc8xxx_irq_set_type to a no-op. This means that the
following SoCs are affected:
- fsl,mpc8572-gpio
- fsl,ls1028a-gpio
- fsl,ls1088a-gpio
On these boards, the irq_set_type does exactly nothing, and the GPIO
controller keeps its GPICR register in the hardware-default state. On
the LS1028A, that is ACTIVE_BOTH, which means 2 interrupts are raised
even if the IRQ client requests LEVEL_HIGH. Another implication is that
the IRQs are not checked (e.g. level-triggered interrupts are not
rejected, although they are not supported).
Fixes: 82e39b0d8566 ("gpio: mpc8xxx: handle differences between incarnations at a single place")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20191115125551.31061-1-olteanv@gmail.com
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-15 15:55:51 +03:00
|
|
|
|
if (devtype->irq_set_type)
|
|
|
|
|
mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
|
2015-07-16 22:08:22 +03:00
|
|
|
|
|
2016-02-22 10:24:54 +03:00
|
|
|
|
if (devtype->gpio_dir_out)
|
|
|
|
|
gc->direction_output = devtype->gpio_dir_out;
|
|
|
|
|
if (devtype->gpio_get)
|
|
|
|
|
gc->get = devtype->gpio_get;
|
|
|
|
|
|
2010-01-07 19:57:46 +03:00
|
|
|
|
gc->to_irq = mpc8xxx_gpio_to_irq;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2020-09-30 10:42:11 +03:00
|
|
|
|
/*
|
|
|
|
|
* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
|
|
|
|
|
* the input enable of each individual GPIO port. When an individual
|
|
|
|
|
* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
|
|
|
|
|
* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
|
|
|
|
|
* the port value to the GPIO Data Register.
|
|
|
|
|
*/
|
2021-03-22 06:38:46 +03:00
|
|
|
|
fwnode = dev_fwnode(&pdev->dev);
|
2020-09-30 10:42:11 +03:00
|
|
|
|
if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
|
|
|
|
|
of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
|
2021-03-22 06:38:46 +03:00
|
|
|
|
of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
|
|
|
|
|
is_acpi_node(fwnode))
|
2019-11-19 16:10:38 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
|
|
|
|
|
|
2021-08-20 18:38:13 +03:00
|
|
|
|
ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
if (ret) {
|
2021-03-22 06:38:46 +03:00
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"GPIO chip registration failed with status %d\n", ret);
|
2021-08-20 18:38:03 +03:00
|
|
|
|
return ret;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
}
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
|
2022-01-14 09:48:20 +03:00
|
|
|
|
if (mpc8xxx_gc->irqn < 0)
|
|
|
|
|
return mpc8xxx_gc->irqn;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
|
|
|
|
|
MPC8XXX_GPIO_PINS,
|
|
|
|
|
&mpc8xxx_gpio_irq_ops,
|
|
|
|
|
mpc8xxx_gc);
|
|
|
|
|
|
2010-01-07 19:57:46 +03:00
|
|
|
|
if (!mpc8xxx_gc->irq)
|
2015-01-18 14:39:32 +03:00
|
|
|
|
return 0;
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
|
|
|
|
/* ack and mask all irqs */
|
2016-02-22 10:24:01 +03:00
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
|
|
|
|
|
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
|
2010-01-07 19:57:46 +03:00
|
|
|
|
|
2019-10-11 03:56:43 +03:00
|
|
|
|
ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
|
|
|
|
|
mpc8xxx_gpio_irq_cascade,
|
2021-07-02 16:37:12 +03:00
|
|
|
|
IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
|
2019-10-11 03:56:43 +03:00
|
|
|
|
mpc8xxx_gc);
|
|
|
|
|
if (ret) {
|
2021-03-22 06:38:46 +03:00
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"failed to devm_request_irq(%d), ret = %d\n",
|
|
|
|
|
mpc8xxx_gc->irqn, ret);
|
2019-10-11 03:56:43 +03:00
|
|
|
|
goto err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-18 14:39:33 +03:00
|
|
|
|
return 0;
|
2016-02-03 14:27:34 +03:00
|
|
|
|
err:
|
2021-08-20 18:38:03 +03:00
|
|
|
|
irq_domain_remove(mpc8xxx_gc->irq);
|
2016-02-03 14:27:34 +03:00
|
|
|
|
return ret;
|
2015-01-18 14:39:33 +03:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc8xxx_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
if (mpc8xxx_gc->irq) {
|
2015-06-21 22:10:46 +03:00
|
|
|
|
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
|
2015-01-18 14:39:33 +03:00
|
|
|
|
irq_domain_remove(mpc8xxx_gc->irq);
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-18 14:39:32 +03:00
|
|
|
|
return 0;
|
2008-09-23 19:35:38 +04:00
|
|
|
|
}
|
|
|
|
|
|
2021-03-22 06:38:46 +03:00
|
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
|
static const struct acpi_device_id gpio_acpi_ids[] = {
|
|
|
|
|
{"NXP0031",},
|
|
|
|
|
{ }
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
|
|
|
|
|
#endif
|
|
|
|
|
|
2015-01-18 14:39:32 +03:00
|
|
|
|
static struct platform_driver mpc8xxx_plat_driver = {
|
|
|
|
|
.probe = mpc8xxx_probe,
|
2015-01-18 14:39:33 +03:00
|
|
|
|
.remove = mpc8xxx_remove,
|
2015-01-18 14:39:32 +03:00
|
|
|
|
.driver = {
|
|
|
|
|
.name = "gpio-mpc8xxx",
|
|
|
|
|
.of_match_table = mpc8xxx_gpio_ids,
|
2021-03-22 06:38:46 +03:00
|
|
|
|
.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
|
2015-01-18 14:39:32 +03:00
|
|
|
|
},
|
|
|
|
|
};
|
2008-09-23 19:35:38 +04:00
|
|
|
|
|
2015-01-18 14:39:32 +03:00
|
|
|
|
static int __init mpc8xxx_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_register(&mpc8xxx_plat_driver);
|
2008-09-23 19:35:38 +04:00
|
|
|
|
}
|
2015-01-18 14:39:32 +03:00
|
|
|
|
|
|
|
|
|
arch_initcall(mpc8xxx_init);
|