2008-07-01 22:43:24 +04:00
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#include <linux/kernel.h>
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2008-07-01 22:43:18 +04:00
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/timer.h>
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2008-07-01 22:43:24 +04:00
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#include <linux/acpi_pmtmr.h>
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2008-07-01 22:43:31 +04:00
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#include <linux/cpufreq.h>
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2008-07-01 22:43:34 +04:00
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#include <linux/delay.h>
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#include <linux/clocksource.h>
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#include <linux/percpu.h>
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2009-06-17 02:31:12 +04:00
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#include <linux/timex.h>
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2008-07-01 22:43:24 +04:00
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#include <asm/hpet.h>
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2008-07-01 22:43:34 +04:00
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#include <asm/timer.h>
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#include <asm/vgtod.h>
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#include <asm/time.h>
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#include <asm/delay.h>
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2008-10-27 20:41:46 +03:00
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#include <asm/hypervisor.h>
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2009-08-20 18:27:41 +04:00
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#include <asm/nmi.h>
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2009-08-20 19:06:25 +04:00
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#include <asm/x86_init.h>
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2008-07-01 22:43:18 +04:00
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2009-03-10 21:02:30 +03:00
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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2008-07-01 22:43:18 +04:00
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EXPORT_SYMBOL(cpu_khz);
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2009-03-10 21:02:30 +03:00
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unsigned int __read_mostly tsc_khz;
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2008-07-01 22:43:18 +04:00
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EXPORT_SYMBOL(tsc_khz);
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/*
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* TSC can be unstable due to cpufreq or due to unsynced TSCs
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*/
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2009-03-10 21:02:30 +03:00
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static int __read_mostly tsc_unstable;
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2008-07-01 22:43:18 +04:00
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/* native_sched_clock() is called before tsc_init(), so
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we must start with the TSC soft disabled to prevent
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erroneous rdtsc usage on !cpu_has_tsc processors */
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2009-03-10 21:02:30 +03:00
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static int __read_mostly tsc_disabled = -1;
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2008-07-01 22:43:18 +04:00
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2011-11-05 02:42:17 +04:00
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int tsc_clocksource_reliable;
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2008-07-01 22:43:18 +04:00
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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u64 native_sched_clock(void)
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{
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u64 this_offset;
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/*
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* Fall back to jiffies if there's no TSC available:
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* ( But note that we still use it if the TSC is marked
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* unstable. We do this because unlike Time Of Day,
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* the scheduler clock tolerates small errors and it's
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* very important for it to be as fast as the platform
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tree-wide: Assorted spelling fixes
In particular, several occurances of funny versions of 'success',
'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address',
'beginning', 'desirable', 'separate' and 'necessary' are fixed.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Joe Perches <joe@perches.com>
Cc: Junio C Hamano <gitster@pobox.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-02-03 03:01:28 +03:00
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* can achieve it. )
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2008-07-01 22:43:18 +04:00
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*/
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if (unlikely(tsc_disabled)) {
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/* No locking but a rare wrong value is not a big deal: */
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return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
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}
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/* read the Time Stamp Counter: */
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rdtscll(this_offset);
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/* return the value in ns */
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2008-11-08 19:05:38 +03:00
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return __cycles_2_ns(this_offset);
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2008-07-01 22:43:18 +04:00
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}
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/* We need to define a real function for sched_clock, to override the
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weak default version */
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#ifdef CONFIG_PARAVIRT
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unsigned long long sched_clock(void)
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{
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return paravirt_sched_clock();
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}
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#else
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unsigned long long
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sched_clock(void) __attribute__((alias("native_sched_clock")));
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#endif
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int check_tsc_unstable(void)
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{
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return tsc_unstable;
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}
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EXPORT_SYMBOL_GPL(check_tsc_unstable);
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#ifdef CONFIG_X86_TSC
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int __init notsc_setup(char *str)
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{
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printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
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"cannot disable TSC completely.\n");
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tsc_disabled = 1;
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return 1;
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}
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#else
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/*
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* disable flag for tsc. Takes effect by clearing the TSC cpu flag
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* in cpu/common.c
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*/
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int __init notsc_setup(char *str)
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{
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setup_clear_cpu_cap(X86_FEATURE_TSC);
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return 1;
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}
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#endif
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__setup("notsc", notsc_setup);
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2008-07-01 22:43:24 +04:00
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2010-10-05 04:03:20 +04:00
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static int no_sched_irq_time;
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2008-10-25 04:22:01 +04:00
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static int __init tsc_setup(char *str)
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{
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if (!strcmp(str, "reliable"))
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tsc_clocksource_reliable = 1;
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2010-10-05 04:03:20 +04:00
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if (!strncmp(str, "noirqtime", 9))
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no_sched_irq_time = 1;
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2008-10-25 04:22:01 +04:00
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return 1;
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}
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__setup("tsc=", tsc_setup);
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2008-07-01 22:43:24 +04:00
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#define MAX_RETRIES 5
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#define SMI_TRESHOLD 50000
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/*
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* Read TSC and the reference counters. Take care of SMI disturbance
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*/
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2008-09-04 19:18:53 +04:00
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static u64 tsc_read_refs(u64 *p, int hpet)
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2008-07-01 22:43:24 +04:00
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{
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u64 t1, t2;
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int i;
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for (i = 0; i < MAX_RETRIES; i++) {
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t1 = get_cycles();
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if (hpet)
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2008-09-04 19:18:53 +04:00
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*p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
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2008-07-01 22:43:24 +04:00
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else
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2008-09-04 19:18:53 +04:00
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*p = acpi_pm_read_early();
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2008-07-01 22:43:24 +04:00
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t2 = get_cycles();
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if ((t2 - t1) < SMI_TRESHOLD)
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return t2;
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}
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return ULLONG_MAX;
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}
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2008-09-04 19:18:48 +04:00
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/*
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* Calculate the TSC frequency from HPET reference
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2008-07-01 22:43:24 +04:00
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*/
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2008-09-04 19:18:48 +04:00
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static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
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2008-07-01 22:43:24 +04:00
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{
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2008-09-04 19:18:48 +04:00
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u64 tmp;
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2008-07-01 22:43:24 +04:00
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2008-09-04 19:18:48 +04:00
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if (hpet2 < hpet1)
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hpet2 += 0x100000000ULL;
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hpet2 -= hpet1;
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tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
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do_div(tmp, 1000000);
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do_div(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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/*
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* Calculate the TSC frequency from PMTimer reference
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*/
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static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
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{
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u64 tmp;
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2008-07-01 22:43:24 +04:00
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2008-09-04 19:18:48 +04:00
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if (!pm1 && !pm2)
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return ULONG_MAX;
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if (pm2 < pm1)
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pm2 += (u64)ACPI_PM_OVRRUN;
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pm2 -= pm1;
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tmp = pm2 * 1000000000LL;
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do_div(tmp, PMTMR_TICKS_PER_SEC);
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do_div(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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2008-09-04 19:18:59 +04:00
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#define CAL_MS 10
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2011-11-02 01:25:07 +04:00
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#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
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2008-09-04 19:18:59 +04:00
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#define CAL_PIT_LOOPS 1000
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#define CAL2_MS 50
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2011-11-02 01:25:07 +04:00
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#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
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2008-09-04 19:18:59 +04:00
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#define CAL2_PIT_LOOPS 5000
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2008-09-04 19:18:44 +04:00
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2008-09-03 18:30:13 +04:00
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/*
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* Try to calibrate the TSC against the Programmable
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* Interrupt Timer and return the frequency of the TSC
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* in kHz.
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*
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* Return ULONG_MAX on failure to calibrate.
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*/
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2008-09-04 19:18:59 +04:00
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static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
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2008-09-03 18:30:13 +04:00
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{
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u64 tsc, t1, t2, delta;
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unsigned long tscmin, tscmax;
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int pitcnt;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Setup CTC channel 2* for mode 0, (interrupt on terminal
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* count mode), binary count. Set the latch register to 50ms
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* (LSB then MSB) to begin countdown.
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*/
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outb(0xb0, 0x43);
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2008-09-04 19:18:59 +04:00
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outb(latch & 0xff, 0x42);
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outb(latch >> 8, 0x42);
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2008-09-03 18:30:13 +04:00
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tsc = t1 = t2 = get_cycles();
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pitcnt = 0;
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tscmax = 0;
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tscmin = ULONG_MAX;
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while ((inb(0x61) & 0x20) == 0) {
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t2 = get_cycles();
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delta = t2 - tsc;
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tsc = t2;
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if ((unsigned long) delta < tscmin)
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tscmin = (unsigned int) delta;
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if ((unsigned long) delta > tscmax)
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tscmax = (unsigned int) delta;
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pitcnt++;
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}
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/*
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* Sanity checks:
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*
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2008-09-04 19:18:59 +04:00
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* If we were not able to read the PIT more than loopmin
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2008-09-03 18:30:13 +04:00
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* times, then we have been hit by a massive SMI
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*
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* If the maximum is 10 times larger than the minimum,
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* then we got hit by an SMI as well.
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*/
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2008-09-04 19:18:59 +04:00
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if (pitcnt < loopmin || tscmax > 10 * tscmin)
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2008-09-03 18:30:13 +04:00
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return ULONG_MAX;
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/* Calculate the PIT value */
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delta = t2 - t1;
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2008-09-04 19:18:59 +04:00
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do_div(delta, ms);
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2008-09-03 18:30:13 +04:00
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return delta;
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}
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x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
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/*
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* This reads the current MSB of the PIT counter, and
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* checks if we are running on sufficiently fast and
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* non-virtualized hardware.
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*
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* Our expectations are:
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*
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* - the PIT is running at roughly 1.19MHz
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*
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* - each IO is going to take about 1us on real hardware,
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* but we allow it to be much faster (by a factor of 10) or
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* _slightly_ slower (ie we allow up to a 2us read+counter
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* update - anything else implies a unacceptably slow CPU
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* or PIT for the fast calibration to work.
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*
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* - with 256 PIT ticks to read the value, we have 214us to
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* see the same MSB (and overhead like doing a single TSC
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* read per MSB value etc).
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*
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* - We're doing 2 reads per loop (LSB, MSB), and we expect
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* them each to take about a microsecond on real hardware.
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* So we expect a count value of around 100. But we'll be
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* generous, and accept anything over 50.
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*
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* - if the PIT is stuck, and we see *many* more reads, we
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* return early (and the next caller of pit_expect_msb()
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* then consider it a failure when they don't see the
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* next expected value).
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*
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* These expectations mean that we know that we have seen the
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* transition from one expected value to another with a fairly
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* high accuracy, and we didn't miss any events. We can thus
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* use the TSC value at the transitions to calculate a pretty
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* good value for the TSC frequencty.
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*/
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2009-07-31 23:45:41 +04:00
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static inline int pit_verify_msb(unsigned char val)
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{
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/* Ignore LSB */
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inb(0x42);
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return inb(0x42) == val;
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}
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Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
{
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
int count;
|
x86, tsc: Fix SMI induced variation in quick_pit_calibrate()
pit_expect_msb() returns success wrongly in the below SMI scenario:
a. pit_verify_msb() has not yet seen the MSB transition.
b. we are close to the MSB transition though and got a SMI immediately after
returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
transition has happened somewhere during SMI execution.
c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
transition, we are way off because of the SMI. And as the SMI happened
between the pit_verify_msb() and before the 'tsc' is recorded in the
for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
quick_pit_calibrate() will not notice this error.
Depending on whether SMI disturbance happens while computing d1 or d2, we will
see the TSC calibrated value smaller or bigger than the expected value. As a
result, in a cluster we were seeing a variation of approximately +/- 20MHz in
the calibrated values, resulting in NTP failures.
[ As far as the SMI source is concerned, this is a periodic SMI that gets
disabled after ACPI is enabled by the OS. But the TSC calibration happens
before the ACPI is enabled. ]
To address this, change pit_expect_msb() so that
- the 'tsc' is the TSC in between the two reads that read the MSB
change from the PIT (same as before)
- the 'delta' is the difference in TSC from *before* the MSB changed
to *after* the MSB changed.
Now the delta is twice as big as before (it covers four PIT accesses,
roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
the calibrated value with in the 500ppm precision. As the delta (d1/d2)
covers four PIT accesses, actual calibrated result might be closer to
250ppm precision.
As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
SMI disturbance will showup as much larger delta's and the loop will take
longer than usual for the result to be with in the accepted precision. Or will
fallback to slow PIT calibration if it takes more than 50msec.
Also while we are at this, remove the calibration correction that aims to
get the result to the middle of the error bars. We really don't know which
direction to correct into, so remove it.
Reported-and-tested-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-01-18 03:35:37 +04:00
|
|
|
u64 tsc = 0, prev_tsc = 0;
|
2008-07-01 22:43:24 +04:00
|
|
|
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
for (count = 0; count < 50000; count++) {
|
2009-07-31 23:45:41 +04:00
|
|
|
if (!pit_verify_msb(val))
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
break;
|
x86, tsc: Fix SMI induced variation in quick_pit_calibrate()
pit_expect_msb() returns success wrongly in the below SMI scenario:
a. pit_verify_msb() has not yet seen the MSB transition.
b. we are close to the MSB transition though and got a SMI immediately after
returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
transition has happened somewhere during SMI execution.
c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
transition, we are way off because of the SMI. And as the SMI happened
between the pit_verify_msb() and before the 'tsc' is recorded in the
for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
quick_pit_calibrate() will not notice this error.
Depending on whether SMI disturbance happens while computing d1 or d2, we will
see the TSC calibrated value smaller or bigger than the expected value. As a
result, in a cluster we were seeing a variation of approximately +/- 20MHz in
the calibrated values, resulting in NTP failures.
[ As far as the SMI source is concerned, this is a periodic SMI that gets
disabled after ACPI is enabled by the OS. But the TSC calibration happens
before the ACPI is enabled. ]
To address this, change pit_expect_msb() so that
- the 'tsc' is the TSC in between the two reads that read the MSB
change from the PIT (same as before)
- the 'delta' is the difference in TSC from *before* the MSB changed
to *after* the MSB changed.
Now the delta is twice as big as before (it covers four PIT accesses,
roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
the calibrated value with in the 500ppm precision. As the delta (d1/d2)
covers four PIT accesses, actual calibrated result might be closer to
250ppm precision.
As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
SMI disturbance will showup as much larger delta's and the loop will take
longer than usual for the result to be with in the accepted precision. Or will
fallback to slow PIT calibration if it takes more than 50msec.
Also while we are at this, remove the calibration correction that aims to
get the result to the middle of the error bars. We really don't know which
direction to correct into, so remove it.
Reported-and-tested-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-01-18 03:35:37 +04:00
|
|
|
prev_tsc = tsc;
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
tsc = get_cycles();
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
}
|
x86, tsc: Fix SMI induced variation in quick_pit_calibrate()
pit_expect_msb() returns success wrongly in the below SMI scenario:
a. pit_verify_msb() has not yet seen the MSB transition.
b. we are close to the MSB transition though and got a SMI immediately after
returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
transition has happened somewhere during SMI execution.
c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
transition, we are way off because of the SMI. And as the SMI happened
between the pit_verify_msb() and before the 'tsc' is recorded in the
for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
quick_pit_calibrate() will not notice this error.
Depending on whether SMI disturbance happens while computing d1 or d2, we will
see the TSC calibrated value smaller or bigger than the expected value. As a
result, in a cluster we were seeing a variation of approximately +/- 20MHz in
the calibrated values, resulting in NTP failures.
[ As far as the SMI source is concerned, this is a periodic SMI that gets
disabled after ACPI is enabled by the OS. But the TSC calibration happens
before the ACPI is enabled. ]
To address this, change pit_expect_msb() so that
- the 'tsc' is the TSC in between the two reads that read the MSB
change from the PIT (same as before)
- the 'delta' is the difference in TSC from *before* the MSB changed
to *after* the MSB changed.
Now the delta is twice as big as before (it covers four PIT accesses,
roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
the calibrated value with in the 500ppm precision. As the delta (d1/d2)
covers four PIT accesses, actual calibrated result might be closer to
250ppm precision.
As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
SMI disturbance will showup as much larger delta's and the loop will take
longer than usual for the result to be with in the accepted precision. Or will
fallback to slow PIT calibration if it takes more than 50msec.
Also while we are at this, remove the calibration correction that aims to
get the result to the middle of the error bars. We really don't know which
direction to correct into, so remove it.
Reported-and-tested-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-01-18 03:35:37 +04:00
|
|
|
*deltap = get_cycles() - prev_tsc;
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
*tscp = tsc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We require _some_ success, but the quality control
|
|
|
|
* will be based on the error terms on the TSC values.
|
|
|
|
*/
|
|
|
|
return count > 5;
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
* How many MSB values do we want to see? We aim for
|
|
|
|
* a maximum error rate of 500ppm (in practice the
|
|
|
|
* real error is much smaller), but refuse to spend
|
x86, tsc: Fix SMI induced variation in quick_pit_calibrate()
pit_expect_msb() returns success wrongly in the below SMI scenario:
a. pit_verify_msb() has not yet seen the MSB transition.
b. we are close to the MSB transition though and got a SMI immediately after
returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
transition has happened somewhere during SMI execution.
c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
transition, we are way off because of the SMI. And as the SMI happened
between the pit_verify_msb() and before the 'tsc' is recorded in the
for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
quick_pit_calibrate() will not notice this error.
Depending on whether SMI disturbance happens while computing d1 or d2, we will
see the TSC calibrated value smaller or bigger than the expected value. As a
result, in a cluster we were seeing a variation of approximately +/- 20MHz in
the calibrated values, resulting in NTP failures.
[ As far as the SMI source is concerned, this is a periodic SMI that gets
disabled after ACPI is enabled by the OS. But the TSC calibration happens
before the ACPI is enabled. ]
To address this, change pit_expect_msb() so that
- the 'tsc' is the TSC in between the two reads that read the MSB
change from the PIT (same as before)
- the 'delta' is the difference in TSC from *before* the MSB changed
to *after* the MSB changed.
Now the delta is twice as big as before (it covers four PIT accesses,
roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
the calibrated value with in the 500ppm precision. As the delta (d1/d2)
covers four PIT accesses, actual calibrated result might be closer to
250ppm precision.
As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
SMI disturbance will showup as much larger delta's and the loop will take
longer than usual for the result to be with in the accepted precision. Or will
fallback to slow PIT calibration if it takes more than 50msec.
Also while we are at this, remove the calibration correction that aims to
get the result to the middle of the error bars. We really don't know which
direction to correct into, so remove it.
Reported-and-tested-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-01-18 03:35:37 +04:00
|
|
|
* more than 50ms on it.
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
*/
|
x86, tsc: Fix SMI induced variation in quick_pit_calibrate()
pit_expect_msb() returns success wrongly in the below SMI scenario:
a. pit_verify_msb() has not yet seen the MSB transition.
b. we are close to the MSB transition though and got a SMI immediately after
returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
transition has happened somewhere during SMI execution.
c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
transition, we are way off because of the SMI. And as the SMI happened
between the pit_verify_msb() and before the 'tsc' is recorded in the
for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
quick_pit_calibrate() will not notice this error.
Depending on whether SMI disturbance happens while computing d1 or d2, we will
see the TSC calibrated value smaller or bigger than the expected value. As a
result, in a cluster we were seeing a variation of approximately +/- 20MHz in
the calibrated values, resulting in NTP failures.
[ As far as the SMI source is concerned, this is a periodic SMI that gets
disabled after ACPI is enabled by the OS. But the TSC calibration happens
before the ACPI is enabled. ]
To address this, change pit_expect_msb() so that
- the 'tsc' is the TSC in between the two reads that read the MSB
change from the PIT (same as before)
- the 'delta' is the difference in TSC from *before* the MSB changed
to *after* the MSB changed.
Now the delta is twice as big as before (it covers four PIT accesses,
roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
the calibrated value with in the 500ppm precision. As the delta (d1/d2)
covers four PIT accesses, actual calibrated result might be closer to
250ppm precision.
As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
SMI disturbance will showup as much larger delta's and the loop will take
longer than usual for the result to be with in the accepted precision. Or will
fallback to slow PIT calibration if it takes more than 50msec.
Also while we are at this, remove the calibration correction that aims to
get the result to the middle of the error bars. We really don't know which
direction to correct into, so remove it.
Reported-and-tested-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-01-18 03:35:37 +04:00
|
|
|
#define MAX_QUICK_PIT_MS 50
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
|
2008-07-01 22:43:24 +04:00
|
|
|
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
static unsigned long quick_pit_calibrate(void)
|
|
|
|
{
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
int i;
|
|
|
|
u64 tsc, delta;
|
|
|
|
unsigned long d1, d2;
|
|
|
|
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
/* Set the Gate high, disable speaker */
|
2008-07-01 22:43:24 +04:00
|
|
|
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
|
|
|
|
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
/*
|
|
|
|
* Counter 2, mode 0 (one-shot), binary count
|
|
|
|
*
|
|
|
|
* NOTE! Mode 2 decrements by two (and then the
|
|
|
|
* output is flipped each time, giving the same
|
|
|
|
* final output frequency as a decrement-by-one),
|
|
|
|
* so mode 0 is much better when looking at the
|
|
|
|
* individual counts.
|
|
|
|
*/
|
2008-07-01 22:43:24 +04:00
|
|
|
outb(0xb0, 0x43);
|
|
|
|
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
/* Start at 0xffff */
|
|
|
|
outb(0xff, 0x42);
|
|
|
|
outb(0xff, 0x42);
|
|
|
|
|
2009-03-17 17:58:26 +03:00
|
|
|
/*
|
|
|
|
* The PIT starts counting at the next edge, so we
|
|
|
|
* need to delay for a microsecond. The easiest way
|
|
|
|
* to do that is to just read back the 16-bit counter
|
|
|
|
* once from the PIT.
|
|
|
|
*/
|
2009-07-31 23:45:41 +04:00
|
|
|
pit_verify_msb(0);
|
2009-03-17 17:58:26 +03:00
|
|
|
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
if (pit_expect_msb(0xff, &tsc, &d1)) {
|
|
|
|
for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
|
|
|
|
if (!pit_expect_msb(0xff-i, &delta, &d2))
|
|
|
|
break;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Iterate until the error is less than 500 ppm
|
|
|
|
*/
|
|
|
|
delta -= tsc;
|
2009-07-31 23:45:41 +04:00
|
|
|
if (d1+d2 >= delta >> 11)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check the PIT one more time to verify that
|
|
|
|
* all TSC reads were stable wrt the PIT.
|
|
|
|
*
|
|
|
|
* This also guarantees serialization of the
|
|
|
|
* last cycle read ('d2') in pit_expect_msb.
|
|
|
|
*/
|
|
|
|
if (!pit_verify_msb(0xfe - i))
|
|
|
|
break;
|
|
|
|
goto success;
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
}
|
|
|
|
}
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
printk("Fast TSC calibration failed\n");
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
return 0;
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
|
|
|
|
success:
|
|
|
|
/*
|
|
|
|
* Ok, if we get here, then we've seen the
|
|
|
|
* MSB of the PIT decrement 'i' times, and the
|
|
|
|
* error has shrunk to less than 500 ppm.
|
|
|
|
*
|
|
|
|
* As a result, we can depend on there not being
|
|
|
|
* any odd delays anywhere, and the TSC reads are
|
x86, tsc: Fix SMI induced variation in quick_pit_calibrate()
pit_expect_msb() returns success wrongly in the below SMI scenario:
a. pit_verify_msb() has not yet seen the MSB transition.
b. we are close to the MSB transition though and got a SMI immediately after
returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
transition has happened somewhere during SMI execution.
c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
transition, we are way off because of the SMI. And as the SMI happened
between the pit_verify_msb() and before the 'tsc' is recorded in the
for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
quick_pit_calibrate() will not notice this error.
Depending on whether SMI disturbance happens while computing d1 or d2, we will
see the TSC calibrated value smaller or bigger than the expected value. As a
result, in a cluster we were seeing a variation of approximately +/- 20MHz in
the calibrated values, resulting in NTP failures.
[ As far as the SMI source is concerned, this is a periodic SMI that gets
disabled after ACPI is enabled by the OS. But the TSC calibration happens
before the ACPI is enabled. ]
To address this, change pit_expect_msb() so that
- the 'tsc' is the TSC in between the two reads that read the MSB
change from the PIT (same as before)
- the 'delta' is the difference in TSC from *before* the MSB changed
to *after* the MSB changed.
Now the delta is twice as big as before (it covers four PIT accesses,
roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
the calibrated value with in the 500ppm precision. As the delta (d1/d2)
covers four PIT accesses, actual calibrated result might be closer to
250ppm precision.
As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
SMI disturbance will showup as much larger delta's and the loop will take
longer than usual for the result to be with in the accepted precision. Or will
fallback to slow PIT calibration if it takes more than 50msec.
Also while we are at this, remove the calibration correction that aims to
get the result to the middle of the error bars. We really don't know which
direction to correct into, so remove it.
Reported-and-tested-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-01-18 03:35:37 +04:00
|
|
|
* reliable (within the error).
|
Fast TSC calibration: calculate proper frequency error bounds
In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.
The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).
However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.
So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly. We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.
In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: Jesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-03-17 18:13:17 +03:00
|
|
|
*
|
|
|
|
* kHz = ticks / time-in-seconds / 1000;
|
|
|
|
* kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
|
|
|
|
* kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
|
|
|
|
*/
|
|
|
|
delta *= PIT_TICK_RATE;
|
|
|
|
do_div(delta, i*256*1000);
|
|
|
|
printk("Fast TSC calibration using PIT\n");
|
|
|
|
return delta;
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
}
|
2008-09-03 18:30:13 +04:00
|
|
|
|
2008-07-01 22:43:24 +04:00
|
|
|
/**
|
2008-07-01 22:43:36 +04:00
|
|
|
* native_calibrate_tsc - calibrate the tsc on boot
|
2008-07-01 22:43:24 +04:00
|
|
|
*/
|
2008-07-01 22:43:36 +04:00
|
|
|
unsigned long native_calibrate_tsc(void)
|
2008-07-01 22:43:24 +04:00
|
|
|
{
|
2008-09-04 19:18:53 +04:00
|
|
|
u64 tsc1, tsc2, delta, ref1, ref2;
|
2008-09-03 02:54:47 +04:00
|
|
|
unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
|
2009-08-20 19:06:25 +04:00
|
|
|
unsigned long flags, latch, ms, fast_calibrate;
|
2008-09-04 19:18:59 +04:00
|
|
|
int hpet = is_hpet_enabled(), i, loopmin;
|
2008-07-01 22:43:24 +04:00
|
|
|
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
local_irq_save(flags);
|
|
|
|
fast_calibrate = quick_pit_calibrate();
|
2008-07-01 22:43:24 +04:00
|
|
|
local_irq_restore(flags);
|
x86: quick TSC calibration
Introduce a fast TSC-calibration method on sane hardware.
It only uses 17920 PIT timer ticks to calibrate the TSC, plus 256 ticks on
each side to make sure the TSC values were very close to the tick, so the
whole calibration takes 15ms. Yet, despite only takign 15ms,
we can actually give pretty stringent guarantees of accuracy:
- the code requires that we hit each 256-counter block at least 50 times,
so the TSC error is basically at *MOST* just a few PIT cycles off in
any direction. In practice, it's going to be about one microseconds
off (which is how long it takes to read the counter)
- so over 17920 PIT cycles, we can pretty much guarantee that the
calibration error is less than one half of a percent.
My testing bears this out: on my machine, the quick-calibration reports
2934.085kHz, while the slow one reports 2933.415.
Yes, the slower calibration is still more precise. For me, the slow
calibration is stable to within about one hundreth of a percent, so it's
(at a guess) roughly an order-and-a-half of magnitude more precise. The
longer you wait, the more precise you can be.
However, the nice thing about the fast TSC PIT synchronization is that
it's pretty much _guaranteed_ to give that 0.5% precision, and fail
gracefully (and very quickly) if it doesn't get it. And it really is
fairly simple (even if there's a lot of _details_ there, and I didn't get
all of those right ont he first try or even the second ;)
The patch says "110 insertions", but 63 of those new lines are actually
comments.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 110 insertions(+), 1 deletions(-)
2008-09-04 21:41:22 +04:00
|
|
|
if (fast_calibrate)
|
|
|
|
return fast_calibrate;
|
2008-07-01 22:43:24 +04:00
|
|
|
|
2008-09-03 02:54:47 +04:00
|
|
|
/*
|
|
|
|
* Run 5 calibration loops to get the lowest frequency value
|
|
|
|
* (the best estimate). We use two different calibration modes
|
|
|
|
* here:
|
|
|
|
*
|
|
|
|
* 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
|
|
|
|
* load a timeout of 50ms. We read the time right after we
|
|
|
|
* started the timer and wait until the PIT count down reaches
|
|
|
|
* zero. In each wait loop iteration we read the TSC and check
|
|
|
|
* the delta to the previous read. We keep track of the min
|
|
|
|
* and max values of that delta. The delta is mostly defined
|
|
|
|
* by the IO time of the PIT access, so we can detect when a
|
2011-03-17 22:24:16 +03:00
|
|
|
* SMI/SMM disturbance happened between the two reads. If the
|
2008-09-03 02:54:47 +04:00
|
|
|
* maximum time is significantly larger than the minimum time,
|
|
|
|
* then we discard the result and have another try.
|
|
|
|
*
|
|
|
|
* 2) Reference counter. If available we use the HPET or the
|
|
|
|
* PMTIMER as a reference to check the sanity of that value.
|
|
|
|
* We use separate TSC readouts and check inside of the
|
|
|
|
* reference read for a SMI/SMM disturbance. We dicard
|
|
|
|
* disturbed values here as well. We do that around the PIT
|
|
|
|
* calibration delay loop as we have to wait for a certain
|
|
|
|
* amount of time anyway.
|
|
|
|
*/
|
2008-09-04 19:18:59 +04:00
|
|
|
|
|
|
|
/* Preset PIT loop values */
|
|
|
|
latch = CAL_LATCH;
|
|
|
|
ms = CAL_MS;
|
|
|
|
loopmin = CAL_PIT_LOOPS;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
2008-09-03 18:30:13 +04:00
|
|
|
unsigned long tsc_pit_khz;
|
2008-09-03 02:54:47 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Read the start value and the reference count of
|
2008-09-03 18:30:13 +04:00
|
|
|
* hpet/pmtimer when available. Then do the PIT
|
|
|
|
* calibration, which will take at least 50ms, and
|
|
|
|
* read the end value.
|
2008-09-03 02:54:47 +04:00
|
|
|
*/
|
2008-09-03 18:30:13 +04:00
|
|
|
local_irq_save(flags);
|
2008-09-04 19:18:53 +04:00
|
|
|
tsc1 = tsc_read_refs(&ref1, hpet);
|
2008-09-04 19:18:59 +04:00
|
|
|
tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
|
2008-09-04 19:18:53 +04:00
|
|
|
tsc2 = tsc_read_refs(&ref2, hpet);
|
2008-09-03 02:54:47 +04:00
|
|
|
local_irq_restore(flags);
|
|
|
|
|
2008-09-03 18:30:13 +04:00
|
|
|
/* Pick the lowest PIT TSC calibration so far */
|
|
|
|
tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
|
2008-09-03 02:54:47 +04:00
|
|
|
|
|
|
|
/* hpet or pmtimer available ? */
|
2011-01-14 20:06:28 +03:00
|
|
|
if (ref1 == ref2)
|
2008-09-03 02:54:47 +04:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Check, whether the sampling was disturbed by an SMI */
|
|
|
|
if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
tsc2 = (tsc2 - tsc1) * 1000000LL;
|
2008-09-04 19:18:48 +04:00
|
|
|
if (hpet)
|
2008-09-04 19:18:53 +04:00
|
|
|
tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
|
2008-09-04 19:18:48 +04:00
|
|
|
else
|
2008-09-04 19:18:53 +04:00
|
|
|
tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
|
2008-09-03 02:54:47 +04:00
|
|
|
|
|
|
|
tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
|
2008-09-04 19:18:59 +04:00
|
|
|
|
|
|
|
/* Check the reference deviation */
|
|
|
|
delta = ((u64) tsc_pit_min) * 100;
|
|
|
|
do_div(delta, tsc_ref_min);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If both calibration results are inside a 10% window
|
|
|
|
* then we can be sure, that the calibration
|
|
|
|
* succeeded. We break out of the loop right away. We
|
|
|
|
* use the reference value, as it is more precise.
|
|
|
|
*/
|
|
|
|
if (delta >= 90 && delta <= 110) {
|
|
|
|
printk(KERN_INFO
|
|
|
|
"TSC: PIT calibration matches %s. %d loops\n",
|
|
|
|
hpet ? "HPET" : "PMTIMER", i + 1);
|
|
|
|
return tsc_ref_min;
|
2008-09-03 02:54:47 +04:00
|
|
|
}
|
|
|
|
|
2008-09-04 19:18:59 +04:00
|
|
|
/*
|
|
|
|
* Check whether PIT failed more than once. This
|
|
|
|
* happens in virtualized environments. We need to
|
|
|
|
* give the virtual PC a slightly longer timeframe for
|
|
|
|
* the HPET/PMTIMER to make the result precise.
|
|
|
|
*/
|
|
|
|
if (i == 1 && tsc_pit_min == ULONG_MAX) {
|
|
|
|
latch = CAL2_LATCH;
|
|
|
|
ms = CAL2_MS;
|
|
|
|
loopmin = CAL2_PIT_LOOPS;
|
|
|
|
}
|
2008-09-03 02:54:47 +04:00
|
|
|
}
|
2008-07-01 22:43:24 +04:00
|
|
|
|
|
|
|
/*
|
2008-09-03 02:54:47 +04:00
|
|
|
* Now check the results.
|
2008-07-01 22:43:24 +04:00
|
|
|
*/
|
2008-09-03 02:54:47 +04:00
|
|
|
if (tsc_pit_min == ULONG_MAX) {
|
|
|
|
/* PIT gave no useful value */
|
2008-09-04 05:18:01 +04:00
|
|
|
printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
|
2008-09-03 02:54:47 +04:00
|
|
|
|
|
|
|
/* We don't have an alternative source, disable TSC */
|
2008-09-04 19:18:53 +04:00
|
|
|
if (!hpet && !ref1 && !ref2) {
|
2008-09-03 02:54:47 +04:00
|
|
|
printk("TSC: No reference (HPET/PMTIMER) available\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The alternative source failed as well, disable TSC */
|
|
|
|
if (tsc_ref_min == ULONG_MAX) {
|
|
|
|
printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
|
2008-09-04 19:18:59 +04:00
|
|
|
"failed.\n");
|
2008-09-03 02:54:47 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Use the alternative source */
|
|
|
|
printk(KERN_INFO "TSC: using %s reference calibration\n",
|
|
|
|
hpet ? "HPET" : "PMTIMER");
|
|
|
|
|
|
|
|
return tsc_ref_min;
|
|
|
|
}
|
2008-07-01 22:43:24 +04:00
|
|
|
|
2008-09-03 02:54:47 +04:00
|
|
|
/* We don't have an alternative source, use the PIT calibration value */
|
2008-09-04 19:18:53 +04:00
|
|
|
if (!hpet && !ref1 && !ref2) {
|
2008-09-03 02:54:47 +04:00
|
|
|
printk(KERN_INFO "TSC: Using PIT calibration value\n");
|
|
|
|
return tsc_pit_min;
|
2008-07-01 22:43:24 +04:00
|
|
|
}
|
|
|
|
|
2008-09-03 02:54:47 +04:00
|
|
|
/* The alternative source failed, use the PIT calibration value */
|
|
|
|
if (tsc_ref_min == ULONG_MAX) {
|
2008-09-04 19:18:59 +04:00
|
|
|
printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
|
|
|
|
"Using PIT calibration\n");
|
2008-09-03 02:54:47 +04:00
|
|
|
return tsc_pit_min;
|
2008-07-01 22:43:24 +04:00
|
|
|
}
|
|
|
|
|
2008-09-03 02:54:47 +04:00
|
|
|
/*
|
|
|
|
* The calibration values differ too much. In doubt, we use
|
|
|
|
* the PIT value as we know that there are PMTIMERs around
|
2008-09-04 19:18:59 +04:00
|
|
|
* running at double speed. At least we let the user know:
|
2008-09-03 02:54:47 +04:00
|
|
|
*/
|
2008-09-04 19:18:59 +04:00
|
|
|
printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
|
|
|
|
hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
|
2008-09-03 02:54:47 +04:00
|
|
|
printk(KERN_INFO "TSC: Using PIT calibration value\n");
|
|
|
|
return tsc_pit_min;
|
2008-07-01 22:43:24 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
int recalibrate_cpu_khz(void)
|
|
|
|
{
|
|
|
|
#ifndef CONFIG_SMP
|
|
|
|
unsigned long cpu_khz_old = cpu_khz;
|
|
|
|
|
|
|
|
if (cpu_has_tsc) {
|
2009-08-20 19:06:25 +04:00
|
|
|
tsc_khz = x86_platform.calibrate_tsc();
|
2008-07-01 22:43:36 +04:00
|
|
|
cpu_khz = tsc_khz;
|
2008-07-01 22:43:24 +04:00
|
|
|
cpu_data(0).loops_per_jiffy =
|
|
|
|
cpufreq_scale(cpu_data(0).loops_per_jiffy,
|
|
|
|
cpu_khz_old, cpu_khz);
|
|
|
|
return 0;
|
|
|
|
} else
|
|
|
|
return -ENODEV;
|
|
|
|
#else
|
|
|
|
return -ENODEV;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(recalibrate_cpu_khz);
|
|
|
|
|
2008-07-01 22:43:31 +04:00
|
|
|
|
|
|
|
/* Accelerators for sched_clock()
|
|
|
|
* convert from cycles(64bits) => nanoseconds (64bits)
|
|
|
|
* basic equation:
|
|
|
|
* ns = cycles / (freq / ns_per_sec)
|
|
|
|
* ns = cycles * (ns_per_sec / freq)
|
|
|
|
* ns = cycles * (10^9 / (cpu_khz * 10^3))
|
|
|
|
* ns = cycles * (10^6 / cpu_khz)
|
|
|
|
*
|
|
|
|
* Then we use scaling math (suggested by george@mvista.com) to get:
|
|
|
|
* ns = cycles * (10^6 * SC / cpu_khz) / SC
|
|
|
|
* ns = cycles * cyc2ns_scale / SC
|
|
|
|
*
|
|
|
|
* And since SC is a constant power of two, we can convert the div
|
|
|
|
* into a shift.
|
|
|
|
*
|
|
|
|
* We can use khz divisor instead of mhz to keep a better precision, since
|
|
|
|
* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
|
|
|
|
* (mathieu.desnoyers@polymtl.ca)
|
|
|
|
*
|
|
|
|
* -johnstul@us.ibm.com "math is hard, lets go shopping!"
|
|
|
|
*/
|
|
|
|
|
|
|
|
DEFINE_PER_CPU(unsigned long, cyc2ns);
|
2009-06-16 23:34:17 +04:00
|
|
|
DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
|
2008-07-01 22:43:31 +04:00
|
|
|
|
2008-07-01 22:43:34 +04:00
|
|
|
static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
|
2008-07-01 22:43:31 +04:00
|
|
|
{
|
2009-06-16 23:34:17 +04:00
|
|
|
unsigned long long tsc_now, ns_now, *offset;
|
2008-07-01 22:43:31 +04:00
|
|
|
unsigned long flags, *scale;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
sched_clock_idle_sleep_event();
|
|
|
|
|
|
|
|
scale = &per_cpu(cyc2ns, cpu);
|
2009-06-16 23:34:17 +04:00
|
|
|
offset = &per_cpu(cyc2ns_offset, cpu);
|
2008-07-01 22:43:31 +04:00
|
|
|
|
|
|
|
rdtscll(tsc_now);
|
|
|
|
ns_now = __cycles_2_ns(tsc_now);
|
|
|
|
|
2009-06-16 23:34:17 +04:00
|
|
|
if (cpu_khz) {
|
2008-07-01 22:43:31 +04:00
|
|
|
*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
|
2009-06-16 23:34:17 +04:00
|
|
|
*offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR);
|
|
|
|
}
|
2008-07-01 22:43:31 +04:00
|
|
|
|
|
|
|
sched_clock_idle_wakeup_event(0);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
2010-08-20 04:03:38 +04:00
|
|
|
static unsigned long long cyc2ns_suspend;
|
|
|
|
|
|
|
|
void save_sched_clock_state(void)
|
|
|
|
{
|
|
|
|
if (!sched_clock_stable)
|
|
|
|
return;
|
|
|
|
|
|
|
|
cyc2ns_suspend = sched_clock();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Even on processors with invariant TSC, TSC gets reset in some the
|
|
|
|
* ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
|
|
|
|
* arbitrary value (still sync'd across cpu's) during resume from such sleep
|
|
|
|
* states. To cope up with this, recompute the cyc2ns_offset for each cpu so
|
|
|
|
* that sched_clock() continues from the point where it was left off during
|
|
|
|
* suspend.
|
|
|
|
*/
|
|
|
|
void restore_sched_clock_state(void)
|
|
|
|
{
|
|
|
|
unsigned long long offset;
|
|
|
|
unsigned long flags;
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
if (!sched_clock_stable)
|
|
|
|
return;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
2010-12-18 18:28:55 +03:00
|
|
|
__this_cpu_write(cyc2ns_offset, 0);
|
2010-08-20 04:03:38 +04:00
|
|
|
offset = cyc2ns_suspend - sched_clock();
|
|
|
|
|
|
|
|
for_each_possible_cpu(cpu)
|
|
|
|
per_cpu(cyc2ns_offset, cpu) = offset;
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
2008-07-01 22:43:31 +04:00
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
|
|
|
|
/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
|
|
|
|
* changes.
|
|
|
|
*
|
|
|
|
* RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
|
|
|
|
* not that important because current Opteron setups do not support
|
|
|
|
* scaling on SMP anyroads.
|
|
|
|
*
|
|
|
|
* Should fix up last_tsc too. Currently gettimeofday in the
|
|
|
|
* first tick after the change will be slightly wrong.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static unsigned int ref_freq;
|
|
|
|
static unsigned long loops_per_jiffy_ref;
|
|
|
|
static unsigned long tsc_khz_ref;
|
|
|
|
|
|
|
|
static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
struct cpufreq_freqs *freq = data;
|
2009-06-01 20:29:55 +04:00
|
|
|
unsigned long *lpj;
|
2008-07-01 22:43:31 +04:00
|
|
|
|
|
|
|
if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
|
|
|
|
return 0;
|
|
|
|
|
2009-06-01 20:29:55 +04:00
|
|
|
lpj = &boot_cpu_data.loops_per_jiffy;
|
2008-07-01 22:43:31 +04:00
|
|
|
#ifdef CONFIG_SMP
|
2009-06-01 20:29:55 +04:00
|
|
|
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
|
2008-07-01 22:43:31 +04:00
|
|
|
lpj = &cpu_data(freq->cpu).loops_per_jiffy;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (!ref_freq) {
|
|
|
|
ref_freq = freq->old;
|
|
|
|
loops_per_jiffy_ref = *lpj;
|
|
|
|
tsc_khz_ref = tsc_khz;
|
|
|
|
}
|
|
|
|
if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
|
|
|
|
(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
|
|
|
|
(val == CPUFREQ_RESUMECHANGE)) {
|
2009-09-17 01:38:38 +04:00
|
|
|
*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
|
2008-07-01 22:43:31 +04:00
|
|
|
|
|
|
|
tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
|
|
|
|
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
|
|
|
|
mark_tsc_unstable("cpufreq changes");
|
|
|
|
}
|
|
|
|
|
2008-08-25 15:35:06 +04:00
|
|
|
set_cyc2ns_scale(tsc_khz, freq->cpu);
|
2008-07-01 22:43:31 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct notifier_block time_cpufreq_notifier_block = {
|
|
|
|
.notifier_call = time_cpufreq_notifier
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init cpufreq_tsc(void)
|
|
|
|
{
|
2008-08-24 22:52:06 +04:00
|
|
|
if (!cpu_has_tsc)
|
|
|
|
return 0;
|
|
|
|
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
|
|
|
|
return 0;
|
2008-07-01 22:43:31 +04:00
|
|
|
cpufreq_register_notifier(&time_cpufreq_notifier_block,
|
|
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
core_initcall(cpufreq_tsc);
|
|
|
|
|
|
|
|
#endif /* CONFIG_CPU_FREQ */
|
2008-07-01 22:43:34 +04:00
|
|
|
|
|
|
|
/* clocksource code */
|
|
|
|
|
|
|
|
static struct clocksource clocksource_tsc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We compare the TSC to the cycle_last value in the clocksource
|
|
|
|
* structure to avoid a nasty time-warp. This can be observed in a
|
|
|
|
* very small window right after one CPU updated cycle_last under
|
|
|
|
* xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
|
|
|
|
* is smaller than the cycle_last reference value due to a TSC which
|
|
|
|
* is slighty behind. This delta is nowhere else observable, but in
|
|
|
|
* that case it results in a forward time jump in the range of hours
|
|
|
|
* due to the unsigned delta calculation of the time keeping core
|
|
|
|
* code, which is necessary to support wrapping clocksources like pm
|
|
|
|
* timer.
|
|
|
|
*/
|
2009-04-21 23:24:00 +04:00
|
|
|
static cycle_t read_tsc(struct clocksource *cs)
|
2008-07-01 22:43:34 +04:00
|
|
|
{
|
|
|
|
cycle_t ret = (cycle_t)get_cycles();
|
|
|
|
|
|
|
|
return ret >= clocksource_tsc.cycle_last ?
|
|
|
|
ret : clocksource_tsc.cycle_last;
|
|
|
|
}
|
|
|
|
|
2010-02-03 01:41:39 +03:00
|
|
|
static void resume_tsc(struct clocksource *cs)
|
2009-08-14 17:47:20 +04:00
|
|
|
{
|
|
|
|
clocksource_tsc.cycle_last = 0;
|
|
|
|
}
|
|
|
|
|
2008-07-01 22:43:34 +04:00
|
|
|
static struct clocksource clocksource_tsc = {
|
|
|
|
.name = "tsc",
|
|
|
|
.rating = 300,
|
|
|
|
.read = read_tsc,
|
2009-08-14 17:47:20 +04:00
|
|
|
.resume = resume_tsc,
|
2008-07-01 22:43:34 +04:00
|
|
|
.mask = CLOCKSOURCE_MASK(64),
|
|
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
|
|
|
|
CLOCK_SOURCE_MUST_VERIFY,
|
|
|
|
#ifdef CONFIG_X86_64
|
2011-07-14 14:47:22 +04:00
|
|
|
.archdata = { .vclock_mode = VCLOCK_TSC },
|
2008-07-01 22:43:34 +04:00
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
void mark_tsc_unstable(char *reason)
|
|
|
|
{
|
|
|
|
if (!tsc_unstable) {
|
|
|
|
tsc_unstable = 1;
|
2009-12-17 23:27:02 +03:00
|
|
|
sched_clock_stable = 0;
|
2010-10-05 04:03:20 +04:00
|
|
|
disable_sched_clock_irqtime();
|
2009-08-28 22:25:24 +04:00
|
|
|
printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
|
2008-07-01 22:43:34 +04:00
|
|
|
/* Change only the rating, when not registered */
|
|
|
|
if (clocksource_tsc.mult)
|
2009-08-28 22:25:24 +04:00
|
|
|
clocksource_mark_unstable(&clocksource_tsc);
|
|
|
|
else {
|
|
|
|
clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
|
2008-07-01 22:43:34 +04:00
|
|
|
clocksource_tsc.rating = 0;
|
2009-08-28 22:25:24 +04:00
|
|
|
}
|
2008-07-01 22:43:34 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL_GPL(mark_tsc_unstable);
|
|
|
|
|
2008-10-25 04:22:01 +04:00
|
|
|
static void __init check_system_tsc_reliable(void)
|
|
|
|
{
|
2008-07-01 22:43:34 +04:00
|
|
|
#ifdef CONFIG_MGEODE_LX
|
2008-10-25 04:22:01 +04:00
|
|
|
/* RTSC counts during suspend */
|
2008-07-01 22:43:34 +04:00
|
|
|
#define RTSC_SUSP 0x100
|
|
|
|
unsigned long res_low, res_high;
|
|
|
|
|
|
|
|
rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
|
2010-01-18 00:44:44 +03:00
|
|
|
/* Geode_LX - the OLPC CPU has a very reliable TSC */
|
2008-07-01 22:43:34 +04:00
|
|
|
if (res_low & RTSC_SUSP)
|
2008-10-25 04:22:01 +04:00
|
|
|
tsc_clocksource_reliable = 1;
|
2008-07-01 22:43:34 +04:00
|
|
|
#endif
|
2008-10-25 04:22:01 +04:00
|
|
|
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
|
|
|
|
tsc_clocksource_reliable = 1;
|
|
|
|
}
|
2008-07-01 22:43:34 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Make an educated guess if the TSC is trustworthy and synchronized
|
|
|
|
* over all CPUs.
|
|
|
|
*/
|
|
|
|
__cpuinit int unsynchronized_tsc(void)
|
|
|
|
{
|
|
|
|
if (!cpu_has_tsc || tsc_unstable)
|
|
|
|
return 1;
|
|
|
|
|
2009-01-27 19:07:08 +03:00
|
|
|
#ifdef CONFIG_SMP
|
2008-07-01 22:43:34 +04:00
|
|
|
if (apic_is_clustered_box())
|
|
|
|
return 1;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
|
|
|
|
return 0;
|
2009-08-18 03:40:47 +04:00
|
|
|
|
|
|
|
if (tsc_clocksource_reliable)
|
|
|
|
return 0;
|
2008-07-01 22:43:34 +04:00
|
|
|
/*
|
|
|
|
* Intel systems are normally all synchronized.
|
|
|
|
* Exceptions must mark TSC as unstable:
|
|
|
|
*/
|
|
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
|
|
|
|
/* assume multi socket systems are not synchronized: */
|
|
|
|
if (num_possible_cpus() > 1)
|
2009-08-18 03:40:47 +04:00
|
|
|
return 1;
|
2008-07-01 22:43:34 +04:00
|
|
|
}
|
|
|
|
|
2009-08-18 03:40:47 +04:00
|
|
|
return 0;
|
2008-07-01 22:43:34 +04:00
|
|
|
}
|
|
|
|
|
2010-07-28 04:00:00 +04:00
|
|
|
|
|
|
|
static void tsc_refine_calibration_work(struct work_struct *work);
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static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
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/**
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* tsc_refine_calibration_work - Further refine tsc freq calibration
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* @work - ignored.
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*
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* This functions uses delayed work over a period of a
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* second to further refine the TSC freq value. Since this is
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* timer based, instead of loop based, we don't block the boot
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* process while this longer calibration is done.
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*
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2011-03-17 22:24:16 +03:00
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* If there are any calibration anomalies (too many SMIs, etc),
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2010-07-28 04:00:00 +04:00
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* or the refined calibration is off by 1% of the fast early
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* calibration, we throw out the new calibration and use the
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* early calibration.
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*/
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static void tsc_refine_calibration_work(struct work_struct *work)
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{
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static u64 tsc_start = -1, ref_start;
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static int hpet;
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u64 tsc_stop, ref_stop, delta;
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unsigned long freq;
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/* Don't bother refining TSC on unstable systems */
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if (check_tsc_unstable())
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goto out;
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/*
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* Since the work is started early in boot, we may be
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* delayed the first time we expire. So set the workqueue
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* again once we know timers are working.
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*/
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if (tsc_start == -1) {
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/*
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* Only set hpet once, to avoid mixing hardware
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* if the hpet becomes enabled later.
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*/
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hpet = is_hpet_enabled();
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schedule_delayed_work(&tsc_irqwork, HZ);
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tsc_start = tsc_read_refs(&ref_start, hpet);
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return;
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}
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tsc_stop = tsc_read_refs(&ref_stop, hpet);
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/* hpet or pmtimer available ? */
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2011-01-14 20:06:28 +03:00
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if (ref_start == ref_stop)
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2010-07-28 04:00:00 +04:00
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goto out;
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/* Check, whether the sampling was disturbed by an SMI */
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if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
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goto out;
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delta = tsc_stop - tsc_start;
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delta *= 1000000LL;
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if (hpet)
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freq = calc_hpet_ref(delta, ref_start, ref_stop);
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else
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freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
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/* Make sure we're within 1% */
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if (abs(tsc_khz - freq) > tsc_khz/100)
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goto out;
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tsc_khz = freq;
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printk(KERN_INFO "Refined TSC clocksource calibration: "
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"%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
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(unsigned long)tsc_khz % 1000);
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out:
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clocksource_register_khz(&clocksource_tsc, tsc_khz);
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}
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static int __init init_tsc_clocksource(void)
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2008-07-01 22:43:34 +04:00
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{
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2011-01-11 13:40:48 +03:00
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if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
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2010-12-13 13:28:02 +03:00
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return 0;
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2008-10-25 04:22:01 +04:00
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if (tsc_clocksource_reliable)
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clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
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2008-07-01 22:43:34 +04:00
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/* lower the rating if we already know its unstable: */
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if (check_tsc_unstable()) {
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clocksource_tsc.rating = 0;
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clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
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}
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2010-07-28 04:00:00 +04:00
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schedule_delayed_work(&tsc_irqwork, 0);
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return 0;
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2008-07-01 22:43:34 +04:00
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}
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2010-07-28 04:00:00 +04:00
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/*
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* We use device_initcall here, to ensure we run after the hpet
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* is fully initialized, which may occur at fs_initcall time.
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*/
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device_initcall(init_tsc_clocksource);
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2008-07-01 22:43:34 +04:00
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void __init tsc_init(void)
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{
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u64 lpj;
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int cpu;
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2009-08-19 17:37:03 +04:00
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x86_init.timers.tsc_pre_init();
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2008-07-01 22:43:34 +04:00
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if (!cpu_has_tsc)
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return;
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2009-08-20 19:06:25 +04:00
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tsc_khz = x86_platform.calibrate_tsc();
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2008-07-01 22:43:36 +04:00
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cpu_khz = tsc_khz;
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2008-07-01 22:43:34 +04:00
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2008-07-01 22:43:36 +04:00
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if (!tsc_khz) {
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2008-07-01 22:43:34 +04:00
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mark_tsc_unstable("could not calculate TSC khz");
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return;
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}
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printk("Detected %lu.%03lu MHz processor.\n",
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(unsigned long)cpu_khz / 1000,
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(unsigned long)cpu_khz % 1000);
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/*
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* Secondary CPUs do not run through tsc_init(), so set up
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* all the scale factors for all CPUs, assuming the same
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* speed as the bootup CPU. (cpufreq notifiers will fix this
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* up if their speed diverges)
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*/
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for_each_possible_cpu(cpu)
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set_cyc2ns_scale(cpu_khz, cpu);
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if (tsc_disabled > 0)
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return;
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/* now allow native_sched_clock() to use rdtsc */
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tsc_disabled = 0;
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2010-10-05 04:03:20 +04:00
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if (!no_sched_irq_time)
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enable_sched_clock_irqtime();
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2008-11-03 22:18:47 +03:00
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lpj = ((u64)tsc_khz * 1000);
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do_div(lpj, HZ);
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lpj_fine = lpj;
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|
2008-07-01 22:43:34 +04:00
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use_tsc_delay();
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if (unsynchronized_tsc())
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mark_tsc_unstable("TSCs unsynchronized");
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|
2008-10-25 04:22:01 +04:00
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check_system_tsc_reliable();
|
2008-07-01 22:43:34 +04:00
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}
|
|
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|
2011-11-16 03:33:56 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/*
|
|
|
|
* If we have a constant TSC and are using the TSC for the delay loop,
|
|
|
|
* we can skip clock calibration if another cpu in the same socket has already
|
|
|
|
* been calibrated. This assumes that CONSTANT_TSC applies to all
|
|
|
|
* cpus in the socket - this should be a safe assumption.
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|
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*/
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unsigned long __cpuinit calibrate_delay_is_known(void)
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|
|
{
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|
int i, cpu = smp_processor_id();
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|
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if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
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return 0;
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for_each_online_cpu(i)
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|
|
if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
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|
|
return cpu_data(i).loops_per_jiffy;
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|
|
return 0;
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|
}
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#endif
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