2019-05-27 09:55:01 +03:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
2005-04-17 02:20:36 +04:00
|
|
|
/*
|
|
|
|
* vDSO provided cache flush routines
|
|
|
|
*
|
|
|
|
* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
|
|
|
|
* IBM Corp.
|
|
|
|
*/
|
|
|
|
#include <asm/processor.h>
|
|
|
|
#include <asm/ppc_asm.h>
|
|
|
|
#include <asm/vdso.h>
|
2019-12-02 10:57:30 +03:00
|
|
|
#include <asm/vdso_datapage.h>
|
2005-09-09 22:57:26 +04:00
|
|
|
#include <asm/asm-offsets.h>
|
2019-12-02 10:57:31 +03:00
|
|
|
#include <asm/cache.h>
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
.text
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Default "generic" version of __kernel_sync_dicache.
|
|
|
|
*
|
|
|
|
* void __kernel_sync_dicache(unsigned long start, unsigned long end)
|
|
|
|
*
|
|
|
|
* Flushes the data cache & invalidate the instruction cache for the
|
|
|
|
* provided range [start, end[
|
|
|
|
*/
|
|
|
|
V_FUNCTION_BEGIN(__kernel_sync_dicache)
|
|
|
|
.cfi_startproc
|
2020-09-27 12:16:35 +03:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
b 3f
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
|
2019-12-02 10:57:31 +03:00
|
|
|
#ifdef CONFIG_PPC64
|
2007-11-20 04:24:45 +03:00
|
|
|
mflr r12
|
|
|
|
.cfi_register lr,r12
|
2020-09-27 12:16:32 +03:00
|
|
|
get_datapage r10
|
2007-11-20 04:24:45 +03:00
|
|
|
mtlr r12
|
2020-09-27 12:16:35 +03:00
|
|
|
.cfi_restore lr
|
2019-12-02 10:57:31 +03:00
|
|
|
#endif
|
2007-11-20 04:24:45 +03:00
|
|
|
|
2019-12-02 10:57:31 +03:00
|
|
|
#ifdef CONFIG_PPC64
|
2007-11-20 04:24:45 +03:00
|
|
|
lwz r7,CFG_DCACHE_BLOCKSZ(r10)
|
|
|
|
addi r5,r7,-1
|
2019-12-02 10:57:31 +03:00
|
|
|
#else
|
|
|
|
li r5, L1_CACHE_BYTES - 1
|
|
|
|
#endif
|
2019-12-02 10:57:30 +03:00
|
|
|
andc r6,r3,r5 /* round low to line bdy */
|
2005-04-17 02:20:36 +04:00
|
|
|
subf r8,r6,r4 /* compute length */
|
|
|
|
add r8,r8,r5 /* ensure we get enough */
|
2019-12-02 10:57:31 +03:00
|
|
|
#ifdef CONFIG_PPC64
|
2007-11-20 04:24:45 +03:00
|
|
|
lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
|
|
|
|
srw. r8,r8,r9 /* compute line count */
|
2019-12-02 10:57:31 +03:00
|
|
|
#else
|
|
|
|
srwi. r8, r8, L1_CACHE_SHIFT
|
|
|
|
mr r7, r6
|
|
|
|
#endif
|
2005-11-16 05:54:32 +03:00
|
|
|
crclr cr0*4+so
|
2005-04-17 02:20:36 +04:00
|
|
|
beqlr /* nothing to do? */
|
|
|
|
mtctr r8
|
2007-11-20 04:24:45 +03:00
|
|
|
1: dcbst 0,r6
|
2019-12-02 10:57:31 +03:00
|
|
|
#ifdef CONFIG_PPC64
|
2007-11-20 04:24:45 +03:00
|
|
|
add r6,r6,r7
|
2019-12-02 10:57:31 +03:00
|
|
|
#else
|
|
|
|
addi r6, r6, L1_CACHE_BYTES
|
|
|
|
#endif
|
2005-04-17 02:20:36 +04:00
|
|
|
bdnz 1b
|
|
|
|
sync
|
2007-11-20 04:24:45 +03:00
|
|
|
|
|
|
|
/* Now invalidate the instruction cache */
|
|
|
|
|
2019-12-02 10:57:31 +03:00
|
|
|
#ifdef CONFIG_PPC64
|
2007-11-20 04:24:45 +03:00
|
|
|
lwz r7,CFG_ICACHE_BLOCKSZ(r10)
|
|
|
|
addi r5,r7,-1
|
2019-12-02 10:57:30 +03:00
|
|
|
andc r6,r3,r5 /* round low to line bdy */
|
2007-11-20 04:24:45 +03:00
|
|
|
subf r8,r6,r4 /* compute length */
|
|
|
|
add r8,r8,r5
|
|
|
|
lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
|
|
|
|
srw. r8,r8,r9 /* compute line count */
|
|
|
|
crclr cr0*4+so
|
|
|
|
beqlr /* nothing to do? */
|
2019-12-02 10:57:31 +03:00
|
|
|
#endif
|
2005-04-17 02:20:36 +04:00
|
|
|
mtctr r8
|
2019-12-02 10:57:31 +03:00
|
|
|
#ifdef CONFIG_PPC64
|
2007-11-20 04:24:45 +03:00
|
|
|
2: icbi 0,r6
|
|
|
|
add r6,r6,r7
|
2019-12-02 10:57:31 +03:00
|
|
|
#else
|
|
|
|
2: icbi 0, r7
|
|
|
|
addi r7, r7, L1_CACHE_BYTES
|
|
|
|
#endif
|
2007-11-20 04:24:45 +03:00
|
|
|
bdnz 2b
|
2005-04-17 02:20:36 +04:00
|
|
|
isync
|
2005-04-28 05:04:45 +04:00
|
|
|
li r3,0
|
2005-04-17 02:20:36 +04:00
|
|
|
blr
|
2020-09-27 12:16:35 +03:00
|
|
|
3:
|
2005-11-16 05:54:32 +03:00
|
|
|
crclr cr0*4+so
|
2005-04-17 02:20:36 +04:00
|
|
|
sync
|
|
|
|
isync
|
2005-04-28 05:04:45 +04:00
|
|
|
li r3,0
|
2005-04-17 02:20:36 +04:00
|
|
|
blr
|
|
|
|
.cfi_endproc
|
2020-09-27 12:16:35 +03:00
|
|
|
V_FUNCTION_END(__kernel_sync_dicache)
|