iio: adc: Add support for STM32 ADC
This patch adds support for STMicroelectronics STM32 MCU's analog to digital converter. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Fabrice Gasnier
Jonathan Cameron
Родитель
1add698802
Коммит
0f883b223a
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@ -453,6 +453,16 @@ config STM32_ADC_CORE
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This driver can also be built as a module. If so, the module
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will be called stm32-adc-core.
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config STM32_ADC
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tristate "STMicroelectronics STM32 adc"
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depends on STM32_ADC_CORE
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help
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Say yes here to build support for STMicroelectronics stm32 Analog
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to Digital Converter (ADC).
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This driver can also be built as a module. If so, the module
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will be called stm32-adc.
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config STX104
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tristate "Apex Embedded Systems STX104 driver"
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depends on X86 && ISA_BUS_API
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@ -44,6 +44,7 @@ obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
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obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_STX104) += stx104.o
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obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
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obj-$(CONFIG_STM32_ADC) += stm32-adc.o
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obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
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obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
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obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
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@ -0,0 +1,518 @@
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/*
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* This file is part of STM32 ADC driver
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
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*
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* License type: GPLv2
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include "stm32-adc-core.h"
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/* STM32F4 - Registers for each ADC instance */
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#define STM32F4_ADC_SR 0x00
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#define STM32F4_ADC_CR1 0x04
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#define STM32F4_ADC_CR2 0x08
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#define STM32F4_ADC_SMPR1 0x0C
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#define STM32F4_ADC_SMPR2 0x10
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#define STM32F4_ADC_HTR 0x24
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#define STM32F4_ADC_LTR 0x28
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#define STM32F4_ADC_SQR1 0x2C
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#define STM32F4_ADC_SQR2 0x30
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#define STM32F4_ADC_SQR3 0x34
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#define STM32F4_ADC_JSQR 0x38
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#define STM32F4_ADC_JDR1 0x3C
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#define STM32F4_ADC_JDR2 0x40
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#define STM32F4_ADC_JDR3 0x44
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#define STM32F4_ADC_JDR4 0x48
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#define STM32F4_ADC_DR 0x4C
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/* STM32F4_ADC_SR - bit fields */
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#define STM32F4_STRT BIT(4)
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#define STM32F4_EOC BIT(1)
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/* STM32F4_ADC_CR1 - bit fields */
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#define STM32F4_SCAN BIT(8)
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#define STM32F4_EOCIE BIT(5)
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/* STM32F4_ADC_CR2 - bit fields */
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#define STM32F4_SWSTART BIT(30)
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#define STM32F4_EXTEN_MASK GENMASK(29, 28)
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#define STM32F4_EOCS BIT(10)
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#define STM32F4_ADON BIT(0)
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/* STM32F4_ADC_SQR1 - bit fields */
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#define STM32F4_L_SHIFT 20
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#define STM32F4_L_MASK GENMASK(23, 20)
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/* STM32F4_ADC_SQR3 - bit fields */
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#define STM32F4_SQ1_SHIFT 0
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#define STM32F4_SQ1_MASK GENMASK(4, 0)
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#define STM32_ADC_TIMEOUT_US 100000
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#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
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/**
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* struct stm32_adc - private data of each ADC IIO instance
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* @common: reference to ADC block common data
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* @offset: ADC instance register offset in ADC block
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* @completion: end of single conversion completion
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* @buffer: data buffer
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* @clk: clock for this adc instance
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* @irq: interrupt for this adc instance
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* @lock: spinlock
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*/
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struct stm32_adc {
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struct stm32_adc_common *common;
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u32 offset;
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struct completion completion;
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u16 *buffer;
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struct clk *clk;
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int irq;
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spinlock_t lock; /* interrupt lock */
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};
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/**
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* struct stm32_adc_chan_spec - specification of stm32 adc channel
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* @type: IIO channel type
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* @channel: channel number (single ended)
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* @name: channel name (single ended)
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*/
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struct stm32_adc_chan_spec {
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enum iio_chan_type type;
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int channel;
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const char *name;
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};
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/* Input definitions common for all STM32F4 instances */
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static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
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{ IIO_VOLTAGE, 0, "in0" },
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{ IIO_VOLTAGE, 1, "in1" },
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{ IIO_VOLTAGE, 2, "in2" },
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{ IIO_VOLTAGE, 3, "in3" },
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{ IIO_VOLTAGE, 4, "in4" },
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{ IIO_VOLTAGE, 5, "in5" },
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{ IIO_VOLTAGE, 6, "in6" },
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{ IIO_VOLTAGE, 7, "in7" },
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{ IIO_VOLTAGE, 8, "in8" },
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{ IIO_VOLTAGE, 9, "in9" },
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{ IIO_VOLTAGE, 10, "in10" },
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{ IIO_VOLTAGE, 11, "in11" },
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{ IIO_VOLTAGE, 12, "in12" },
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{ IIO_VOLTAGE, 13, "in13" },
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{ IIO_VOLTAGE, 14, "in14" },
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{ IIO_VOLTAGE, 15, "in15" },
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};
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/**
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* STM32 ADC registers access routines
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* @adc: stm32 adc instance
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* @reg: reg offset in adc instance
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*
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* Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
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* for adc1, adc2 and adc3.
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*/
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static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
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{
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return readl_relaxed(adc->common->base + adc->offset + reg);
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}
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static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
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{
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return readw_relaxed(adc->common->base + adc->offset + reg);
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}
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static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
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{
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writel_relaxed(val, adc->common->base + adc->offset + reg);
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}
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static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
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{
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unsigned long flags;
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spin_lock_irqsave(&adc->lock, flags);
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stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
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spin_unlock_irqrestore(&adc->lock, flags);
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}
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static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
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{
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unsigned long flags;
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spin_lock_irqsave(&adc->lock, flags);
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stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
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spin_unlock_irqrestore(&adc->lock, flags);
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}
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/**
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* stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
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* @adc: stm32 adc instance
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*/
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static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
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{
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stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
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};
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/**
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* stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
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* @adc: stm32 adc instance
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*/
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static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
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{
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
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}
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/**
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* stm32_adc_start_conv() - Start conversions for regular channels.
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* @adc: stm32 adc instance
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*/
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static void stm32_adc_start_conv(struct stm32_adc *adc)
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{
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stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
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stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
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/* Wait for Power-up time (tSTAB from datasheet) */
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usleep_range(2, 3);
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/* Software start ? (e.g. trigger detection disabled ?) */
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if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
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stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
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}
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static void stm32_adc_stop_conv(struct stm32_adc *adc)
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{
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
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stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_ADON);
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}
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/**
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* stm32_adc_single_conv() - Performs a single conversion
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* @indio_dev: IIO device
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* @chan: IIO channel
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* @res: conversion result
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*
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* The function performs a single conversion on a given channel:
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* - Program sequencer with one channel (e.g. in SQ1 with len = 1)
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* - Use SW trigger
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* - Start conversion, then wait for interrupt completion.
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*/
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static int stm32_adc_single_conv(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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int *res)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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long timeout;
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u32 val;
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u16 result;
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int ret;
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reinit_completion(&adc->completion);
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adc->buffer = &result;
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/* Program chan number in regular sequence */
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val = stm32_adc_readl(adc, STM32F4_ADC_SQR3);
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val &= ~STM32F4_SQ1_MASK;
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val |= chan->channel << STM32F4_SQ1_SHIFT;
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stm32_adc_writel(adc, STM32F4_ADC_SQR3, val);
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/* Set regular sequence len (0 for 1 conversion) */
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stm32_adc_clr_bits(adc, STM32F4_ADC_SQR1, STM32F4_L_MASK);
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/* Trigger detection disabled (conversion can be launched in SW) */
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
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stm32_adc_conv_irq_enable(adc);
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stm32_adc_start_conv(adc);
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timeout = wait_for_completion_interruptible_timeout(
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&adc->completion, STM32_ADC_TIMEOUT);
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if (timeout == 0) {
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ret = -ETIMEDOUT;
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} else if (timeout < 0) {
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ret = timeout;
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} else {
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*res = result;
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ret = IIO_VAL_INT;
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}
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stm32_adc_stop_conv(adc);
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stm32_adc_conv_irq_disable(adc);
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return ret;
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}
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static int stm32_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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return ret;
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if (chan->type == IIO_VOLTAGE)
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ret = stm32_adc_single_conv(indio_dev, chan, val);
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else
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ret = -EINVAL;
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iio_device_release_direct_mode(indio_dev);
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return ret;
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case IIO_CHAN_INFO_SCALE:
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*val = adc->common->vref_mv;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static irqreturn_t stm32_adc_isr(int irq, void *data)
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{
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struct stm32_adc *adc = data;
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u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR);
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if (status & STM32F4_EOC) {
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*adc->buffer = stm32_adc_readw(adc, STM32F4_ADC_DR);
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complete(&adc->completion);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
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const struct of_phandle_args *iiospec)
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{
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int i;
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for (i = 0; i < indio_dev->num_channels; i++)
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if (indio_dev->channels[i].channel == iiospec->args[0])
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return i;
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return -EINVAL;
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}
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/**
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* stm32_adc_debugfs_reg_access - read or write register value
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*
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* To read a value from an ADC register:
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* echo [ADC reg offset] > direct_reg_access
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* cat direct_reg_access
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*
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* To write a value in a ADC register:
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* echo [ADC_reg_offset] [value] > direct_reg_access
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*/
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static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
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unsigned reg, unsigned writeval,
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unsigned *readval)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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if (!readval)
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stm32_adc_writel(adc, reg, writeval);
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else
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*readval = stm32_adc_readl(adc, reg);
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return 0;
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}
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static const struct iio_info stm32_adc_iio_info = {
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.read_raw = stm32_adc_read_raw,
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.debugfs_reg_access = stm32_adc_debugfs_reg_access,
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.of_xlate = stm32_adc_of_xlate,
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.driver_module = THIS_MODULE,
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};
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static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
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struct iio_chan_spec *chan,
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const struct stm32_adc_chan_spec *channel,
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int scan_index)
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{
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chan->type = channel->type;
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chan->channel = channel->channel;
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chan->datasheet_name = channel->name;
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chan->scan_index = scan_index;
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chan->indexed = 1;
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chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
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chan->scan_type.sign = 'u';
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chan->scan_type.realbits = 12;
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chan->scan_type.storagebits = 16;
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}
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static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
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{
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struct device_node *node = indio_dev->dev.of_node;
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struct property *prop;
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const __be32 *cur;
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struct iio_chan_spec *channels;
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int scan_index = 0, num_channels;
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u32 val;
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num_channels = of_property_count_u32_elems(node, "st,adc-channels");
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if (num_channels < 0 ||
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num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
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dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
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return num_channels < 0 ? num_channels : -EINVAL;
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}
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channels = devm_kcalloc(&indio_dev->dev, num_channels,
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sizeof(struct iio_chan_spec), GFP_KERNEL);
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if (!channels)
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return -ENOMEM;
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of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
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if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
|
||||
dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
|
||||
return -EINVAL;
|
||||
}
|
||||
stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
|
||||
&stm32f4_adc123_channels[val],
|
||||
scan_index);
|
||||
scan_index++;
|
||||
}
|
||||
|
||||
indio_dev->num_channels = scan_index;
|
||||
indio_dev->channels = channels;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_adc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct iio_dev *indio_dev;
|
||||
struct stm32_adc *adc;
|
||||
int ret;
|
||||
|
||||
if (!pdev->dev.of_node)
|
||||
return -ENODEV;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
|
||||
if (!indio_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
adc = iio_priv(indio_dev);
|
||||
adc->common = dev_get_drvdata(pdev->dev.parent);
|
||||
spin_lock_init(&adc->lock);
|
||||
init_completion(&adc->completion);
|
||||
|
||||
indio_dev->name = dev_name(&pdev->dev);
|
||||
indio_dev->dev.parent = &pdev->dev;
|
||||
indio_dev->dev.of_node = pdev->dev.of_node;
|
||||
indio_dev->info = &stm32_adc_iio_info;
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
|
||||
platform_set_drvdata(pdev, adc);
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "missing reg property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
adc->irq = platform_get_irq(pdev, 0);
|
||||
if (adc->irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get irq\n");
|
||||
return adc->irq;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
|
||||
0, pdev->name, adc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
adc->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(adc->clk)) {
|
||||
dev_err(&pdev->dev, "Can't get clock\n");
|
||||
return PTR_ERR(adc->clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(adc->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "clk enable failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = stm32_adc_chan_of_init(indio_dev);
|
||||
if (ret < 0)
|
||||
goto err_clk_disable;
|
||||
|
||||
ret = iio_device_register(indio_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "iio dev register failed\n");
|
||||
goto err_clk_disable;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_disable:
|
||||
clk_disable_unprepare(adc->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_adc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_adc *adc = platform_get_drvdata(pdev);
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
|
||||
iio_device_unregister(indio_dev);
|
||||
clk_disable_unprepare(adc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id stm32_adc_of_match[] = {
|
||||
{ .compatible = "st,stm32f4-adc" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
|
||||
|
||||
static struct platform_driver stm32_adc_driver = {
|
||||
.probe = stm32_adc_probe,
|
||||
.remove = stm32_adc_remove,
|
||||
.driver = {
|
||||
.name = "stm32-adc",
|
||||
.of_match_table = stm32_adc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(stm32_adc_driver);
|
||||
|
||||
MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
|
||||
MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:stm32-adc");
|
||||
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