i7core_edac: Add error insertion code for Nehalem
Implements set_inject_error() with the low-level code needed to inject memory errors at Nehalem, and adds some sysfs nodes to allow error injection The next patch will add an API for error injection. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
Родитель
a0c36a1f0f
Коммит
194a40feab
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@ -20,7 +20,6 @@
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* http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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@ -64,12 +63,16 @@
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/* OFFSETS for Devices 4,5 and 6 Function 0 */
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#define MC_CHANNEL_ADDR_MATCH 0xf0
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#define MC_MASK_DIMM (1 << 41)
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#define MC_MASK_RANK (1 << 40)
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#define MC_MASK_BANK (1 << 39)
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#define MC_MASK_PAGE (1 << 38)
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#define MC_MASK_COL (1 << 37)
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#define MC_CHANNEL_ERROR_MASK 0xf8
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#define MC_CHANNEL_ERROR_INJECT 0xfc
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#define INJECT_ADDR_PARITY 0x10
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#define INJECT_ECC 0x08
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#define MASK_CACHELINE 0x06
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#define MASK_FULL_CACHELINE 0x06
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#define MASK_MSB32_CACHELINE 0x04
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#define MASK_LSB32_CACHELINE 0x02
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#define NO_MASK_CACHELINE 0x00
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#define REPEAT_EN 0x01
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/*
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* i7core structs
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@ -84,10 +87,23 @@ struct i7core_info {
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u32 max_dod;
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};
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struct i7core_inject {
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int enable;
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u32 section;
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u32 type;
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u32 eccmask;
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/* Error address mask */
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int channel, dimm, rank, bank, page, col;
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};
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struct i7core_pvt {
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struct pci_dev *pci_mcr; /* Dev 3:0 */
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struct pci_dev *pci_ch[NUM_CHANS][NUM_FUNCS];
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struct i7core_info info;
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struct i7core_inject inject;
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};
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/* Device name and register DID (Device ID) */
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@ -166,6 +182,7 @@ static inline int maxnumcol(struct i7core_pvt *pvt)
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return cols[((pvt->info.max_dod >> 9) & 0x3) << 12];
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}
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/****************************************************************************
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Memory check routines
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****************************************************************************/
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@ -199,6 +216,390 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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return 0;
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}
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/****************************************************************************
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Error insertion routines
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****************************************************************************/
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/* The i7core has independent error injection features per channel.
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However, to have a simpler code, we don't allow enabling error injection
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on more than one channel.
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Also, since a change at an inject parameter will be applied only at enable,
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we're disabling error injection on all write calls to the sysfs nodes that
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controls the error code injection.
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*/
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static void disable_inject(struct mem_ctl_info *mci)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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pvt->inject.enable = 0;
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, 0);
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}
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/*
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* i7core inject inject.section
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*
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* accept and store error injection inject.section value
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* bit 0 - refers to the lower 32-byte half cacheline
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* bit 1 - refers to the upper 32-byte half cacheline
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*/
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static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int rc;
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if (pvt->inject.enable)
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disable_inject(mci);
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rc = strict_strtoul(data, 10, &value);
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if ((rc < 0) || (value > 3))
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return 0;
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pvt->inject.section = (u32) value;
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return count;
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}
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static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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return sprintf(data, "0x%08x\n", pvt->inject.section);
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}
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/*
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* i7core inject.type
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*
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* accept and store error injection inject.section value
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* bit 0 - repeat enable - Enable error repetition
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* bit 1 - inject ECC error
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* bit 2 - inject parity error
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*/
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static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int rc;
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if (pvt->inject.enable)
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disable_inject(mci);
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rc = strict_strtoul(data, 10, &value);
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if ((rc < 0) || (value > 7))
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return 0;
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pvt->inject.type = (u32) value;
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return count;
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}
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static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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return sprintf(data, "0x%08x\n", pvt->inject.type);
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}
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/*
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* i7core_inject_inject.eccmask_store
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*
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* The type of error (UE/CE) will depend on the inject.eccmask value:
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* Any bits set to a 1 will flip the corresponding ECC bit
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* Correctable errors can be injected by flipping 1 bit or the bits within
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* a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
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* 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
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* uncorrectable error to be injected.
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*/
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static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int rc;
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if (pvt->inject.enable)
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disable_inject(mci);
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rc = strict_strtoul(data, 10, &value);
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if (rc < 0)
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return 0;
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pvt->inject.eccmask = (u32) value;
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return count;
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}
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static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
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}
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/*
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* i7core_addrmatch
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*
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* The type of error (UE/CE) will depend on the inject.eccmask value:
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* Any bits set to a 1 will flip the corresponding ECC bit
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* Correctable errors can be injected by flipping 1 bit or the bits within
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* a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
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* 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
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* uncorrectable error to be injected.
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*/
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static ssize_t i7core_inject_addrmatch_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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char *cmd, *val;
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long value;
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int rc;
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if (pvt->inject.enable)
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disable_inject(mci);
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do {
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cmd = strsep((char **) &data, ":");
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if (!cmd)
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break;
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val = strsep((char **) &data, " \n\t");
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if (!val)
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return cmd - data;
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if (!strcasecmp(val,"any"))
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value = -1;
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else {
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rc = strict_strtol(val, 10, &value);
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if ((rc < 0) || (value < 0))
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return cmd - data;
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}
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if (!strcasecmp(cmd,"channel")) {
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if (value < 3)
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pvt->inject.channel = value;
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else
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return cmd - data;
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} else if (!strcasecmp(cmd,"dimm")) {
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if (value < 4)
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pvt->inject.dimm = value;
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else
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return cmd - data;
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} else if (!strcasecmp(cmd,"rank")) {
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if (value < 4)
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pvt->inject.rank = value;
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else
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return cmd - data;
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} else if (!strcasecmp(cmd,"bank")) {
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if (value < 4)
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pvt->inject.bank = value;
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else
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return cmd - data;
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} else if (!strcasecmp(cmd,"page")) {
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if (value <= 0xffff)
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pvt->inject.page = value;
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else
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return cmd - data;
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} else if (!strcasecmp(cmd,"col") ||
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!strcasecmp(cmd,"column")) {
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if (value <= 0x3fff)
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pvt->inject.col = value;
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else
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return cmd - data;
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}
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} while (1);
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return count;
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}
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static ssize_t i7core_inject_addrmatch_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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char channel[4], dimm[4], bank[4], rank[4], page[7], col[7];
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if (pvt->inject.channel < 0)
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sprintf(channel, "any");
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else
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sprintf(channel, "%d", pvt->inject.channel);
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if (pvt->inject.dimm < 0)
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sprintf(dimm, "any");
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else
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sprintf(dimm, "%d", pvt->inject.dimm);
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if (pvt->inject.bank < 0)
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sprintf(bank, "any");
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else
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sprintf(bank, "%d", pvt->inject.bank);
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if (pvt->inject.rank < 0)
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sprintf(rank, "any");
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else
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sprintf(rank, "%d", pvt->inject.rank);
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if (pvt->inject.page < 0)
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sprintf(page, "any");
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else
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sprintf(page, "0x%04x", pvt->inject.page);
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if (pvt->inject.col < 0)
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sprintf(col, "any");
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else
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sprintf(col, "0x%04x", pvt->inject.col);
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return sprintf(data, "channel: %s\ndimm: %s\nbank: %s\n"
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"rank: %s\npage: %s\ncolumn: %s\n",
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channel, dimm, bank, rank, page, col);
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}
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/*
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* This routine prepares the Memory Controller for error injection.
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* The error will be injected when some process tries to write to the
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* memory that matches the given criteria.
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* The criteria can be set in terms of a mask where dimm, rank, bank, page
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* and col can be specified.
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* A -1 value for any of the mask items will make the MCU to ignore
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* that matching criteria for error injection.
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*
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* It should be noticed that the error will only happen after a write operation
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* on a memory that matches the condition. if REPEAT_EN is not enabled at
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* inject mask, then it will produce just one error. Otherwise, it will repeat
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* until the injectmask would be cleaned.
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*
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* FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
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* is reliable enough to check if the MC is using the
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* three channels. However, this is not clear at the datasheet.
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*/
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static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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u32 injectmask;
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u64 mask = 0;
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int rc;
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long enable;
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rc = strict_strtoul(data, 10, &enable);
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if ((rc < 0))
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return 0;
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if (enable) {
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pvt->inject.enable = 1;
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} else {
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disable_inject(mci);
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return count;
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}
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/* Sets pvt->inject.dimm mask */
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if (pvt->inject.dimm < 0)
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mask |= 1l << 41;
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else {
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if (maxnumdimms(pvt) > 2)
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mask |= (pvt->inject.dimm & 0x3l) << 35;
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else
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mask |= (pvt->inject.dimm & 0x1l) << 36;
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}
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/* Sets pvt->inject.rank mask */
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if (pvt->inject.rank < 0)
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mask |= 1l << 40;
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else {
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if (maxnumdimms(pvt) > 2)
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mask |= (pvt->inject.rank & 0x1l) << 34;
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else
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mask |= (pvt->inject.rank & 0x3l) << 34;
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}
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/* Sets pvt->inject.bank mask */
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if (pvt->inject.bank < 0)
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mask |= 1l << 39;
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else
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mask |= (pvt->inject.bank & 0x15l) << 30;
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/* Sets pvt->inject.page mask */
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if (pvt->inject.page < 0)
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mask |= 1l << 38;
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else
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mask |= (pvt->inject.page & 0xffffl) << 14;
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/* Sets pvt->inject.column mask */
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if (pvt->inject.col < 0)
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mask |= 1l << 37;
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else
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mask |= (pvt->inject.col & 0x3fffl);
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pci_write_config_qword(pvt->pci_ch[pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH, mask);
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
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/*
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* bit 0: REPEAT_EN
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* bits 1-2: MASK_HALF_CACHELINE
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* bit 3: INJECT_ECC
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* bit 4: INJECT_ADDR_PARITY
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*/
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injectmask = (pvt->inject.type & 1) &&
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(pvt->inject.section & 0x3) << 1 &&
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(pvt->inject.type & 0x6) << (3 - 1);
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, injectmask);
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debugf0("Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
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mask, pvt->inject.eccmask, injectmask);
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return count;
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}
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static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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return sprintf(data, "%d\n", pvt->inject.enable);
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}
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/*
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* Sysfs struct
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*/
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static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
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{
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.attr = {
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.name = "inject_section",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_inject_section_show,
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.store = i7core_inject_section_store,
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}, {
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.attr = {
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.name = "inject_type",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_inject_type_show,
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.store = i7core_inject_type_store,
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}, {
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.attr = {
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.name = "inject_eccmask",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_inject_eccmask_show,
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.store = i7core_inject_eccmask_store,
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}, {
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.attr = {
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.name = "inject_addrmatch",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_inject_addrmatch_show,
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.store = i7core_inject_addrmatch_store,
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}, {
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.attr = {
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.name = "inject_enable",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_inject_enable_show,
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.store = i7core_inject_enable_store,
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},
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};
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/****************************************************************************
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Device initialization routines: put/get, init/exit
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****************************************************************************/
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|
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@ -322,10 +723,11 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
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mci->dev = &pdev->dev; /* record ptr to the generic device */
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mci->dev = &pdev->dev; /* record ptr to the generic device */
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dev_set_drvdata(mci->dev, mci);
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pvt = mci->pvt_info;
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// pvt->system_address = pdev; /* Record this device in our private */
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// pvt->maxch = num_channels;
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// pvt->maxdimmperch = num_dimms_per_channel;
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|
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@ -343,6 +745,7 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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mci->ctl_name = i7core_devs[dev_idx].ctl_name;
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mci->dev_name = pci_name(pdev);
|
||||
mci->ctl_page_to_phys = NULL;
|
||||
mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
|
||||
|
||||
/* add this new MC control structure to EDAC's list of MCs */
|
||||
if (edac_mc_add_mc(mci)) {
|
||||
|
|
@ -365,6 +768,14 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
|
|||
__func__);
|
||||
}
|
||||
|
||||
/* Default error mask is any memory */
|
||||
pvt->inject.channel = -1;
|
||||
pvt->inject.dimm = -1;
|
||||
pvt->inject.rank = -1;
|
||||
pvt->inject.bank = -1;
|
||||
pvt->inject.page = -1;
|
||||
pvt->inject.col = -1;
|
||||
|
||||
return 0;
|
||||
|
||||
fail1:
|
||||
|
|
|
|||
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