Merge branch 'socfpga/hw' into next/soc
From Dinh Nguyen, this is a series of patches introducing support for socfpga hardware (Altera Cyclone5). It also includes a cleanup that moves some of the ARMv7 cache maintenance functions to a common location, since three other platforms aready implemented it separately. * socfpga/hw: arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW Trivial conflict in arch/arm/mach-tegra/headsmp.S. Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
1c75c42100
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@ -3,9 +3,11 @@ Altera SOCFPGA System Manager
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Required properties:
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- compatible : "altr,sys-mgr"
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- reg : Should contain 1 register ranges(address and length)
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- cpu1-start-addr : CPU1 start address in hex.
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Example:
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sysmgr@ffd08000 {
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compatible = "altr,sys-mgr";
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reg = <0xffd08000 0x1000>;
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cpu1-start-addr = <0xffd080c4>;
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};
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@ -125,6 +125,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
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r8a7740-armadillo800eva.dtb \
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sh73a0-kzm9g.dtb \
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sh7372-mackerel.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
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socfpga_vt.dtb
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dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
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spear1340-evb.dtb
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dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
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@ -25,6 +25,10 @@
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ethernet0 = &gmac0;
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serial0 = &uart0;
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serial1 = &uart1;
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timer0 = &timer0;
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timer1 = &timer1;
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timer2 = &timer2;
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timer3 = &timer3;
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};
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cpus {
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@ -98,47 +102,41 @@
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interrupts = <1 13 0xf04>;
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};
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timer0: timer@ffc08000 {
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timer0: timer0@ffc08000 {
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compatible = "snps,dw-apb-timer-sp";
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interrupts = <0 167 4>;
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clock-frequency = <200000000>;
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reg = <0xffc08000 0x1000>;
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};
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timer1: timer@ffc09000 {
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timer1: timer1@ffc09000 {
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compatible = "snps,dw-apb-timer-sp";
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interrupts = <0 168 4>;
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clock-frequency = <200000000>;
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reg = <0xffc09000 0x1000>;
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};
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timer2: timer@ffd00000 {
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timer2: timer2@ffd00000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 169 4>;
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clock-frequency = <200000000>;
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reg = <0xffd00000 0x1000>;
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};
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timer3: timer@ffd01000 {
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timer3: timer3@ffd01000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 170 4>;
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clock-frequency = <200000000>;
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reg = <0xffd01000 0x1000>;
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};
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uart0: uart@ffc02000 {
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uart0: serial0@ffc02000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02000 0x1000>;
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clock-frequency = <7372800>;
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interrupts = <0 162 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart1: uart@ffc03000 {
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uart1: serial1@ffc03000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc03000 0x1000>;
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clock-frequency = <7372800>;
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interrupts = <0 163 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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@ -20,7 +20,7 @@
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/ {
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model = "Altera SOCFPGA Cyclone V";
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compatible = "altr,socfpga-cyclone5";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,57600";
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@ -29,6 +29,36 @@
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x10000000>; /* 256MB */
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <100000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <25000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <25000000>;
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};
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serial0@ffc02000 {
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clock-frequency = <100000000>;
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};
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serial1@ffc03000 {
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clock-frequency = <100000000>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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/ {
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model = "Altera SOCFPGA VT";
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compatible = "altr,socfpga-vt", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1 GB */
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};
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soc {
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timer0@ffc08000 {
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clock-frequency = <7000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <7000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <7000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <7000000>;
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};
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serial0@ffc02000 {
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clock-frequency = <7372800>;
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};
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serial1@ffc03000 {
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clock-frequency = <7372800>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd08010>;
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};
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};
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};
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@ -17,53 +17,6 @@
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.section ".text.head", "ax"
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/*
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*
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* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
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* to be called for both secondary cores startup and primary core resume
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* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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#ifdef CONFIG_SMP
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ENTRY(v7_secondary_startup)
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bl v7_invalidate_l1
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@ -16,54 +16,6 @@
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__CPUINIT
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/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
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*
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*
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* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
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* to be called for both secondary cores startup and primary core resume
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* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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ENTRY(shmobile_invalidate_start)
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bl v7_invalidate_l1
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b secondary_startup
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@ -20,7 +20,7 @@
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#ifndef __MACH_CORE_H
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#define __MACH_CORE_H
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extern void secondary_startup(void);
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extern void socfpga_secondary_startup(void);
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extern void __iomem *socfpga_scu_base_addr;
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extern void socfpga_init_clocks(void);
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@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void);
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extern struct smp_operations socfpga_smp_ops;
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extern char secondary_trampoline, secondary_trampoline_end;
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extern unsigned long cpu1start_addr;
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#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
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#endif
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|
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@ -13,13 +13,21 @@
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__CPUINIT
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.arch armv7-a
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#define CPU1_START_ADDR 0xffd08010
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ENTRY(secondary_trampoline)
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movw r0, #:lower16:CPU1_START_ADDR
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movt r0, #:upper16:CPU1_START_ADDR
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movw r2, #:lower16:cpu1start_addr
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movt r2, #:upper16:cpu1start_addr
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/* The socfpga VT cannot handle a 0xC0000000 page offset when loading
|
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the cpu1start_addr, we bit clear it. Tested on HW and VT. */
|
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bic r2, r2, #0x40000000
|
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|
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ldr r0, [r2]
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ldr r1, [r0]
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bx r1
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|
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ENTRY(secondary_trampoline_end)
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||||
|
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ENTRY(socfpga_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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||||
ENDPROC(socfpga_secondary_startup)
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|
|
|
|||
|
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@ -47,16 +47,19 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
|
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{
|
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int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
|
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|
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memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
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if (cpu1start_addr) {
|
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memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
|
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|
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__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
|
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__raw_writel(virt_to_phys(socfpga_secondary_startup),
|
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(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
|
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|
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flush_cache_all();
|
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smp_wmb();
|
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outer_clean_range(0, trampoline_size);
|
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flush_cache_all();
|
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smp_wmb();
|
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outer_clean_range(0, trampoline_size);
|
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|
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/* This will release CPU #1 out of reset.*/
|
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__raw_writel(0, rst_manager_base_addr + 0x10);
|
||||
/* This will release CPU #1 out of reset.*/
|
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__raw_writel(0, rst_manager_base_addr + 0x10);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
|
||||
void __iomem *sys_manager_base_addr;
|
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void __iomem *rst_manager_base_addr;
|
||||
unsigned long cpu1start_addr;
|
||||
|
||||
static struct map_desc scu_io_desc __initdata = {
|
||||
.virtual = SOCFPGA_SCU_VIRT_BASE,
|
||||
|
|
@ -67,6 +68,11 @@ void __init socfpga_sysmgr_init(void)
|
|||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
|
||||
|
||||
if (of_property_read_u32(np, "cpu1-start-addr",
|
||||
(u32 *) &cpu1start_addr))
|
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pr_err("SMP: Need cpu1-start-addr in device tree.\n");
|
||||
|
||||
sys_manager_base_addr = of_iomap(np, 0);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
|
||||
|
|
@ -93,7 +99,6 @@ static void __init socfpga_cyclone5_init(void)
|
|||
|
||||
static const char *altera_dt_match[] = {
|
||||
"altr,socfpga",
|
||||
"altr,socfpga-cyclone5",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -5,49 +5,6 @@
|
|||
|
||||
.section ".text.head", "ax"
|
||||
|
||||
/*
|
||||
* Tegra specific entry point for secondary CPUs.
|
||||
* The secondary kernel init calls v7_flush_dcache_all before it enables
|
||||
* the L1; however, the L1 comes out of reset in an undefined state, so
|
||||
* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
|
||||
* of cache lines with uninitialized data and uninitialized tags to get
|
||||
* written out to memory, which does really unpleasant things to the main
|
||||
* processor. We fix this by performing an invalidate, rather than a
|
||||
* clean + invalidate, before jumping into the kernel.
|
||||
*/
|
||||
ENTRY(v7_invalidate_l1)
|
||||
mov r0, #0
|
||||
mcr p15, 2, r0, c0, c0, 0
|
||||
mrc p15, 1, r0, c0, c0, 0
|
||||
|
||||
ldr r1, =0x7fff
|
||||
and r2, r1, r0, lsr #13
|
||||
|
||||
ldr r1, =0x3ff
|
||||
|
||||
and r3, r1, r0, lsr #3 @ NumWays - 1
|
||||
add r2, r2, #1 @ NumSets
|
||||
|
||||
and r0, r0, #0x7
|
||||
add r0, r0, #4 @ SetShift
|
||||
|
||||
clz r1, r3 @ WayShift
|
||||
add r4, r3, #1 @ NumWays
|
||||
1: sub r2, r2, #1 @ NumSets--
|
||||
mov r3, r4 @ Temp = NumWays
|
||||
2: subs r3, r3, #1 @ Temp--
|
||||
mov r5, r3, lsl r1
|
||||
mov r6, r2, lsl r0
|
||||
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
|
||||
mcr p15, 0, r5, c7, c6, 2
|
||||
bgt 2b
|
||||
cmp r2, #0
|
||||
bgt 1b
|
||||
dsb
|
||||
isb
|
||||
mov pc, lr
|
||||
ENDPROC(v7_invalidate_l1)
|
||||
|
||||
ENTRY(tegra_secondary_startup)
|
||||
bl v7_invalidate_l1
|
||||
/* Enable coresight */
|
||||
|
|
|
|||
|
|
@ -18,6 +18,52 @@
|
|||
|
||||
#include "proc-macros.S"
|
||||
|
||||
/*
|
||||
* The secondary kernel init calls v7_flush_dcache_all before it enables
|
||||
* the L1; however, the L1 comes out of reset in an undefined state, so
|
||||
* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
|
||||
* of cache lines with uninitialized data and uninitialized tags to get
|
||||
* written out to memory, which does really unpleasant things to the main
|
||||
* processor. We fix this by performing an invalidate, rather than a
|
||||
* clean + invalidate, before jumping into the kernel.
|
||||
*
|
||||
* This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
|
||||
* to be called for both secondary cores startup and primary core resume
|
||||
* procedures.
|
||||
*/
|
||||
ENTRY(v7_invalidate_l1)
|
||||
mov r0, #0
|
||||
mcr p15, 2, r0, c0, c0, 0
|
||||
mrc p15, 1, r0, c0, c0, 0
|
||||
|
||||
ldr r1, =0x7fff
|
||||
and r2, r1, r0, lsr #13
|
||||
|
||||
ldr r1, =0x3ff
|
||||
|
||||
and r3, r1, r0, lsr #3 @ NumWays - 1
|
||||
add r2, r2, #1 @ NumSets
|
||||
|
||||
and r0, r0, #0x7
|
||||
add r0, r0, #4 @ SetShift
|
||||
|
||||
clz r1, r3 @ WayShift
|
||||
add r4, r3, #1 @ NumWays
|
||||
1: sub r2, r2, #1 @ NumSets--
|
||||
mov r3, r4 @ Temp = NumWays
|
||||
2: subs r3, r3, #1 @ Temp--
|
||||
mov r5, r3, lsl r1
|
||||
mov r6, r2, lsl r0
|
||||
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
|
||||
mcr p15, 0, r5, c7, c6, 2
|
||||
bgt 2b
|
||||
cmp r2, #0
|
||||
bgt 1b
|
||||
dsb
|
||||
isb
|
||||
mov pc, lr
|
||||
ENDPROC(v7_invalidate_l1)
|
||||
|
||||
/*
|
||||
* v7_flush_icache_all()
|
||||
*
|
||||
|
|
|
|||
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