clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler clocks. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
Родитель
453e519e5a
Коммит
2a2f33e83d
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@ -545,6 +545,12 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
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GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
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ENABLE_ACLK_TOP, 18,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
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ENABLE_ACLK_TOP, 15,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
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ENABLE_ACLK_TOP, 14,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
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ENABLE_ACLK_TOP, 2,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -3247,3 +3253,143 @@ static void __init exynos5433_cmu_g3d_init(struct device_node *np)
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}
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CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
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exynos5433_cmu_g3d_init);
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/*
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* Register offset definitions for CMU_GSCL
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*/
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#define MUX_SEL_GSCL 0x0200
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#define MUX_ENABLE_GSCL 0x0300
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#define MUX_STAT_GSCL 0x0400
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#define ENABLE_ACLK_GSCL 0x0800
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#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
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#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
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#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
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#define ENABLE_PCLK_GSCL 0x0900
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#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
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#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
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#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
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#define ENABLE_IP_GSCL0 0x0b00
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#define ENABLE_IP_GSCL1 0x0b04
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#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
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#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
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#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
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static unsigned long gscl_clk_regs[] __initdata = {
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MUX_SEL_GSCL,
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MUX_ENABLE_GSCL,
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MUX_STAT_GSCL,
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ENABLE_ACLK_GSCL,
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
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ENABLE_PCLK_GSCL,
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
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ENABLE_IP_GSCL0,
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ENABLE_IP_GSCL1,
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ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
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ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
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ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
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};
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/* list of all parent clock list */
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PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
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PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
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static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
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/* MUX_SEL_GSCL */
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MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
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aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
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MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
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aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
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};
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static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
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/* ENABLE_ACLK_GSCL */
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GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 11, 0, 0),
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GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 10, 0, 0),
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GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 9, 0, 0),
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GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
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"mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
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8, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 7, 0, 0),
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GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
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ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
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"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
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GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
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"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
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GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 3, 0, 0),
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GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 2, 0, 0),
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GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 1, 0, 0),
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GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL, 0, 0, 0),
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/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
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GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
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/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
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GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
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/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
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GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
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ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
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/* ENABLE_PCLK_GSCL */
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GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 7, 0, 0),
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GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 6, 0, 0),
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GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 5, 0, 0),
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GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
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"mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
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3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 2, 0, 0),
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GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 1, 0, 0),
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GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL, 0, 0, 0),
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/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
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GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
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/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
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GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
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/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
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GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
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};
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static struct samsung_cmu_info gscl_cmu_info __initdata = {
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.mux_clks = gscl_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
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.gate_clks = gscl_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
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.nr_clk_ids = GSCL_NR_CLK,
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.clk_regs = gscl_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
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};
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static void __init exynos5433_cmu_gscl_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &gscl_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
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exynos5433_cmu_gscl_init);
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@ -147,8 +147,10 @@
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#define CLK_SCLK_UFSUNIPRO_FSYS 229
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#define CLK_SCLK_USBHOST30_FSYS 230
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#define CLK_SCLK_USBDRD30_FSYS 231
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#define CLK_ACLK_GSCL_111 232
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#define CLK_ACLK_GSCL_333 233
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#define TOP_NR_CLK 232
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#define TOP_NR_CLK 234
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/* CMU_CPIF */
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#define CLK_FOUT_MPHY_PLL 1
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@ -819,4 +821,37 @@
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#define G3D_NR_CLK 20
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/* CMU_GSCL */
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#define CLK_MOUT_ACLK_GSCL_111_USER 1
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#define CLK_MOUT_ACLK_GSCL_333_USER 2
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#define CLK_ACLK_BTS_GSCL2 3
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#define CLK_ACLK_BTS_GSCL1 4
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#define CLK_ACLK_BTS_GSCL0 5
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#define CLK_ACLK_AHB2APB_GSCLP 6
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#define CLK_ACLK_XIU_GSCLX 7
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#define CLK_ACLK_GSCLNP_111 8
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#define CLK_ACLK_GSCLRTND_333 9
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#define CLK_ACLK_GSCLBEND_333 10
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#define CLK_ACLK_GSD 11
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#define CLK_ACLK_GSCL2 12
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#define CLK_ACLK_GSCL1 13
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#define CLK_ACLK_GSCL0 14
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#define CLK_ACLK_SMMU_GSCL0 15
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#define CLK_ACLK_SMMU_GSCL1 16
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#define CLK_ACLK_SMMU_GSCL2 17
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#define CLK_PCLK_BTS_GSCL2 18
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#define CLK_PCLK_BTS_GSCL1 19
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#define CLK_PCLK_BTS_GSCL0 20
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#define CLK_PCLK_PMU_GSCL 21
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#define CLK_PCLK_SYSREG_GSCL 22
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#define CLK_PCLK_GSCL2 23
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#define CLK_PCLK_GSCL1 24
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#define CLK_PCLK_GSCL0 25
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#define CLK_PCLK_SMMU_GSCL0 26
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#define CLK_PCLK_SMMU_GSCL1 27
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#define CLK_PCLK_SMMU_GSCL2 28
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#define GSCL_NR_CLK 29
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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