pwm: Changes for v3.17-rc1
The set of changes for this merge window contains two new drivers: one for Rockchip SoCs and another for STMicroelectronics STiH4xx SoCs. The remainder of the changes are the usual small cleanups such as removing redundant OOM messages, signalling that a PWM chip's operations can sleep and removing an unneeded dependency. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJT5LH8AAoJEN0jrNd/PrOhm1gQAKZUW7ueTT5Ar9cwBvWwtHSr qLtTx0GxJ91cH6h2bNkhBLz3A2ps9KPcxWgDxfod4TyOHsqZmbAwVHZzORyxr3Hi n5iQST0SpH/Qon5iptbJdmdeDOJ2MOvLU6YrlCO5XdGzJjVt1JeCXCuYZn1FG4IJ rsZbvkp3w0U3BuRwq41FK2RqwlMp+6VkAjMd5gqLL8/AWnLGy+T5pLtADiOyNeBa f9EDqrVXz0PwuLt7JXR2TktAVEv/vlGWKnmqYWGTEr45BDsxRVdV49QMnMIIjrPA ohLKqYJgX5bU4XwHfbePLU/Jt8P1Kc+bdh4iTpMJSTEETdnMt0W9GdpwI+hKZThH hZoALp9KBimIh/To8LnuSLeJ4NItkXelLZzzvGbX4wJSSBtA/CvG+1akyRnhE86m Z5xp71tIBAQ45KHBz6sN95NTQirCLgbfReE7jo2xfAspqY8yUotorMoYdHz/gWMs xX/x4BdcfYBd25YDYT6SwNLZ0uGwtwxnRvzNURmpLu6WY177cg50CgL32skxVvIJ TlsQDVyQj8DcIb0GfevUk1X7EL6lYz2czjgpA2HvyNIXJRGJhm5+1iyTcaGOYQ4F WsZj8GI8ECF/LYssa4tyrT2WW7MbHpXY1f4Qn3AD+XymtSQ6la8pPEh2YXBPWwvr ep6Sbib+61h+mIMem25i =ZE0j -----END PGP SIGNATURE----- Merge tag 'pwm/for-3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm changes from Thierry Reding: "The set of changes for this merge window contains two new drivers: one for Rockchip SoCs and another for STMicroelectronics STiH4xx SoCs. The remainder of the changes are the usual small cleanups such as removing redundant OOM messages, signalling that a PWM chip's operations can sleep and removing an unneeded dependency" * tag 'pwm/for-3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: rockchip: Added to support for RK3288 SoC pwm: rockchip: document RK3288 SoC compatible pwm: sti: Remove PWM period table pwm: sti: Sync between enable/disable calls pwm: sti: Ensure same period values for all channels pwm: sti: Fix PWM prescaler handling pwm: sti: Supply Device Tree binding documentation for ST's PWM IP pwm: sti: Add new driver for ST's PWM IP pwm: imx: set can_sleep flag for imx_pwm pwm: lpss: remove dependency on clk framework pwm: pwm-tipwmss: remove unnecessary OOM messages pwm: rockchip: document device tree bindings pwm: add Rockchip SoC PWM support
This commit is contained in:
Linus Torvalds
Коммит
34b20e6df6
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@ -0,0 +1,20 @@
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Rockchip PWM controller
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Required properties:
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- compatible: should be "rockchip,<name>-pwm"
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"rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
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"rockchip,rk3288-pwm": found on RK3288 SoC
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"rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
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- reg: physical base address and length of the controller's registers
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- clocks: phandle and clock specifier of the PWM reference clock
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- #pwm-cells: should be 2. See pwm.txt in this directory for a
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description of the cell format.
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Example:
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pwm0: pwm@20030000 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20030000 0x10>;
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clocks = <&cru PCLK_PWM01>;
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#pwm-cells = <2>;
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};
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@ -0,0 +1,41 @@
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STMicroelectronics PWM driver bindings
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--------------------------------------
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Required parameters:
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- compatible : "st,pwm"
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- #pwm-cells : Number of cells used to specify a PWM. First cell
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specifies the per-chip index of the PWM to use and the
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second cell is the period in nanoseconds - fixed to 2
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for STiH41x.
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- reg : Physical base address and length of the controller's
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registers.
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- pinctrl-names: Set to "default".
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- pinctrl-0: List of phandles pointing to pin configuration nodes
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for PWM module.
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For Pinctrl properties, please refer to [1].
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- clock-names: Set to "pwm".
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- clocks: phandle of the clock used by the PWM module.
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For Clk properties, please refer to [2].
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Optional properties:
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- st,pwm-num-chan: Number of available channels. If not passed, the driver
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will consider single channel by default.
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[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Example:
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pwm1: pwm@fe510000 {
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compatible = "st,pwm";
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reg = <0xfe510000 0x68>;
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1_chan0_default
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&pinctrl_pwm1_chan1_default
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&pinctrl_pwm1_chan2_default
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&pinctrl_pwm1_chan3_default>;
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clocks = <&clk_sysin>;
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clock-names = "pwm";
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st,pwm-num-chan = <4>;
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};
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@ -206,6 +206,13 @@ config PWM_RENESAS_TPU
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To compile this driver as a module, choose M here: the module
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will be called pwm-renesas-tpu.
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config PWM_ROCKCHIP
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tristate "Rockchip PWM support"
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depends on ARCH_ROCKCHIP
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help
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Generic PWM framework driver for the PWM controller found on
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Rockchip SoCs.
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config PWM_SAMSUNG
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tristate "Samsung PWM support"
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depends on PLAT_SAMSUNG
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@ -226,6 +233,16 @@ config PWM_SPEAR
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To compile this driver as a module, choose M here: the module
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will be called pwm-spear.
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config PWM_STI
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tristate "STiH4xx PWM support"
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depends on ARCH_STI
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depends on OF
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help
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Generic PWM framework driver for STiH4xx SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sti.
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config PWM_TEGRA
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tristate "NVIDIA Tegra PWM support"
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depends on ARCH_TEGRA
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@ -18,8 +18,10 @@ obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
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obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o
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obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
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obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_STI) += pwm-sti.o
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obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
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obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
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obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
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@ -262,6 +262,7 @@ static int imx_pwm_probe(struct platform_device *pdev)
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imx->chip.dev = &pdev->dev;
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imx->chip.base = -1;
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imx->chip.npwm = 1;
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imx->chip.can_sleep = true;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
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@ -14,7 +14,6 @@
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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@ -37,7 +36,6 @@ static int pci_drv, plat_drv; /* So we know which drivers registered */
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struct pwm_lpss_chip {
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struct pwm_chip chip;
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void __iomem *regs;
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struct clk *clk;
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unsigned long clk_rate;
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};
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@ -97,11 +95,6 @@ static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct pwm_lpss_chip *lpwm = to_lpwm(chip);
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u32 ctrl;
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int ret;
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ret = clk_prepare_enable(lpwm->clk);
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if (ret)
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return ret;
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ctrl = readl(lpwm->regs + PWM);
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writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);
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@ -116,8 +109,6 @@ static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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ctrl = readl(lpwm->regs + PWM);
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writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
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clk_disable_unprepare(lpwm->clk);
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}
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static const struct pwm_ops pwm_lpss_ops = {
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@ -142,17 +133,7 @@ static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
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if (IS_ERR(lpwm->regs))
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return ERR_CAST(lpwm->regs);
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if (info) {
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lpwm->clk_rate = info->clk_rate;
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} else {
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lpwm->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(lpwm->clk)) {
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dev_err(dev, "failed to get PWM clock\n");
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return ERR_CAST(lpwm->clk);
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}
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lpwm->clk_rate = clk_get_rate(lpwm->clk);
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}
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lpwm->clk_rate = info->clk_rate;
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lpwm->chip.dev = dev;
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lpwm->chip.ops = &pwm_lpss_ops;
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lpwm->chip.base = -1;
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@ -221,12 +202,19 @@ static struct pci_driver pwm_lpss_driver_pci = {
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static int pwm_lpss_probe_platform(struct platform_device *pdev)
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{
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const struct pwm_lpss_boardinfo *info;
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const struct acpi_device_id *id;
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struct pwm_lpss_chip *lpwm;
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struct resource *r;
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id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev);
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if (!id)
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return -ENODEV;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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lpwm = pwm_lpss_probe(&pdev->dev, r, NULL);
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info = (struct pwm_lpss_boardinfo *)id->driver_data;
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lpwm = pwm_lpss_probe(&pdev->dev, r, info);
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if (IS_ERR(lpwm))
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return PTR_ERR(lpwm);
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@ -242,7 +230,7 @@ static int pwm_lpss_remove_platform(struct platform_device *pdev)
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}
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static const struct acpi_device_id pwm_lpss_acpi_match[] = {
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{ "80860F09", 0 },
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{ "80860F09", (unsigned long)&byt_info },
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{ },
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};
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MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match);
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@ -0,0 +1,264 @@
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/*
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* PWM driver for Rockchip SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/time.h>
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#define PWM_CTRL_TIMER_EN (1 << 0)
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#define PWM_CTRL_OUTPUT_EN (1 << 3)
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#define PWM_ENABLE (1 << 0)
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#define PWM_CONTINUOUS (1 << 1)
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#define PWM_DUTY_POSITIVE (1 << 3)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_LP_DISABLE (0 << 8)
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struct rockchip_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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const struct rockchip_pwm_data *data;
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void __iomem *base;
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};
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struct rockchip_pwm_regs {
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unsigned long duty;
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unsigned long period;
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unsigned long cntr;
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unsigned long ctrl;
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};
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struct rockchip_pwm_data {
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struct rockchip_pwm_regs regs;
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unsigned int prescaler;
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void (*set_enable)(struct pwm_chip *chip, bool enable);
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};
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static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
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{
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return container_of(c, struct rockchip_pwm_chip, chip);
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}
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static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
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u32 val;
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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}
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static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS | PWM_DUTY_POSITIVE |
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PWM_INACTIVE_NEGATIVE;
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u32 val;
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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}
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static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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unsigned long period, duty;
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u64 clk_rate, div;
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int ret;
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clk_rate = clk_get_rate(pc->clk);
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/*
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* Since period and duty cycle registers have a width of 32
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* bits, every possible input period can be obtained using the
|
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* default prescaler value for all practical clock rate values.
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*/
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div = clk_rate * period_ns;
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do_div(div, pc->data->prescaler * NSEC_PER_SEC);
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period = div;
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|
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div = clk_rate * duty_ns;
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do_div(div, pc->data->prescaler * NSEC_PER_SEC);
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duty = div;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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|
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writel(period, pc->base + pc->data->regs.period);
|
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writel(duty, pc->base + pc->data->regs.duty);
|
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writel(0, pc->base + pc->data->regs.cntr);
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clk_disable(pc->clk);
|
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|
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return 0;
|
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}
|
||||
|
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static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
|
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{
|
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
|
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int ret;
|
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|
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ret = clk_enable(pc->clk);
|
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if (ret)
|
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return ret;
|
||||
|
||||
pc->data->set_enable(chip, true);
|
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|
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return 0;
|
||||
}
|
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|
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static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
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{
|
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
|
||||
|
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pc->data->set_enable(chip, false);
|
||||
|
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clk_disable(pc->clk);
|
||||
}
|
||||
|
||||
static const struct pwm_ops rockchip_pwm_ops = {
|
||||
.config = rockchip_pwm_config,
|
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.enable = rockchip_pwm_enable,
|
||||
.disable = rockchip_pwm_disable,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct rockchip_pwm_data pwm_data_v1 = {
|
||||
.regs = {
|
||||
.duty = 0x04,
|
||||
.period = 0x08,
|
||||
.cntr = 0x00,
|
||||
.ctrl = 0x0c,
|
||||
},
|
||||
.prescaler = 2,
|
||||
.set_enable = rockchip_pwm_set_enable_v1,
|
||||
};
|
||||
|
||||
static const struct rockchip_pwm_data pwm_data_v2 = {
|
||||
.regs = {
|
||||
.duty = 0x08,
|
||||
.period = 0x04,
|
||||
.cntr = 0x00,
|
||||
.ctrl = 0x0c,
|
||||
},
|
||||
.prescaler = 1,
|
||||
.set_enable = rockchip_pwm_set_enable_v2,
|
||||
};
|
||||
|
||||
static const struct rockchip_pwm_data pwm_data_vop = {
|
||||
.regs = {
|
||||
.duty = 0x08,
|
||||
.period = 0x04,
|
||||
.cntr = 0x0c,
|
||||
.ctrl = 0x00,
|
||||
},
|
||||
.prescaler = 1,
|
||||
.set_enable = rockchip_pwm_set_enable_v2,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_pwm_dt_ids[] = {
|
||||
{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
|
||||
{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
|
||||
{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
|
||||
|
||||
static int rockchip_pwm_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *id;
|
||||
struct rockchip_pwm_chip *pc;
|
||||
struct resource *r;
|
||||
int ret;
|
||||
|
||||
id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
|
||||
if (!id)
|
||||
return -EINVAL;
|
||||
|
||||
pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
|
||||
if (!pc)
|
||||
return -ENOMEM;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pc->base = devm_ioremap_resource(&pdev->dev, r);
|
||||
if (IS_ERR(pc->base))
|
||||
return PTR_ERR(pc->base);
|
||||
|
||||
pc->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(pc->clk))
|
||||
return PTR_ERR(pc->clk);
|
||||
|
||||
ret = clk_prepare(pc->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, pc);
|
||||
|
||||
pc->data = id->data;
|
||||
pc->chip.dev = &pdev->dev;
|
||||
pc->chip.ops = &rockchip_pwm_ops;
|
||||
pc->chip.base = -1;
|
||||
pc->chip.npwm = 1;
|
||||
|
||||
ret = pwmchip_add(&pc->chip);
|
||||
if (ret < 0) {
|
||||
clk_unprepare(pc->clk);
|
||||
dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_pwm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
|
||||
|
||||
clk_unprepare(pc->clk);
|
||||
|
||||
return pwmchip_remove(&pc->chip);
|
||||
}
|
||||
|
||||
static struct platform_driver rockchip_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-pwm",
|
||||
.of_match_table = rockchip_pwm_dt_ids,
|
||||
},
|
||||
.probe = rockchip_pwm_probe,
|
||||
.remove = rockchip_pwm_remove,
|
||||
};
|
||||
module_platform_driver(rockchip_pwm_driver);
|
||||
|
||||
MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
|
||||
MODULE_DESCRIPTION("Rockchip SoC PWM driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
/*
|
||||
* PWM device driver for ST SoCs.
|
||||
* Author: Ajit Pal Singh <ajitpal.singh@st.com>
|
||||
*
|
||||
* Copyright (C) 2013-2014 STMicroelectronics (R&D) Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/math64.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pwm.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
#define STI_DS_REG(ch) (4 * (ch)) /* Channel's Duty Cycle register */
|
||||
#define STI_PWMCR 0x50 /* Control/Config register */
|
||||
#define STI_INTEN 0x54 /* Interrupt Enable/Disable register */
|
||||
#define PWM_PRESCALE_LOW_MASK 0x0f
|
||||
#define PWM_PRESCALE_HIGH_MASK 0xf0
|
||||
|
||||
/* Regfield IDs */
|
||||
enum {
|
||||
PWMCLK_PRESCALE_LOW,
|
||||
PWMCLK_PRESCALE_HIGH,
|
||||
PWM_EN,
|
||||
PWM_INT_EN,
|
||||
|
||||
/* Keep last */
|
||||
MAX_REGFIELDS
|
||||
};
|
||||
|
||||
struct sti_pwm_compat_data {
|
||||
const struct reg_field *reg_fields;
|
||||
unsigned int num_chan;
|
||||
unsigned int max_pwm_cnt;
|
||||
unsigned int max_prescale;
|
||||
};
|
||||
|
||||
struct sti_pwm_chip {
|
||||
struct device *dev;
|
||||
struct clk *clk;
|
||||
unsigned long clk_rate;
|
||||
struct regmap *regmap;
|
||||
struct sti_pwm_compat_data *cdata;
|
||||
struct regmap_field *prescale_low;
|
||||
struct regmap_field *prescale_high;
|
||||
struct regmap_field *pwm_en;
|
||||
struct regmap_field *pwm_int_en;
|
||||
struct pwm_chip chip;
|
||||
struct pwm_device *cur;
|
||||
unsigned int en_count;
|
||||
struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
|
||||
void __iomem *mmio;
|
||||
};
|
||||
|
||||
static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
|
||||
[PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWMCR, 0, 3),
|
||||
[PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWMCR, 11, 14),
|
||||
[PWM_EN] = REG_FIELD(STI_PWMCR, 9, 9),
|
||||
[PWM_INT_EN] = REG_FIELD(STI_INTEN, 0, 0),
|
||||
};
|
||||
|
||||
static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct sti_pwm_chip, chip);
|
||||
}
|
||||
|
||||
/*
|
||||
* Calculate the prescaler value corresponding to the period.
|
||||
*/
|
||||
static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
|
||||
unsigned int *prescale)
|
||||
{
|
||||
struct sti_pwm_compat_data *cdata = pc->cdata;
|
||||
unsigned long val;
|
||||
unsigned int ps;
|
||||
|
||||
/*
|
||||
* prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_count + 1)) - 1
|
||||
*/
|
||||
val = NSEC_PER_SEC / pc->clk_rate;
|
||||
val *= cdata->max_pwm_cnt + 1;
|
||||
|
||||
if (period % val) {
|
||||
return -EINVAL;
|
||||
} else {
|
||||
ps = period / val - 1;
|
||||
if (ps > cdata->max_prescale)
|
||||
return -EINVAL;
|
||||
}
|
||||
*prescale = ps;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Calculate the number of PWM devices configured with a period. */
|
||||
static unsigned int sti_pwm_count_configured(struct pwm_chip *chip)
|
||||
{
|
||||
struct pwm_device *pwm;
|
||||
unsigned int ncfg = 0;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < chip->npwm; i++) {
|
||||
pwm = &chip->pwms[i];
|
||||
if (test_bit(PWMF_REQUESTED, &pwm->flags)) {
|
||||
if (pwm_get_period(pwm))
|
||||
ncfg++;
|
||||
}
|
||||
}
|
||||
|
||||
return ncfg;
|
||||
}
|
||||
|
||||
/*
|
||||
* For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles.
|
||||
* The only way to change the period (apart from changing the PWM input clock)
|
||||
* is to change the PWM clock prescaler.
|
||||
* The prescaler is of 8 bits, so 256 prescaler values and hence
|
||||
* 256 possible period values are supported (for a particular clock rate).
|
||||
* The requested period will be applied only if it matches one of these
|
||||
* 256 values.
|
||||
*/
|
||||
static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
int duty_ns, int period_ns)
|
||||
{
|
||||
struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
|
||||
struct sti_pwm_compat_data *cdata = pc->cdata;
|
||||
struct pwm_device *cur = pc->cur;
|
||||
struct device *dev = pc->dev;
|
||||
unsigned int prescale = 0, pwmvalx;
|
||||
int ret;
|
||||
unsigned int ncfg;
|
||||
bool period_same = false;
|
||||
|
||||
ncfg = sti_pwm_count_configured(chip);
|
||||
if (ncfg)
|
||||
period_same = (period_ns == pwm_get_period(cur));
|
||||
|
||||
/* Allow configuration changes if one of the
|
||||
* following conditions satisfy.
|
||||
* 1. No channels have been configured.
|
||||
* 2. Only one channel has been configured and the new request
|
||||
* is for the same channel.
|
||||
* 3. Only one channel has been configured and the new request is
|
||||
* for a new channel and period of the new channel is same as
|
||||
* the current configured period.
|
||||
* 4. More than one channels are configured and period of the new
|
||||
* requestis the same as the current period.
|
||||
*/
|
||||
if (!ncfg ||
|
||||
((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
|
||||
((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
|
||||
((ncfg > 1) && period_same)) {
|
||||
/* Enable clock before writing to PWM registers. */
|
||||
ret = clk_enable(pc->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!period_same) {
|
||||
ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
|
||||
if (ret)
|
||||
goto clk_dis;
|
||||
|
||||
ret =
|
||||
regmap_field_write(pc->prescale_low,
|
||||
prescale & PWM_PRESCALE_LOW_MASK);
|
||||
if (ret)
|
||||
goto clk_dis;
|
||||
|
||||
ret =
|
||||
regmap_field_write(pc->prescale_high,
|
||||
(prescale & PWM_PRESCALE_HIGH_MASK) >> 4);
|
||||
if (ret)
|
||||
goto clk_dis;
|
||||
}
|
||||
|
||||
/*
|
||||
* When PWMVal == 0, PWM pulse = 1 local clock cycle.
|
||||
* When PWMVal == max_pwm_count,
|
||||
* PWM pulse = (max_pwm_count + 1) local cycles,
|
||||
* that is continuous pulse: signal never goes low.
|
||||
*/
|
||||
pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns;
|
||||
|
||||
ret = regmap_write(pc->regmap, STI_DS_REG(pwm->hwpwm), pwmvalx);
|
||||
if (ret)
|
||||
goto clk_dis;
|
||||
|
||||
ret = regmap_field_write(pc->pwm_int_en, 0);
|
||||
|
||||
pc->cur = pwm;
|
||||
|
||||
dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n",
|
||||
prescale, period_ns, duty_ns, pwmvalx);
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk_dis:
|
||||
clk_disable(pc->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
|
||||
struct device *dev = pc->dev;
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* Since we have a common enable for all PWM channels,
|
||||
* do not enable if already enabled.
|
||||
*/
|
||||
mutex_lock(&pc->sti_pwm_lock);
|
||||
if (!pc->en_count) {
|
||||
ret = clk_enable(pc->clk);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = regmap_field_write(pc->pwm_en, 1);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable PWM device:%d\n",
|
||||
pwm->hwpwm);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
pc->en_count++;
|
||||
out:
|
||||
mutex_unlock(&pc->sti_pwm_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
|
||||
|
||||
mutex_lock(&pc->sti_pwm_lock);
|
||||
if (--pc->en_count) {
|
||||
mutex_unlock(&pc->sti_pwm_lock);
|
||||
return;
|
||||
}
|
||||
regmap_field_write(pc->pwm_en, 0);
|
||||
|
||||
clk_disable(pc->clk);
|
||||
mutex_unlock(&pc->sti_pwm_lock);
|
||||
}
|
||||
|
||||
static const struct pwm_ops sti_pwm_ops = {
|
||||
.config = sti_pwm_config,
|
||||
.enable = sti_pwm_enable,
|
||||
.disable = sti_pwm_disable,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
|
||||
{
|
||||
struct device *dev = pc->dev;
|
||||
const struct reg_field *reg_fields;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct sti_pwm_compat_data *cdata = pc->cdata;
|
||||
u32 num_chan;
|
||||
|
||||
of_property_read_u32(np, "st,pwm-num-chan", &num_chan);
|
||||
if (num_chan)
|
||||
cdata->num_chan = num_chan;
|
||||
|
||||
reg_fields = cdata->reg_fields;
|
||||
|
||||
pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
|
||||
reg_fields[PWMCLK_PRESCALE_LOW]);
|
||||
if (IS_ERR(pc->prescale_low))
|
||||
return PTR_ERR(pc->prescale_low);
|
||||
|
||||
pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
|
||||
reg_fields[PWMCLK_PRESCALE_HIGH]);
|
||||
if (IS_ERR(pc->prescale_high))
|
||||
return PTR_ERR(pc->prescale_high);
|
||||
|
||||
pc->pwm_en = devm_regmap_field_alloc(dev, pc->regmap,
|
||||
reg_fields[PWM_EN]);
|
||||
if (IS_ERR(pc->pwm_en))
|
||||
return PTR_ERR(pc->pwm_en);
|
||||
|
||||
pc->pwm_int_en = devm_regmap_field_alloc(dev, pc->regmap,
|
||||
reg_fields[PWM_INT_EN]);
|
||||
if (IS_ERR(pc->pwm_int_en))
|
||||
return PTR_ERR(pc->pwm_int_en);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct regmap_config sti_pwm_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static int sti_pwm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sti_pwm_compat_data *cdata;
|
||||
struct sti_pwm_chip *pc;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
|
||||
if (!pc)
|
||||
return -ENOMEM;
|
||||
|
||||
cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
|
||||
if (!cdata)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
pc->mmio = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(pc->mmio))
|
||||
return PTR_ERR(pc->mmio);
|
||||
|
||||
pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
|
||||
&sti_pwm_regmap_config);
|
||||
if (IS_ERR(pc->regmap))
|
||||
return PTR_ERR(pc->regmap);
|
||||
|
||||
/*
|
||||
* Setup PWM data with default values: some values could be replaced
|
||||
* with specific ones provided from Device Tree.
|
||||
*/
|
||||
cdata->reg_fields = &sti_pwm_regfields[0];
|
||||
cdata->max_prescale = 0xff;
|
||||
cdata->max_pwm_cnt = 255;
|
||||
cdata->num_chan = 1;
|
||||
|
||||
pc->cdata = cdata;
|
||||
pc->dev = dev;
|
||||
pc->en_count = 0;
|
||||
mutex_init(&pc->sti_pwm_lock);
|
||||
|
||||
ret = sti_pwm_probe_dt(pc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pc->clk = of_clk_get_by_name(dev->of_node, "pwm");
|
||||
if (IS_ERR(pc->clk)) {
|
||||
dev_err(dev, "failed to get PWM clock\n");
|
||||
return PTR_ERR(pc->clk);
|
||||
}
|
||||
|
||||
pc->clk_rate = clk_get_rate(pc->clk);
|
||||
if (!pc->clk_rate) {
|
||||
dev_err(dev, "failed to get clock rate\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_prepare(pc->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to prepare clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pc->chip.dev = dev;
|
||||
pc->chip.ops = &sti_pwm_ops;
|
||||
pc->chip.base = -1;
|
||||
pc->chip.npwm = pc->cdata->num_chan;
|
||||
pc->chip.can_sleep = true;
|
||||
|
||||
ret = pwmchip_add(&pc->chip);
|
||||
if (ret < 0) {
|
||||
clk_unprepare(pc->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, pc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sti_pwm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < pc->cdata->num_chan; i++)
|
||||
pwm_disable(&pc->chip.pwms[i]);
|
||||
|
||||
clk_unprepare(pc->clk);
|
||||
|
||||
return pwmchip_remove(&pc->chip);
|
||||
}
|
||||
|
||||
static const struct of_device_id sti_pwm_of_match[] = {
|
||||
{ .compatible = "st,sti-pwm", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
|
||||
|
||||
static struct platform_driver sti_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "sti-pwm",
|
||||
.of_match_table = sti_pwm_of_match,
|
||||
},
|
||||
.probe = sti_pwm_probe,
|
||||
.remove = sti_pwm_remove,
|
||||
};
|
||||
module_platform_driver(sti_pwm_driver);
|
||||
|
||||
MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
|
||||
MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -62,10 +62,8 @@ static int pwmss_probe(struct platform_device *pdev)
|
|||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
|
||||
if (!info) {
|
||||
dev_err(&pdev->dev, "failed to allocate memory\n");
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mutex_init(&info->pwmss_lock);
|
||||
|
||||
|
|
|
|||
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