Merge branch 'dt/irq-fix' into next/dt64
* dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
This commit is contained in:
Коммит
37179033fc
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@ -255,10 +255,10 @@
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/* Local timer */
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf01>,
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<1 14 0xf01>,
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<1 11 0xf01>,
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<1 10 0xf01>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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timer0: timer0@ffc03000 {
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@ -102,13 +102,13 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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@ -110,10 +110,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
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<1 13 0xff01>, /* Non-secure Phys IRQ */
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<1 14 0xff01>, /* Virt IRQ */
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<1 15 0xff01>; /* Hyp IRQ */
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interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
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<1 13 0xff08>, /* Non-secure Phys IRQ */
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<1 14 0xff08>, /* Virt IRQ */
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<1 15 0xff08>; /* Hyp IRQ */
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clock-frequency = <50000000>;
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};
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@ -88,13 +88,13 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>;
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IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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@ -354,10 +354,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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<1 14 0xff01>,
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<1 11 0xff01>,
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<1 10 0xff01>;
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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pmu {
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@ -475,13 +475,13 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>;
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu_system_controller: system-controller@105c0000 {
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@ -119,10 +119,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x1>, /* Physical Secure PPI */
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<1 14 0x1>, /* Physical Non-Secure PPI */
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<1 11 0x1>, /* Virtual PPI */
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<1 10 0x1>; /* Hypervisor PPI */
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interrupts = <1 13 0xf08>, /* Physical Secure PPI */
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<1 14 0xf08>, /* Physical Non-Secure PPI */
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<1 11 0xf08>, /* Virtual PPI */
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<1 10 0xf08>; /* Hypervisor PPI */
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};
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pmu {
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@ -191,10 +191,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
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<1 14 4>, /* Physical Non-Secure PPI, active-low */
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<1 11 4>, /* Virtual PPI, active-low */
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<1 10 4>; /* Hypervisor PPI, active-low */
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};
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pmu {
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@ -122,10 +122,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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@ -118,10 +118,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf01>,
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<1 14 0xf01>,
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<1 11 0xf01>,
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<1 10 0xf01>;
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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soc {
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@ -66,10 +66,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <1 13 0xf01>,
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<1 14 0xf01>,
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<1 11 0xf01>,
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<1 10 0xf01>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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amba_apu {
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