Merge branch 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo <shawn.guo@linaro.org>: * 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx6q: add clocks for gpmi-nand ARM: imx: enable flexcan on imx25, imx35, imx53, imx6q ARM: imx6q: add DT node for gpmi nand ARM: imx6q: add clock for apbh-dma ARM: imx6q: add DT node for apbh-dma Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
3858f8f91a
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@ -22,6 +22,12 @@
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};
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soc {
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gpmi-nand@00112000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "disabled"; /* gpmi nand conflicts with SD */
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};
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aips-bus@02100000 { /* AIPS2 */
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ethernet@02188000 {
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phy-mode = "rgmii";
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@ -87,6 +87,23 @@
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interrupt-parent = <&intc>;
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ranges;
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dma-apbh@00110000 {
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compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x00110000 0x2000>;
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};
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gpmi-nand@00112000 {
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compatible = "fsl,imx6q-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <0 13 0x04>, <0 15 0x04>;
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interrupt-names = "gpmi-dma", "bch";
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fsl,gpmi-dma-channel = <0>;
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status = "disabled";
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};
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timer@00a00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x00a00600 0x20>;
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@ -495,6 +512,30 @@
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};
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};
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gpmi-nand {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
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1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
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1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
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1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
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1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
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1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
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1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
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1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
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1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
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1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
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1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
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1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
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1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
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1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
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1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
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1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
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1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
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1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
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1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
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};
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};
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i2c1 {
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pinctrl_i2c1_1: i2c1grp-1 {
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fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
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@ -52,6 +52,7 @@ config SOC_IMX25
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select ARCH_MX25
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select COMMON_CLK
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select CPU_ARM926T
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select HAVE_CAN_FLEXCAN if CAN
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select ARCH_MXC_IOMUX_V3
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select MXC_AVIC
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@ -79,6 +80,7 @@ config SOC_IMX35
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select HAVE_EPIT
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select MXC_AVIC
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select SMP_ON_UP if SMP
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select HAVE_CAN_FLEXCAN if CAN
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config SOC_IMX5
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select CPU_V7
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@ -105,6 +107,7 @@ config SOC_IMX53
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select SOC_IMX5
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select ARCH_MX5
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select ARCH_MX53
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select HAVE_CAN_FLEXCAN if CAN
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if ARCH_IMX_V4_V5
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@ -826,6 +829,7 @@ config SOC_IMX6Q
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select COMMON_CLK
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select CPU_V7
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select HAVE_ARM_SCU
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select HAVE_CAN_FLEXCAN if CAN
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select HAVE_IMX_GPC
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select HAVE_IMX_MMDC
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select HAVE_IMX_SRC
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@ -147,7 +147,7 @@ enum mx6q_clks {
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esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
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hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
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ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
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mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
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mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
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gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
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ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
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usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
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@ -318,7 +318,7 @@ int __init mx6q_clocks_init(void)
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clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
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/* name parent_name reg shift */
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clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4);
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clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
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clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
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clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
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clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
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@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void)
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clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
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clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
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clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
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clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
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clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
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clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
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clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
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@ -394,6 +395,12 @@ int __init mx6q_clocks_init(void)
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clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
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clk_register_clkdev(clk[twd], NULL, "smp_twd");
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clk_register_clkdev(clk[usboh3], NULL, "usboh3");
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clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
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clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
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clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
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clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
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clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
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