Merge branch 'remotes/lorenzo/pci/cadence'
- Add DT binding and TI j721e support for refclk to PCIe connector (Kishon Vijay Abraham I) - Add host mode and endpoint mode DT bindings for TI AM64 SoC (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: PCI: j721e: Add support to provide refclk to PCIe connector dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector
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Коммит
3ec17ca688
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@ -16,13 +16,15 @@ allOf:
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properties:
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compatible:
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oneOf:
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- const: ti,j721e-pcie-ep
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- description: PCIe EP controller in AM64
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items:
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- const: ti,am64-pcie-ep
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- const: ti,j721e-pcie-ep
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- description: PCIe EP controller in J7200
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items:
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- const: ti,j7200-pcie-ep
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- const: ti,j721e-pcie-ep
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- description: PCIe EP controller in J721E
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items:
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- const: ti,j721e-pcie-ep
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reg:
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maxItems: 4
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@ -66,7 +68,6 @@ required:
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- power-domains
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- clocks
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- clock-names
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- dma-coherent
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- max-functions
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- phys
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- phy-names
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@ -16,13 +16,15 @@ allOf:
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properties:
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compatible:
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oneOf:
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- const: ti,j721e-pcie-host
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- description: PCIe controller in AM64
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items:
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- const: ti,am64-pcie-host
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- const: ti,j721e-pcie-host
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- description: PCIe controller in J7200
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items:
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- const: ti,j7200-pcie-host
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- const: ti,j721e-pcie-host
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- description: PCIe controller in J721E
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items:
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- const: ti,j721e-pcie-host
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reg:
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maxItems: 4
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@ -46,12 +48,17 @@ properties:
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maxItems: 1
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clocks:
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maxItems: 1
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description: clock-specifier to represent input to the PCIe
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minItems: 1
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maxItems: 2
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description: |+
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clock-specifier to represent input to the PCIe for 1 item.
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2nd item if present represents reference clock to the connector.
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clock-names:
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minItems: 1
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items:
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- const: fck
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- const: pcie_refclk
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vendor-id:
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const: 0x104c
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@ -62,6 +69,8 @@ properties:
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- const: 0xb00d
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- items:
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- const: 0xb00f
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- items:
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- const: 0xb010
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msi-map: true
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@ -78,7 +87,6 @@ required:
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- vendor-id
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- device-id
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- msi-map
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- dma-coherent
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- dma-ranges
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- ranges
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- reset-gpios
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@ -6,6 +6,7 @@
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/io.h>
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@ -50,6 +51,7 @@ enum link_status {
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struct j721e_pcie {
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struct device *dev;
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struct clk *refclk;
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u32 mode;
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u32 num_lanes;
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struct cdns_pcie *cdns_pcie;
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@ -312,6 +314,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
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struct cdns_pcie_ep *ep;
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struct gpio_desc *gpiod;
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void __iomem *base;
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struct clk *clk;
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u32 num_lanes;
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u32 mode;
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int ret;
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@ -411,6 +414,20 @@ static int j721e_pcie_probe(struct platform_device *pdev)
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goto err_get_sync;
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}
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clk = devm_clk_get_optional(dev, "pcie_refclk");
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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dev_err(dev, "failed to get pcie_refclk\n");
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goto err_pcie_setup;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "failed to enable pcie_refclk\n");
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goto err_get_sync;
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}
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pcie->refclk = clk;
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/*
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* "Power Sequencing and Reset Signal Timings" table in
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* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
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@ -425,8 +442,10 @@ static int j721e_pcie_probe(struct platform_device *pdev)
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}
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ret = cdns_pcie_host_setup(rc);
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if (ret < 0)
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if (ret < 0) {
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clk_disable_unprepare(pcie->refclk);
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goto err_pcie_setup;
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}
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break;
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case PCI_MODE_EP:
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@ -479,6 +498,7 @@ static int j721e_pcie_remove(struct platform_device *pdev)
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struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
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struct device *dev = &pdev->dev;
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clk_disable_unprepare(pcie->refclk);
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cdns_pcie_disable_phy(cdns_pcie);
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pm_runtime_put(dev);
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pm_runtime_disable(dev);
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