csiostor:Remove T4 FCoE Support.
We found a subtle issue with FCoE on T4 very late in the game and decided not to productize FCoE on T4 and therefore there are no customers that will be impacted by this change. Hence T4 FCoE support is removed. FCoE supported only on T5 cards. changes in v2: - Make the commit message more clearer. Signed-off-by: Praveen Madhavan <praveenm@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Praveen Madhavan
David S. Miller
Родитель
b66a4eaaee
Коммит
3fb4c22eaa
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@ -60,37 +60,10 @@ int csio_msi = 2;
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static int dev_num;
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/* FCoE Adapter types & its description */
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static const struct csio_adap_desc csio_t4_fcoe_adapters[] = {
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{"T440-Dbg 10G", "Chelsio T440-Dbg 10G [FCoE]"},
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{"T420-CR 10G", "Chelsio T420-CR 10G [FCoE]"},
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{"T422-CR 10G/1G", "Chelsio T422-CR 10G/1G [FCoE]"},
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{"T440-CR 10G", "Chelsio T440-CR 10G [FCoE]"},
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{"T420-BCH 10G", "Chelsio T420-BCH 10G [FCoE]"},
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{"T440-BCH 10G", "Chelsio T440-BCH 10G [FCoE]"},
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{"T440-CH 10G", "Chelsio T440-CH 10G [FCoE]"},
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{"T420-SO 10G", "Chelsio T420-SO 10G [FCoE]"},
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{"T420-CX4 10G", "Chelsio T420-CX4 10G [FCoE]"},
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{"T420-BT 10G", "Chelsio T420-BT 10G [FCoE]"},
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{"T404-BT 1G", "Chelsio T404-BT 1G [FCoE]"},
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{"B420-SR 10G", "Chelsio B420-SR 10G [FCoE]"},
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{"B404-BT 1G", "Chelsio B404-BT 1G [FCoE]"},
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{"T480-CR 10G", "Chelsio T480-CR 10G [FCoE]"},
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{"T440-LP-CR 10G", "Chelsio T440-LP-CR 10G [FCoE]"},
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{"AMSTERDAM 10G", "Chelsio AMSTERDAM 10G [FCoE]"},
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{"HUAWEI T480 10G", "Chelsio HUAWEI T480 10G [FCoE]"},
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{"HUAWEI T440 10G", "Chelsio HUAWEI T440 10G [FCoE]"},
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{"HUAWEI STG 10G", "Chelsio HUAWEI STG 10G [FCoE]"},
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{"ACROMAG XAUI 10G", "Chelsio ACROMAG XAUI 10G [FCoE]"},
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{"ACROMAG SFP+ 10G", "Chelsio ACROMAG SFP+ 10G [FCoE]"},
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{"QUANTA SFP+ 10G", "Chelsio QUANTA SFP+ 10G [FCoE]"},
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{"HUAWEI 10Gbase-T", "Chelsio HUAWEI 10Gbase-T [FCoE]"},
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{"HUAWEI T4TOE 10G", "Chelsio HUAWEI T4TOE 10G [FCoE]"}
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};
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static const struct csio_adap_desc csio_t5_fcoe_adapters[] = {
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{"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
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{"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
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{"T522-CR 10G/1G", "Chelsio T452-CR 10G/1G [FCoE]"},
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{"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
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{"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
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{"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
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{"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
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@ -107,7 +80,9 @@ static const struct csio_adap_desc csio_t5_fcoe_adapters[] = {
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{"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"},
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{"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"},
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{"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"},
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{"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"}
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{"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"},
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{"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"},
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{"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"}
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};
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static void csio_mgmtm_cleanup(struct csio_mgmtm *);
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@ -1716,9 +1691,9 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
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uint32_t *cfg_data;
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int value_to_add = 0;
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if (request_firmware(&cf, CSIO_CF_FNAME(hw), dev) < 0) {
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if (request_firmware(&cf, FW_CFG_NAME_T5, dev) < 0) {
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csio_err(hw, "could not find config file %s, err: %d\n",
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CSIO_CF_FNAME(hw), ret);
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FW_CFG_NAME_T5, ret);
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return -ENOENT;
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}
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@ -1758,8 +1733,8 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
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}
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if (ret == 0) {
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csio_info(hw, "config file upgraded to %s\n",
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CSIO_CF_FNAME(hw));
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snprintf(path, 64, "%s%s", "/lib/firmware/", CSIO_CF_FNAME(hw));
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FW_CFG_NAME_T5);
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snprintf(path, 64, "%s%s", "/lib/firmware/", FW_CFG_NAME_T5);
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}
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leave:
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@ -2123,9 +2098,9 @@ csio_hw_flash_fw(struct csio_hw *hw, int *reset)
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return -EINVAL;
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}
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if (request_firmware(&fw, CSIO_FW_FNAME(hw), dev) < 0) {
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if (request_firmware(&fw, FW_FNAME_T5, dev) < 0) {
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csio_err(hw, "could not find firmware image %s, err: %d\n",
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CSIO_FW_FNAME(hw), ret);
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FW_FNAME_T5, ret);
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return -EINVAL;
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}
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@ -3207,7 +3182,7 @@ static void csio_ncsi_intr_handler(struct csio_hw *hw)
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*/
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static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
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{
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uint32_t v = csio_rd_reg32(hw, CSIO_MAC_INT_CAUSE_REG(hw, port));
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uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
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v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
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if (!v)
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@ -3217,7 +3192,7 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
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csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port);
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if (v & RXFIFO_PRTY_ERR_F)
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csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port);
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csio_wr_reg32(hw, v, CSIO_MAC_INT_CAUSE_REG(hw, port));
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csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
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csio_hw_fatal_err(hw);
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}
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@ -3966,13 +3941,7 @@ csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id)
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prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK);
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adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK);
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if (prot_type == CSIO_T4_FCOE_ASIC) {
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memcpy(hw->hw_ver,
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csio_t4_fcoe_adapters[adap_type].model_no, 16);
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memcpy(hw->model_desc,
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csio_t4_fcoe_adapters[adap_type].description,
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32);
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} else if (prot_type == CSIO_T5_FCOE_ASIC) {
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if (prot_type == CSIO_T5_FCOE_ASIC) {
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memcpy(hw->hw_ver,
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csio_t5_fcoe_adapters[adap_type].model_no, 16);
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memcpy(hw->model_desc,
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@ -4009,8 +3978,8 @@ csio_hw_init(struct csio_hw *hw)
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strcpy(hw->name, CSIO_HW_NAME);
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/* Initialize the HW chip ops with T4/T5 specific ops */
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hw->chip_ops = csio_is_t4(hw->chip_id) ? &t4_ops : &t5_ops;
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/* Initialize the HW chip ops T5 specific ops */
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hw->chip_ops = &t5_ops;
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/* Set the model & its description */
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@ -37,24 +37,14 @@
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#include "csio_defs.h"
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/* Define MACRO values */
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#define CSIO_HW_T4 0x4000
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#define CSIO_T4_FCOE_ASIC 0x4600
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#define CSIO_HW_T5 0x5000
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#define CSIO_T5_FCOE_ASIC 0x5600
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#define CSIO_HW_CHIP_MASK 0xF000
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#define T4_REGMAP_SIZE (160 * 1024)
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#define T5_REGMAP_SIZE (332 * 1024)
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#define FW_FNAME_T4 "cxgb4/t4fw.bin"
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#define FW_FNAME_T5 "cxgb4/t5fw.bin"
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#define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
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#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
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#define T4FW_VERSION_MAJOR 0x01
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#define T4FW_VERSION_MINOR 0x0B
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#define T4FW_VERSION_MICRO 0x1B
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#define T4FW_VERSION_BUILD 0x00
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#define T5FW_VERSION_MAJOR 0x01
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#define T5FW_VERSION_MINOR 0x0B
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#define T5FW_VERSION_MICRO 0x1B
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@ -65,27 +55,15 @@
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#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
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#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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enum chip_type {
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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T4_FIRST_REV = T4_A1,
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T4_LAST_REV = T4_A2,
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T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
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T5_FIRST_REV = T5_A0,
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T5_LAST_REV = T5_A1,
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};
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/* Define static functions */
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static inline int csio_is_t4(uint16_t chip)
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{
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return (chip == CSIO_HW_T4);
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}
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static inline int csio_is_t5(uint16_t chip)
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{
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return (chip == CSIO_HW_T5);
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@ -95,21 +73,6 @@ static inline int csio_is_t5(uint16_t chip)
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#define CSIO_DEVICE(devid, idx) \
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{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
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#define CSIO_HW_PIDX(hw, index) \
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(csio_is_t4(hw->chip_id) ? (PIDX_V(index)) : \
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(PIDX_T5_G(index) | DBTYPE_F))
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#define CSIO_HW_LP_INT_THRESH(hw, val) \
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(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \
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(LP_INT_THRESH_T5_V(val)))
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#define CSIO_HW_M_LP_INT_THRESH(hw) \
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(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M))
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#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
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(csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE_A)) : \
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(T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)))
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#include "t4fw_api.h"
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#define FW_VERSION(chip) ( \
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@ -125,11 +88,6 @@ struct fw_info {
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char *fw_mod_name;
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struct fw_hdr fw_hdr;
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};
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#define CSIO_FW_FNAME(hw) \
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(csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
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#define CSIO_CF_FNAME(hw) \
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(csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
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/* Declare ENUMS */
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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@ -163,7 +121,6 @@ struct csio_hw_chip_ops {
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void (*chip_dfs_create_ext_mem)(struct csio_hw *);
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};
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extern struct csio_hw_chip_ops t4_ops;
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extern struct csio_hw_chip_ops t5_ops;
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#endif /* #ifndef __CSIO_HW_CHIP_H__ */
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@ -1176,9 +1176,8 @@ static struct pci_error_handlers csio_err_handler = {
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*/
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#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
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static struct pci_device_id csio_pci_tbl[] = {
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/* Define for iSCSI uses PF5, FCoE uses PF6 */
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#define CH_PCI_DEVICE_ID_FUNCTION 0x5
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#define CH_PCI_DEVICE_ID_FUNCTION2 0x6
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/* Define for FCoE uses PF6 */
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#define CH_PCI_DEVICE_ID_FUNCTION 0x6
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#define CH_PCI_ID_TABLE_ENTRY(devid) \
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{ PCI_VDEVICE(CHELSIO, (devid)), 0 }
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@ -1256,5 +1255,4 @@ MODULE_DESCRIPTION(CSIO_DRV_DESC);
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MODULE_LICENSE(CSIO_DRV_LICENSE);
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MODULE_DEVICE_TABLE(pci, csio_pci_tbl);
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MODULE_VERSION(CSIO_DRV_VERSION);
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MODULE_FIRMWARE(FW_FNAME_T4);
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MODULE_FIRMWARE(FW_FNAME_T5);
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@ -85,7 +85,7 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
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*/
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if (flq->inc_idx >= 8) {
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csio_wr_reg32(hw, DBPRIO_F | QID_V(flq->un.fl.flid) |
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CSIO_HW_PIDX(hw, flq->inc_idx / 8),
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PIDX_T5_V(flq->inc_idx / 8) | DBTYPE_F,
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MYPF_REG(SGE_PF_KDOORBELL_A));
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flq->inc_idx &= 7;
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}
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@ -983,7 +983,7 @@ csio_wr_issue(struct csio_hw *hw, int qidx, bool prio)
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wmb();
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/* Ring SGE Doorbell writing q->pidx into it */
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csio_wr_reg32(hw, DBPRIO_V(prio) | QID_V(q->un.eq.physeqid) |
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CSIO_HW_PIDX(hw, q->inc_idx),
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PIDX_T5_V(q->inc_idx) | DBTYPE_F,
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MYPF_REG(SGE_PF_KDOORBELL_A));
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q->inc_idx = 0;
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@ -1467,12 +1467,11 @@ csio_wr_set_sge(struct csio_hw *hw)
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* and generate an interrupt when this occurs so we can recover.
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*/
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csio_set_reg_field(hw, SGE_DBFIFO_STATUS_A,
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HP_INT_THRESH_V(HP_INT_THRESH_M) |
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CSIO_HW_LP_INT_THRESH(hw,
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CSIO_HW_M_LP_INT_THRESH(hw)),
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HP_INT_THRESH_V(CSIO_SGE_DBFIFO_INT_THRESH) |
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CSIO_HW_LP_INT_THRESH(hw,
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CSIO_SGE_DBFIFO_INT_THRESH));
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LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
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LP_INT_THRESH_T5_V(CSIO_SGE_DBFIFO_INT_THRESH));
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csio_set_reg_field(hw, SGE_DBFIFO_STATUS2_A,
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HP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
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HP_INT_THRESH_T5_V(CSIO_SGE_DBFIFO_INT_THRESH));
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csio_set_reg_field(hw, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
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ENABLE_DROP_F);
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