Qualcomm ARM Based SoC Updates for v4.1
* Merged the based Qualcomm SCM and SCM boot support * Cleaned up SCM interface to only expose functional SCM APIs * Moved Qualcomm SCM code into drivers/firmware * Updated the SCM APIs for setting cpu cold and warm boot addresses * Added support for ADM CRCI muxing -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJVB0QrAAoJEF9hYXeAcXzBQbgQAIEr0DaEwyo0sE0vEbrVvN4E ObEvFNIyKC6dXxCFdzZ/RjIk5Pw0pmeVP+j7f178LEc1EitAkl28uNJ4Ewzo1ymG mmN8tGryQrLl98URyRK9TZa7KgJoUU5+C4DVWJzMokyvqWJbBWcRJ1n9SmPyith+ ePqyo/yzkucLdCntLtwcfj1Nhd9lY5k58f78JGrOZB0+tbbZT4PqjdQpVYizP9B4 owzgvpzZQhH+lqCrW3dyKdwd1/LARUuDVI1NAIz4roLJYO5IgZhMKwW4d6VrbunR PNiMpUnMkQY2Nyt3tbX57AgSvgoqjBL9Rjh9AuIx53GH8B/00x0ZBpmsRmrz5HN+ XkYszfr5LD6D+fBpJ8TZNn3pyXzy2mlGc5FWqQpBqC2kZnyz/p0Ah9lC59GMvTW0 MaaW+GgPIkGjK5y7l2yE7kQ27/IW3l0B2wWN/pFDq5GAYd6ZYXFTz01Zs0rJ1BmN e9NeegsOnH48ywR52vXHUBCbEgn8qSr1j4DG43VeC50QZ/KiXKcKcKIyUlsTA8JL wxMNs1l6Am5Bf295BN76N77u2xO71QbTIj+6HFpyHp/a6V7G9KApEzG7YGY3TdSs XxAOdI1rOY6I/qV3rE1GbZ9racAKyao1iSkW5X9t8fLlDUXaC6BtDoB2JKQL2Ylh SM4K6AzpmcYygfRKhiAB =KYay -----END PGP SIGNATURE----- Merge tag 'qcom-soc-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/drivers Merge "qcom SoC changes for v4.1" from Kumar Gala: Qualcomm ARM Based SoC Updates for v4.1 * Merged the based Qualcomm SCM and SCM boot support * Cleaned up SCM interface to only expose functional SCM APIs * Moved Qualcomm SCM code into drivers/firmware * Updated the SCM APIs for setting cpu cold and warm boot addresses * Added support for ADM CRCI muxing * tag 'qcom-soc-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: soc: qcom: gsbi: Add support for ADM CRCI muxing firmware: qcom: scm: Support cpu power down through SCM firmware: qcom: scm: Add qcom_scm_set_warm_boot_addr function firmware: qcom: scm: Clean cold boot entry to export only the API firmware: qcom: scm: Move the scm driver to drivers/firmware ARM: qcom: Prep scm code for move to drivers/firmware ARM: qcom: Cleanup scm interface to only export what is needed ARM: qcom: Merge scm and scm boot code together Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
4580cb8a98
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@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of
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the 4 GSBI IOs.
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Required properties:
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- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
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- compatible: Should contain "qcom,gsbi-v1.0.0"
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- cell-index: Should contain the GSBI index
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- reg: Address range for GSBI registers
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- clocks: required clock
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- clock-names: must contain "iface" entry
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@ -16,6 +17,8 @@ Required properties:
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Optional properties:
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- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
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dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
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dma.
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Required properties if child node exists:
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- #address-cells: Must be 1
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@ -39,6 +42,7 @@ Example for APQ8064:
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gsbi4@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <4>;
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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@ -48,22 +52,24 @@ Example for APQ8064:
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qcom,mode = <GSBI_PROT_I2C_UART>;
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qcom,crci = <GSBI_CRCI_QUP>;
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syscon-tcsr = <&tcsr>;
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/* child nodes go under here */
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i2c_qup4: i2c@16380000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <200000>;
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clock-frequency = <200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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uart4: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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@ -76,3 +82,7 @@ Example for APQ8064:
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,apq8064-tcsr", "syscon";
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reg = <0x1a400000 0x100>;
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};
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@ -1317,6 +1317,7 @@ L: linux-soc@vger.kernel.org
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S: Maintained
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F: arch/arm/mach-qcom/
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F: drivers/soc/qcom/
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F: drivers/firmware/qcom_scm.c
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
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ARM/RADISYS ENP2611 MACHINE SUPPORT
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@ -2160,6 +2160,8 @@ source "net/Kconfig"
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source "drivers/Kconfig"
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source "drivers/firmware/Kconfig"
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source "fs/Kconfig"
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source "arch/arm/Kconfig.debug"
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@ -22,7 +22,4 @@ config ARCH_MSM8974
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bool "Enable support for MSM8974"
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select HAVE_ARM_ARCH_TIMER
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config QCOM_SCM
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bool
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endif
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@ -1,5 +1,2 @@
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obj-y := board.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
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CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
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@ -17,10 +17,10 @@
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/qcom_scm.h>
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#include <asm/smp_plat.h>
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#include "scm-boot.h"
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
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#define SCSS_CPU1CORE_RESET 0x2d80
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@ -319,25 +319,10 @@ static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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unsigned int flags = 0;
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static const int cold_boot_flags[] = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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SCM_FLAG_COLDBOOT_CPU2,
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SCM_FLAG_COLDBOOT_CPU3,
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};
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int cpu;
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for_each_present_cpu(cpu) {
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map = cpu_logical_map(cpu);
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if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
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set_cpu_present(cpu, false);
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continue;
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}
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flags |= cold_boot_flags[map];
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}
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if (scm_set_boot_addr(virt_to_phys(secondary_startup_arm), flags)) {
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if (qcom_scm_set_cold_boot_addr(secondary_startup_arm,
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cpu_present_mask)) {
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for_each_present_cpu(cpu) {
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if (cpu == smp_processor_id())
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continue;
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@ -1,39 +0,0 @@
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "scm.h"
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#include "scm-boot.h"
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/*
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* Set the cold/warm boot address for one of the CPU cores.
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*/
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int scm_set_boot_addr(u32 addr, int flags)
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{
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struct {
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__le32 flags;
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__le32 addr;
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} cmd;
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cmd.addr = cpu_to_le32(addr);
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cmd.flags = cpu_to_le32(flags);
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return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
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&cmd, sizeof(cmd), NULL, 0);
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}
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EXPORT_SYMBOL(scm_set_boot_addr);
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@ -1,26 +0,0 @@
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_SCM_BOOT_H
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#define __MACH_SCM_BOOT_H
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#define SCM_BOOT_ADDR 0x1
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#define SCM_FLAG_COLDBOOT_CPU1 0x01
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#define SCM_FLAG_COLDBOOT_CPU2 0x08
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#define SCM_FLAG_COLDBOOT_CPU3 0x20
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#define SCM_FLAG_WARMBOOT_CPU0 0x04
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#define SCM_FLAG_WARMBOOT_CPU1 0x02
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#define SCM_FLAG_WARMBOOT_CPU2 0x10
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#define SCM_FLAG_WARMBOOT_CPU3 0x40
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int scm_set_boot_addr(u32 addr, int flags);
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#endif
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@ -1,326 +0,0 @@
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <asm/outercache.h>
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#include <asm/cacheflush.h>
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#include "scm.h"
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#define SCM_ENOMEM -5
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#define SCM_EOPNOTSUPP -4
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#define SCM_EINVAL_ADDR -3
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#define SCM_EINVAL_ARG -2
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#define SCM_ERROR -1
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#define SCM_INTERRUPTED 1
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static DEFINE_MUTEX(scm_lock);
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/**
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* struct scm_command - one SCM command buffer
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* @len: total available memory for command and response
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* @buf_offset: start of command buffer
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* @resp_hdr_offset: start of response buffer
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* @id: command to be executed
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* @buf: buffer returned from scm_get_command_buffer()
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*
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* An SCM command is laid out in memory as follows:
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*
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* ------------------- <--- struct scm_command
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* | command header |
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* ------------------- <--- scm_get_command_buffer()
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* | command buffer |
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* ------------------- <--- struct scm_response and
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* | response header | scm_command_to_response()
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* ------------------- <--- scm_get_response_buffer()
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* | response buffer |
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* -------------------
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*
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* There can be arbitrary padding between the headers and buffers so
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* you should always use the appropriate scm_get_*_buffer() routines
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* to access the buffers in a safe manner.
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*/
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struct scm_command {
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__le32 len;
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__le32 buf_offset;
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__le32 resp_hdr_offset;
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__le32 id;
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__le32 buf[0];
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};
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/**
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* struct scm_response - one SCM response buffer
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* @len: total available memory for response
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* @buf_offset: start of response data relative to start of scm_response
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* @is_complete: indicates if the command has finished processing
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*/
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struct scm_response {
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__le32 len;
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__le32 buf_offset;
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__le32 is_complete;
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};
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|
||||
/**
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||||
* alloc_scm_command() - Allocate an SCM command
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* @cmd_size: size of the command buffer
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* @resp_size: size of the response buffer
|
||||
*
|
||||
* Allocate an SCM command, including enough room for the command
|
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* and response headers as well as the command and response buffers.
|
||||
*
|
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* Returns a valid &scm_command on success or %NULL if the allocation fails.
|
||||
*/
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static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size)
|
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{
|
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struct scm_command *cmd;
|
||||
size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size +
|
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resp_size;
|
||||
u32 offset;
|
||||
|
||||
cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
|
||||
if (cmd) {
|
||||
cmd->len = cpu_to_le32(len);
|
||||
offset = offsetof(struct scm_command, buf);
|
||||
cmd->buf_offset = cpu_to_le32(offset);
|
||||
cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
|
||||
}
|
||||
return cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* free_scm_command() - Free an SCM command
|
||||
* @cmd: command to free
|
||||
*
|
||||
* Free an SCM command.
|
||||
*/
|
||||
static inline void free_scm_command(struct scm_command *cmd)
|
||||
{
|
||||
kfree(cmd);
|
||||
}
|
||||
|
||||
/**
|
||||
* scm_command_to_response() - Get a pointer to a scm_response
|
||||
* @cmd: command
|
||||
*
|
||||
* Returns a pointer to a response for a command.
|
||||
*/
|
||||
static inline struct scm_response *scm_command_to_response(
|
||||
const struct scm_command *cmd)
|
||||
{
|
||||
return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* scm_get_command_buffer() - Get a pointer to a command buffer
|
||||
* @cmd: command
|
||||
*
|
||||
* Returns a pointer to the command buffer of a command.
|
||||
*/
|
||||
static inline void *scm_get_command_buffer(const struct scm_command *cmd)
|
||||
{
|
||||
return (void *)cmd->buf;
|
||||
}
|
||||
|
||||
/**
|
||||
* scm_get_response_buffer() - Get a pointer to a response buffer
|
||||
* @rsp: response
|
||||
*
|
||||
* Returns a pointer to a response buffer of a response.
|
||||
*/
|
||||
static inline void *scm_get_response_buffer(const struct scm_response *rsp)
|
||||
{
|
||||
return (void *)rsp + le32_to_cpu(rsp->buf_offset);
|
||||
}
|
||||
|
||||
static int scm_remap_error(int err)
|
||||
{
|
||||
pr_err("scm_call failed with error code %d\n", err);
|
||||
switch (err) {
|
||||
case SCM_ERROR:
|
||||
return -EIO;
|
||||
case SCM_EINVAL_ADDR:
|
||||
case SCM_EINVAL_ARG:
|
||||
return -EINVAL;
|
||||
case SCM_EOPNOTSUPP:
|
||||
return -EOPNOTSUPP;
|
||||
case SCM_ENOMEM:
|
||||
return -ENOMEM;
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static u32 smc(u32 cmd_addr)
|
||||
{
|
||||
int context_id;
|
||||
register u32 r0 asm("r0") = 1;
|
||||
register u32 r1 asm("r1") = (u32)&context_id;
|
||||
register u32 r2 asm("r2") = cmd_addr;
|
||||
do {
|
||||
asm volatile(
|
||||
__asmeq("%0", "r0")
|
||||
__asmeq("%1", "r0")
|
||||
__asmeq("%2", "r1")
|
||||
__asmeq("%3", "r2")
|
||||
#ifdef REQUIRES_SEC
|
||||
".arch_extension sec\n"
|
||||
#endif
|
||||
"smc #0 @ switch to secure world\n"
|
||||
: "=r" (r0)
|
||||
: "r" (r0), "r" (r1), "r" (r2)
|
||||
: "r3");
|
||||
} while (r0 == SCM_INTERRUPTED);
|
||||
|
||||
return r0;
|
||||
}
|
||||
|
||||
static int __scm_call(const struct scm_command *cmd)
|
||||
{
|
||||
int ret;
|
||||
u32 cmd_addr = virt_to_phys(cmd);
|
||||
|
||||
/*
|
||||
* Flush the command buffer so that the secure world sees
|
||||
* the correct data.
|
||||
*/
|
||||
__cpuc_flush_dcache_area((void *)cmd, cmd->len);
|
||||
outer_flush_range(cmd_addr, cmd_addr + cmd->len);
|
||||
|
||||
ret = smc(cmd_addr);
|
||||
if (ret < 0)
|
||||
ret = scm_remap_error(ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void scm_inv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
u32 cacheline_size, ctr;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
|
||||
cacheline_size = 4 << ((ctr >> 16) & 0xf);
|
||||
|
||||
start = round_down(start, cacheline_size);
|
||||
end = round_up(end, cacheline_size);
|
||||
outer_inv_range(start, end);
|
||||
while (start < end) {
|
||||
asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
|
||||
: "memory");
|
||||
start += cacheline_size;
|
||||
}
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
/**
|
||||
* scm_call() - Send an SCM command
|
||||
* @svc_id: service identifier
|
||||
* @cmd_id: command identifier
|
||||
* @cmd_buf: command buffer
|
||||
* @cmd_len: length of the command buffer
|
||||
* @resp_buf: response buffer
|
||||
* @resp_len: length of the response buffer
|
||||
*
|
||||
* Sends a command to the SCM and waits for the command to finish processing.
|
||||
*
|
||||
* A note on cache maintenance:
|
||||
* Note that any buffers that are expected to be accessed by the secure world
|
||||
* must be flushed before invoking scm_call and invalidated in the cache
|
||||
* immediately after scm_call returns. Cache maintenance on the command and
|
||||
* response buffers is taken care of by scm_call; however, callers are
|
||||
* responsible for any other cached buffers passed over to the secure world.
|
||||
*/
|
||||
int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
|
||||
void *resp_buf, size_t resp_len)
|
||||
{
|
||||
int ret;
|
||||
struct scm_command *cmd;
|
||||
struct scm_response *rsp;
|
||||
unsigned long start, end;
|
||||
|
||||
cmd = alloc_scm_command(cmd_len, resp_len);
|
||||
if (!cmd)
|
||||
return -ENOMEM;
|
||||
|
||||
cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
|
||||
if (cmd_buf)
|
||||
memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len);
|
||||
|
||||
mutex_lock(&scm_lock);
|
||||
ret = __scm_call(cmd);
|
||||
mutex_unlock(&scm_lock);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
rsp = scm_command_to_response(cmd);
|
||||
start = (unsigned long)rsp;
|
||||
|
||||
do {
|
||||
scm_inv_range(start, start + sizeof(*rsp));
|
||||
} while (!rsp->is_complete);
|
||||
|
||||
end = (unsigned long)scm_get_response_buffer(rsp) + resp_len;
|
||||
scm_inv_range(start, end);
|
||||
|
||||
if (resp_buf)
|
||||
memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len);
|
||||
out:
|
||||
free_scm_command(cmd);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(scm_call);
|
||||
|
||||
u32 scm_get_version(void)
|
||||
{
|
||||
int context_id;
|
||||
static u32 version = -1;
|
||||
register u32 r0 asm("r0");
|
||||
register u32 r1 asm("r1");
|
||||
|
||||
if (version != -1)
|
||||
return version;
|
||||
|
||||
mutex_lock(&scm_lock);
|
||||
|
||||
r0 = 0x1 << 8;
|
||||
r1 = (u32)&context_id;
|
||||
do {
|
||||
asm volatile(
|
||||
__asmeq("%0", "r0")
|
||||
__asmeq("%1", "r1")
|
||||
__asmeq("%2", "r0")
|
||||
__asmeq("%3", "r1")
|
||||
#ifdef REQUIRES_SEC
|
||||
".arch_extension sec\n"
|
||||
#endif
|
||||
"smc #0 @ switch to secure world\n"
|
||||
: "=r" (r0), "=r" (r1)
|
||||
: "r" (r0), "r" (r1)
|
||||
: "r2", "r3");
|
||||
} while (r0 == SCM_INTERRUPTED);
|
||||
|
||||
version = r1;
|
||||
mutex_unlock(&scm_lock);
|
||||
|
||||
return version;
|
||||
}
|
||||
EXPORT_SYMBOL(scm_get_version);
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __MACH_SCM_H
|
||||
#define __MACH_SCM_H
|
||||
|
||||
#define SCM_SVC_BOOT 0x1
|
||||
#define SCM_SVC_PIL 0x2
|
||||
|
||||
extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
|
||||
void *resp_buf, size_t resp_len);
|
||||
|
||||
#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
|
||||
|
||||
extern u32 scm_get_version(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -132,6 +132,10 @@ config ISCSI_IBFT
|
|||
detect iSCSI boot parameters dynamically during system boot, say Y.
|
||||
Otherwise, say N.
|
||||
|
||||
config QCOM_SCM
|
||||
bool
|
||||
depends on ARM || ARM64
|
||||
|
||||
source "drivers/firmware/google/Kconfig"
|
||||
source "drivers/firmware/efi/Kconfig"
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@ obj-$(CONFIG_DMIID) += dmi-id.o
|
|||
obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
|
||||
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
|
||||
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
|
||||
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
|
||||
CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
|
||||
|
||||
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
|
||||
obj-$(CONFIG_EFI) += efi/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,494 @@
|
|||
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (C) 2015 Linaro Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/qcom_scm.h>
|
||||
|
||||
#include <asm/outercache.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
|
||||
#define QCOM_SCM_ENOMEM -5
|
||||
#define QCOM_SCM_EOPNOTSUPP -4
|
||||
#define QCOM_SCM_EINVAL_ADDR -3
|
||||
#define QCOM_SCM_EINVAL_ARG -2
|
||||
#define QCOM_SCM_ERROR -1
|
||||
#define QCOM_SCM_INTERRUPTED 1
|
||||
|
||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
|
||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
|
||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
|
||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
|
||||
|
||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
|
||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
|
||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
|
||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
|
||||
|
||||
struct qcom_scm_entry {
|
||||
int flag;
|
||||
void *entry;
|
||||
};
|
||||
|
||||
static struct qcom_scm_entry qcom_scm_wb[] = {
|
||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
|
||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
|
||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
|
||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
|
||||
};
|
||||
|
||||
static DEFINE_MUTEX(qcom_scm_lock);
|
||||
|
||||
/**
|
||||
* struct qcom_scm_command - one SCM command buffer
|
||||
* @len: total available memory for command and response
|
||||
* @buf_offset: start of command buffer
|
||||
* @resp_hdr_offset: start of response buffer
|
||||
* @id: command to be executed
|
||||
* @buf: buffer returned from qcom_scm_get_command_buffer()
|
||||
*
|
||||
* An SCM command is laid out in memory as follows:
|
||||
*
|
||||
* ------------------- <--- struct qcom_scm_command
|
||||
* | command header |
|
||||
* ------------------- <--- qcom_scm_get_command_buffer()
|
||||
* | command buffer |
|
||||
* ------------------- <--- struct qcom_scm_response and
|
||||
* | response header | qcom_scm_command_to_response()
|
||||
* ------------------- <--- qcom_scm_get_response_buffer()
|
||||
* | response buffer |
|
||||
* -------------------
|
||||
*
|
||||
* There can be arbitrary padding between the headers and buffers so
|
||||
* you should always use the appropriate qcom_scm_get_*_buffer() routines
|
||||
* to access the buffers in a safe manner.
|
||||
*/
|
||||
struct qcom_scm_command {
|
||||
__le32 len;
|
||||
__le32 buf_offset;
|
||||
__le32 resp_hdr_offset;
|
||||
__le32 id;
|
||||
__le32 buf[0];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_scm_response - one SCM response buffer
|
||||
* @len: total available memory for response
|
||||
* @buf_offset: start of response data relative to start of qcom_scm_response
|
||||
* @is_complete: indicates if the command has finished processing
|
||||
*/
|
||||
struct qcom_scm_response {
|
||||
__le32 len;
|
||||
__le32 buf_offset;
|
||||
__le32 is_complete;
|
||||
};
|
||||
|
||||
/**
|
||||
* alloc_qcom_scm_command() - Allocate an SCM command
|
||||
* @cmd_size: size of the command buffer
|
||||
* @resp_size: size of the response buffer
|
||||
*
|
||||
* Allocate an SCM command, including enough room for the command
|
||||
* and response headers as well as the command and response buffers.
|
||||
*
|
||||
* Returns a valid &qcom_scm_command on success or %NULL if the allocation fails.
|
||||
*/
|
||||
static struct qcom_scm_command *alloc_qcom_scm_command(size_t cmd_size, size_t resp_size)
|
||||
{
|
||||
struct qcom_scm_command *cmd;
|
||||
size_t len = sizeof(*cmd) + sizeof(struct qcom_scm_response) + cmd_size +
|
||||
resp_size;
|
||||
u32 offset;
|
||||
|
||||
cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
|
||||
if (cmd) {
|
||||
cmd->len = cpu_to_le32(len);
|
||||
offset = offsetof(struct qcom_scm_command, buf);
|
||||
cmd->buf_offset = cpu_to_le32(offset);
|
||||
cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
|
||||
}
|
||||
return cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* free_qcom_scm_command() - Free an SCM command
|
||||
* @cmd: command to free
|
||||
*
|
||||
* Free an SCM command.
|
||||
*/
|
||||
static inline void free_qcom_scm_command(struct qcom_scm_command *cmd)
|
||||
{
|
||||
kfree(cmd);
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response
|
||||
* @cmd: command
|
||||
*
|
||||
* Returns a pointer to a response for a command.
|
||||
*/
|
||||
static inline struct qcom_scm_response *qcom_scm_command_to_response(
|
||||
const struct qcom_scm_command *cmd)
|
||||
{
|
||||
return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_get_command_buffer() - Get a pointer to a command buffer
|
||||
* @cmd: command
|
||||
*
|
||||
* Returns a pointer to the command buffer of a command.
|
||||
*/
|
||||
static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd)
|
||||
{
|
||||
return (void *)cmd->buf;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_get_response_buffer() - Get a pointer to a response buffer
|
||||
* @rsp: response
|
||||
*
|
||||
* Returns a pointer to a response buffer of a response.
|
||||
*/
|
||||
static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp)
|
||||
{
|
||||
return (void *)rsp + le32_to_cpu(rsp->buf_offset);
|
||||
}
|
||||
|
||||
static int qcom_scm_remap_error(int err)
|
||||
{
|
||||
pr_err("qcom_scm_call failed with error code %d\n", err);
|
||||
switch (err) {
|
||||
case QCOM_SCM_ERROR:
|
||||
return -EIO;
|
||||
case QCOM_SCM_EINVAL_ADDR:
|
||||
case QCOM_SCM_EINVAL_ARG:
|
||||
return -EINVAL;
|
||||
case QCOM_SCM_EOPNOTSUPP:
|
||||
return -EOPNOTSUPP;
|
||||
case QCOM_SCM_ENOMEM:
|
||||
return -ENOMEM;
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static u32 smc(u32 cmd_addr)
|
||||
{
|
||||
int context_id;
|
||||
register u32 r0 asm("r0") = 1;
|
||||
register u32 r1 asm("r1") = (u32)&context_id;
|
||||
register u32 r2 asm("r2") = cmd_addr;
|
||||
do {
|
||||
asm volatile(
|
||||
__asmeq("%0", "r0")
|
||||
__asmeq("%1", "r0")
|
||||
__asmeq("%2", "r1")
|
||||
__asmeq("%3", "r2")
|
||||
#ifdef REQUIRES_SEC
|
||||
".arch_extension sec\n"
|
||||
#endif
|
||||
"smc #0 @ switch to secure world\n"
|
||||
: "=r" (r0)
|
||||
: "r" (r0), "r" (r1), "r" (r2)
|
||||
: "r3");
|
||||
} while (r0 == QCOM_SCM_INTERRUPTED);
|
||||
|
||||
return r0;
|
||||
}
|
||||
|
||||
static int __qcom_scm_call(const struct qcom_scm_command *cmd)
|
||||
{
|
||||
int ret;
|
||||
u32 cmd_addr = virt_to_phys(cmd);
|
||||
|
||||
/*
|
||||
* Flush the command buffer so that the secure world sees
|
||||
* the correct data.
|
||||
*/
|
||||
__cpuc_flush_dcache_area((void *)cmd, cmd->len);
|
||||
outer_flush_range(cmd_addr, cmd_addr + cmd->len);
|
||||
|
||||
ret = smc(cmd_addr);
|
||||
if (ret < 0)
|
||||
ret = qcom_scm_remap_error(ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void qcom_scm_inv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
u32 cacheline_size, ctr;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
|
||||
cacheline_size = 4 << ((ctr >> 16) & 0xf);
|
||||
|
||||
start = round_down(start, cacheline_size);
|
||||
end = round_up(end, cacheline_size);
|
||||
outer_inv_range(start, end);
|
||||
while (start < end) {
|
||||
asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
|
||||
: "memory");
|
||||
start += cacheline_size;
|
||||
}
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_call() - Send an SCM command
|
||||
* @svc_id: service identifier
|
||||
* @cmd_id: command identifier
|
||||
* @cmd_buf: command buffer
|
||||
* @cmd_len: length of the command buffer
|
||||
* @resp_buf: response buffer
|
||||
* @resp_len: length of the response buffer
|
||||
*
|
||||
* Sends a command to the SCM and waits for the command to finish processing.
|
||||
*
|
||||
* A note on cache maintenance:
|
||||
* Note that any buffers that are expected to be accessed by the secure world
|
||||
* must be flushed before invoking qcom_scm_call and invalidated in the cache
|
||||
* immediately after qcom_scm_call returns. Cache maintenance on the command
|
||||
* and response buffers is taken care of by qcom_scm_call; however, callers are
|
||||
* responsible for any other cached buffers passed over to the secure world.
|
||||
*/
|
||||
static int qcom_scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf,
|
||||
size_t cmd_len, void *resp_buf, size_t resp_len)
|
||||
{
|
||||
int ret;
|
||||
struct qcom_scm_command *cmd;
|
||||
struct qcom_scm_response *rsp;
|
||||
unsigned long start, end;
|
||||
|
||||
cmd = alloc_qcom_scm_command(cmd_len, resp_len);
|
||||
if (!cmd)
|
||||
return -ENOMEM;
|
||||
|
||||
cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
|
||||
if (cmd_buf)
|
||||
memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len);
|
||||
|
||||
mutex_lock(&qcom_scm_lock);
|
||||
ret = __qcom_scm_call(cmd);
|
||||
mutex_unlock(&qcom_scm_lock);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
rsp = qcom_scm_command_to_response(cmd);
|
||||
start = (unsigned long)rsp;
|
||||
|
||||
do {
|
||||
qcom_scm_inv_range(start, start + sizeof(*rsp));
|
||||
} while (!rsp->is_complete);
|
||||
|
||||
end = (unsigned long)qcom_scm_get_response_buffer(rsp) + resp_len;
|
||||
qcom_scm_inv_range(start, end);
|
||||
|
||||
if (resp_buf)
|
||||
memcpy(resp_buf, qcom_scm_get_response_buffer(rsp), resp_len);
|
||||
out:
|
||||
free_qcom_scm_command(cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define SCM_CLASS_REGISTER (0x2 << 8)
|
||||
#define SCM_MASK_IRQS BIT(5)
|
||||
#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
|
||||
SCM_CLASS_REGISTER | \
|
||||
SCM_MASK_IRQS | \
|
||||
(n & 0xf))
|
||||
|
||||
/**
|
||||
* qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
|
||||
* @svc_id: service identifier
|
||||
* @cmd_id: command identifier
|
||||
* @arg1: first argument
|
||||
*
|
||||
* This shall only be used with commands that are guaranteed to be
|
||||
* uninterruptable, atomic and SMP safe.
|
||||
*/
|
||||
static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
|
||||
{
|
||||
int context_id;
|
||||
|
||||
register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
|
||||
register u32 r1 asm("r1") = (u32)&context_id;
|
||||
register u32 r2 asm("r2") = arg1;
|
||||
|
||||
asm volatile(
|
||||
__asmeq("%0", "r0")
|
||||
__asmeq("%1", "r0")
|
||||
__asmeq("%2", "r1")
|
||||
__asmeq("%3", "r2")
|
||||
#ifdef REQUIRES_SEC
|
||||
".arch_extension sec\n"
|
||||
#endif
|
||||
"smc #0 @ switch to secure world\n"
|
||||
: "=r" (r0)
|
||||
: "r" (r0), "r" (r1), "r" (r2)
|
||||
: "r3");
|
||||
return r0;
|
||||
}
|
||||
|
||||
u32 qcom_scm_get_version(void)
|
||||
{
|
||||
int context_id;
|
||||
static u32 version = -1;
|
||||
register u32 r0 asm("r0");
|
||||
register u32 r1 asm("r1");
|
||||
|
||||
if (version != -1)
|
||||
return version;
|
||||
|
||||
mutex_lock(&qcom_scm_lock);
|
||||
|
||||
r0 = 0x1 << 8;
|
||||
r1 = (u32)&context_id;
|
||||
do {
|
||||
asm volatile(
|
||||
__asmeq("%0", "r0")
|
||||
__asmeq("%1", "r1")
|
||||
__asmeq("%2", "r0")
|
||||
__asmeq("%3", "r1")
|
||||
#ifdef REQUIRES_SEC
|
||||
".arch_extension sec\n"
|
||||
#endif
|
||||
"smc #0 @ switch to secure world\n"
|
||||
: "=r" (r0), "=r" (r1)
|
||||
: "r" (r0), "r" (r1)
|
||||
: "r2", "r3");
|
||||
} while (r0 == QCOM_SCM_INTERRUPTED);
|
||||
|
||||
version = r1;
|
||||
mutex_unlock(&qcom_scm_lock);
|
||||
|
||||
return version;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_get_version);
|
||||
|
||||
#define QCOM_SCM_SVC_BOOT 0x1
|
||||
#define QCOM_SCM_BOOT_ADDR 0x1
|
||||
/*
|
||||
* Set the cold/warm boot address for one of the CPU cores.
|
||||
*/
|
||||
static int qcom_scm_set_boot_addr(u32 addr, int flags)
|
||||
{
|
||||
struct {
|
||||
__le32 flags;
|
||||
__le32 addr;
|
||||
} cmd;
|
||||
|
||||
cmd.addr = cpu_to_le32(addr);
|
||||
cmd.flags = cpu_to_le32(flags);
|
||||
return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
|
||||
&cmd, sizeof(cmd), NULL, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
|
||||
* @entry: Entry point function for the cpus
|
||||
* @cpus: The cpumask of cpus that will use the entry point
|
||||
*
|
||||
* Set the cold boot address of the cpus. Any cpu outside the supported
|
||||
* range would be removed from the cpu present mask.
|
||||
*/
|
||||
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
int flags = 0;
|
||||
int cpu;
|
||||
int scm_cb_flags[] = {
|
||||
QCOM_SCM_FLAG_COLDBOOT_CPU0,
|
||||
QCOM_SCM_FLAG_COLDBOOT_CPU1,
|
||||
QCOM_SCM_FLAG_COLDBOOT_CPU2,
|
||||
QCOM_SCM_FLAG_COLDBOOT_CPU3,
|
||||
};
|
||||
|
||||
if (!cpus || (cpus && cpumask_empty(cpus)))
|
||||
return -EINVAL;
|
||||
|
||||
for_each_cpu(cpu, cpus) {
|
||||
if (cpu < ARRAY_SIZE(scm_cb_flags))
|
||||
flags |= scm_cb_flags[cpu];
|
||||
else
|
||||
set_cpu_present(cpu, false);
|
||||
}
|
||||
|
||||
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
|
||||
|
||||
/**
|
||||
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
|
||||
* @entry: Entry point function for the cpus
|
||||
* @cpus: The cpumask of cpus that will use the entry point
|
||||
*
|
||||
* Set the Linux entry point for the SCM to transfer control to when coming
|
||||
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
|
||||
*/
|
||||
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
int ret;
|
||||
int flags = 0;
|
||||
int cpu;
|
||||
|
||||
/*
|
||||
* Reassign only if we are switching from hotplug entry point
|
||||
* to cpuidle entry point or vice versa.
|
||||
*/
|
||||
for_each_cpu(cpu, cpus) {
|
||||
if (entry == qcom_scm_wb[cpu].entry)
|
||||
continue;
|
||||
flags |= qcom_scm_wb[cpu].flag;
|
||||
}
|
||||
|
||||
/* No change in entry function */
|
||||
if (!flags)
|
||||
return 0;
|
||||
|
||||
ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
|
||||
if (!ret) {
|
||||
for_each_cpu(cpu, cpus)
|
||||
qcom_scm_wb[cpu].entry = entry;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
|
||||
|
||||
#define QCOM_SCM_CMD_TERMINATE_PC 0x2
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
|
||||
/**
|
||||
* qcom_scm_cpu_power_down() - Power down the cpu
|
||||
* @flags - Flags to flush cache
|
||||
*
|
||||
* This is an end point to power down cpu. If there was a pending interrupt,
|
||||
* the control would return from this function, otherwise, the cpu jumps to the
|
||||
* warm boot entry point set for this cpu upon reset.
|
||||
*/
|
||||
void qcom_scm_cpu_power_down(u32 flags)
|
||||
{
|
||||
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
|
||||
flags & QCOM_SCM_FLUSH_FLAG_MASK);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
|
||||
|
|
@ -4,6 +4,7 @@
|
|||
config QCOM_GSBI
|
||||
tristate "QCOM General Serial Bus Interface"
|
||||
depends on ARCH_QCOM
|
||||
select MFD_SYSCON
|
||||
help
|
||||
Say y here to enable GSBI support. The GSBI provides control
|
||||
functions for connecting the underlying serial UART, SPI, and I2C
|
||||
|
|
|
|||
|
|
@ -18,22 +18,129 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
|
||||
#define GSBI_CTRL_REG 0x0000
|
||||
#define GSBI_PROTOCOL_SHIFT 4
|
||||
#define MAX_GSBI 12
|
||||
|
||||
#define TCSR_ADM_CRCI_BASE 0x70
|
||||
|
||||
struct crci_config {
|
||||
u32 num_rows;
|
||||
const u32 (*array)[MAX_GSBI];
|
||||
};
|
||||
|
||||
static const u32 crci_ipq8064[][MAX_GSBI] = {
|
||||
{
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000c00, 0x003000, 0x00c000,
|
||||
0x030000, 0x0c0000, 0x300000, 0xc00000
|
||||
},
|
||||
{
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000c00, 0x003000, 0x00c000,
|
||||
0x030000, 0x0c0000, 0x300000, 0xc00000
|
||||
},
|
||||
};
|
||||
|
||||
static const struct crci_config config_ipq8064 = {
|
||||
.num_rows = ARRAY_SIZE(crci_ipq8064),
|
||||
.array = crci_ipq8064,
|
||||
};
|
||||
|
||||
static const unsigned int crci_apq8064[][MAX_GSBI] = {
|
||||
{
|
||||
0x001800, 0x006000, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000400, 0x000000, 0x000000,
|
||||
0x000000, 0x000000, 0x000000, 0x000000
|
||||
},
|
||||
{
|
||||
0x000000, 0x000000, 0x000000, 0x000000,
|
||||
0x000000, 0x000020, 0x0000c0, 0x000000,
|
||||
0x000000, 0x000000, 0x000000, 0x000000
|
||||
},
|
||||
};
|
||||
|
||||
static const struct crci_config config_apq8064 = {
|
||||
.num_rows = ARRAY_SIZE(crci_apq8064),
|
||||
.array = crci_apq8064,
|
||||
};
|
||||
|
||||
static const unsigned int crci_msm8960[][MAX_GSBI] = {
|
||||
{
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000400, 0x000000, 0x000000,
|
||||
0x000000, 0x000000, 0x000000, 0x000000
|
||||
},
|
||||
{
|
||||
0x000000, 0x000000, 0x000000, 0x000000,
|
||||
0x000000, 0x000020, 0x0000c0, 0x000300,
|
||||
0x001800, 0x006000, 0x000000, 0x000000
|
||||
},
|
||||
};
|
||||
|
||||
static const struct crci_config config_msm8960 = {
|
||||
.num_rows = ARRAY_SIZE(crci_msm8960),
|
||||
.array = crci_msm8960,
|
||||
};
|
||||
|
||||
static const unsigned int crci_msm8660[][MAX_GSBI] = {
|
||||
{ /* ADM 0 - B */
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000c00, 0x003000, 0x00c000,
|
||||
0x030000, 0x0c0000, 0x300000, 0xc00000
|
||||
},
|
||||
{ /* ADM 0 - B */
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000c00, 0x003000, 0x00c000,
|
||||
0x030000, 0x0c0000, 0x300000, 0xc00000
|
||||
},
|
||||
{ /* ADM 1 - A */
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000c00, 0x003000, 0x00c000,
|
||||
0x030000, 0x0c0000, 0x300000, 0xc00000
|
||||
},
|
||||
{ /* ADM 1 - B */
|
||||
0x000003, 0x00000c, 0x000030, 0x0000c0,
|
||||
0x000300, 0x000c00, 0x003000, 0x00c000,
|
||||
0x030000, 0x0c0000, 0x300000, 0xc00000
|
||||
},
|
||||
};
|
||||
|
||||
static const struct crci_config config_msm8660 = {
|
||||
.num_rows = ARRAY_SIZE(crci_msm8660),
|
||||
.array = crci_msm8660,
|
||||
};
|
||||
|
||||
struct gsbi_info {
|
||||
struct clk *hclk;
|
||||
u32 mode;
|
||||
u32 crci;
|
||||
struct regmap *tcsr;
|
||||
};
|
||||
|
||||
static const struct of_device_id tcsr_dt_match[] = {
|
||||
{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
|
||||
{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
|
||||
{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
|
||||
{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
|
||||
{ },
|
||||
};
|
||||
|
||||
static int gsbi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device_node *tcsr_node;
|
||||
const struct of_device_id *match;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
struct gsbi_info *gsbi;
|
||||
int i;
|
||||
u32 mask, gsbi_num;
|
||||
const struct crci_config *config = NULL;
|
||||
|
||||
gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
|
||||
|
||||
|
|
@ -45,6 +152,32 @@ static int gsbi_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
/* get the tcsr node and setup the config and regmap */
|
||||
gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
|
||||
|
||||
if (!IS_ERR(gsbi->tcsr)) {
|
||||
tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
|
||||
if (tcsr_node) {
|
||||
match = of_match_node(tcsr_dt_match, tcsr_node);
|
||||
if (match)
|
||||
config = match->data;
|
||||
else
|
||||
dev_warn(&pdev->dev, "no matching TCSR\n");
|
||||
|
||||
of_node_put(tcsr_node);
|
||||
}
|
||||
}
|
||||
|
||||
if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
|
||||
dev_err(&pdev->dev, "missing cell-index\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
|
||||
dev_err(&pdev->dev, "invalid cell-index\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
|
||||
dev_err(&pdev->dev, "missing mode configuration\n");
|
||||
return -EINVAL;
|
||||
|
|
@ -64,6 +197,25 @@ static int gsbi_probe(struct platform_device *pdev)
|
|||
writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
|
||||
base + GSBI_CTRL_REG);
|
||||
|
||||
/*
|
||||
* modify tcsr to reflect mode and ADM CRCI mux
|
||||
* Each gsbi contains a pair of bits, one for RX and one for TX
|
||||
* SPI mode requires both bits cleared, otherwise they are set
|
||||
*/
|
||||
if (config) {
|
||||
for (i = 0; i < config->num_rows; i++) {
|
||||
mask = config->array[i][gsbi_num - 1];
|
||||
|
||||
if (gsbi->mode == GSBI_PROT_SPI)
|
||||
regmap_update_bits(gsbi->tcsr,
|
||||
TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
|
||||
else
|
||||
regmap_update_bits(gsbi->tcsr,
|
||||
TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure the gsbi control write is not reordered */
|
||||
wmb();
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2015 Linaro Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __QCOM_SCM_H
|
||||
#define __QCOM_SCM_H
|
||||
|
||||
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
|
||||
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
|
||||
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
|
||||
|
||||
extern void qcom_scm_cpu_power_down(u32 flags);
|
||||
|
||||
#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
|
||||
|
||||
extern u32 qcom_scm_get_version(void);
|
||||
|
||||
#endif
|
||||
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