cmd64x: fix multiword and remove single-word DMA support
Fix the multiword DMA and drop the single-word DMA support (which nobody will
miss, I think). In order to do it, a number of changes was necessary:
- rename program_drive_counts() to program_cycle_times(), pass to it cycle's
total/active times instead of the clock counts, and convert them into the
active/recovery clocks there instead of cmd64x_tune_pio() -- this causes
quantize_timing() to also move;
- contrarywise, move all the code handling the address setup timing into
cmd64x_tune_pio(), so that setting MWDMA mode wouldn't change address setup;
- remove from the speedproc() method the bogus code pretending to set the DMA
timings by twiddling bits in the BMIDE status register, handle setting MWDMA
by just calling program_cycle_times(); while at it, improve the style of that
whole switch statement;
- stop fiddling with the DMA capable bits in the speedproc() method -- they do
not enable DMA, and are properly dealt with by the dma_host_{on,off} methods;
- don't set hwif->swdma_mask in the init_hwif() method anymore.
In addition to those changes, do the following:
- in cmd64x_tune_pio(), when writing to ARTTIM23 register preserve the interrupt
status bit, eliminate local_irq_{save|restore}() around this code as there's
*no* actual race with the interrupt handler, and move cmdprintk() to a more
fitting place -- after ide_get_best_pio_mode() call;
- make {arttim|drwtim}_regs arrays single-dimensional, indexed with drive->dn;
- rename {setup|recovery}_counts[] into more fitting {setup|recovery}_values[];
- in the speedproc() method, get rid of the duplicate reads/writes from/to the
UDIDETCRx registers and of the extra variable used to store the transfer mode
value after filtering, use another method of determining master/slave drive,
and cleanup useless parens;
- beautify cmdprintk() output here and there.
While at it, remove meaningless comment about the driver being used only on
UltraSPARC and long non-relevant RCS tag. :-)
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
Родитель
688a87d145
Коммит
60e7a82f1a
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@ -1,10 +1,7 @@
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/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
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*
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* linux/drivers/ide/pci/cmd64x.c Version 1.42 Feb 8, 2007
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/*
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* linux/drivers/ide/pci/cmd64x.c Version 1.43 Mar 10, 2007
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*
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* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
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* Note, this driver is not used at all on other systems because
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* there the "BIOS" has done all of the following already.
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* Due to massive hardware bugs, UltraDMA is only supported
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* on the 646U2 and not on the 646U.
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*
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@ -195,116 +192,103 @@ static u8 quantize_timing(int timing, int quant)
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}
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/*
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* This routine writes the prepared setup/active/recovery counts
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* for a drive into the cmd646 chipset registers to active them.
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* This routine calculates active/recovery counts and then writes them into
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* the chipset registers.
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*/
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static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
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static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
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{
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unsigned long flags;
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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ide_drive_t *drives = HWIF(drive)->drives;
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u8 temp_b;
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static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
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static const u8 recovery_counts[] =
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int clock_time = 1000 / system_bus_clock();
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u8 cycle_count, active_count, recovery_count, drwtim;
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static const u8 recovery_values[] =
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{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
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static const u8 arttim_regs[2][2] = {
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{ ARTTIM0, ARTTIM1 },
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{ ARTTIM23, ARTTIM23 }
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};
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static const u8 drwtim_regs[2][2] = {
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{ DRWTIM0, DRWTIM1 },
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{ DRWTIM2, DRWTIM3 }
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};
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int channel = (int) HWIF(drive)->channel;
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int slave = (drives != drive); /* Is this really the best way to determine this?? */
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static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
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cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
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setup_count, active_count, recovery_count, drive->present);
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/*
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* Set up address setup count registers.
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* Primary interface has individual count/timing registers for
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* each drive. Secondary interface has one common set of registers,
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* for address setup so we merge these timings, using the slowest
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* value.
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*/
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if (channel) {
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drive->drive_data = setup_count;
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setup_count = max(drives[0].drive_data,
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drives[1].drive_data);
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cmdprintk("Secondary interface, setup_count = %d\n",
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setup_count);
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}
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cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
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cycle_time, active_time);
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cycle_count = quantize_timing( cycle_time, clock_time);
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active_count = quantize_timing(active_time, clock_time);
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recovery_count = cycle_count - active_count;
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/*
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* Convert values to internal chipset representation
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* In case we've got too long recovery phase, try to lengthen
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* the active phase
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*/
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setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
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active_count &= 0xf; /* Remember, max value is 16 */
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recovery_count = (int) recovery_counts[recovery_count];
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cmdprintk("Final values = %d,%d,%d\n",
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setup_count, active_count, recovery_count);
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/*
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* Now that everything is ready, program the new timings
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*/
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local_irq_save(flags);
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/*
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* Program the address_setup clocks into ARTTIM reg,
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* and then the active/recovery counts into the DRWTIM reg
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*/
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(void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
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(void) pci_write_config_byte(dev, arttim_regs[channel][slave],
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((u8) setup_count) | (temp_b & 0x3f));
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(void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
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(u8) ((active_count << 4) | recovery_count));
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cmdprintk ("Write %x to %x\n",
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((u8) setup_count) | (temp_b & 0x3f),
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arttim_regs[channel][slave]);
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cmdprintk ("Write %x to %x\n",
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(u8) ((active_count << 4) | recovery_count),
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drwtim_regs[channel][slave]);
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local_irq_restore(flags);
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}
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/*
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* This routine selects drive's best PIO mode, calculates setup/active/recovery
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* counts, and then writes them into the chipset registers.
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*/
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static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
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{
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int setup_time, active_time, cycle_time;
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u8 cycle_count, setup_count, active_count, recovery_count;
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u8 pio_mode;
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int clock_time = 1000 / system_bus_clock();
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ide_pio_data_t pio;
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pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
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cycle_time = pio.cycle_time;
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setup_time = ide_pio_timings[pio_mode].setup_time;
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active_time = ide_pio_timings[pio_mode].active_time;
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setup_count = quantize_timing( setup_time, clock_time);
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cycle_count = quantize_timing( cycle_time, clock_time);
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active_count = quantize_timing(active_time, clock_time);
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recovery_count = cycle_count - active_count;
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/* program_drive_counts() takes care of zero recovery cycles */
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if (recovery_count > 16) {
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active_count += recovery_count - 16;
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recovery_count = 16;
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}
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if (active_count > 16)
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active_count = 16; /* maximum allowed by cmd64x */
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if (active_count > 16) /* shouldn't actually happen... */
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active_count = 16;
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program_drive_counts (drive, setup_count, active_count, recovery_count);
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cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
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cycle_count, active_count, recovery_count);
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cmdprintk("%s: PIO mode wanted %d, selected %d (%dns)%s, "
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"clocks=%d/%d/%d\n",
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drive->name, mode_wanted, pio_mode, cycle_time,
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pio.overridden ? " (overriding vendor mode)" : "",
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setup_count, active_count, recovery_count);
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/*
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* Convert values to internal chipset representation
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*/
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recovery_count = recovery_values[recovery_count];
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active_count &= 0x0f;
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/* Program the active/recovery counts into the DRWTIM register */
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drwtim = (active_count << 4) | recovery_count;
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(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
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cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
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}
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/*
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* This routine selects drive's best PIO mode and writes into the chipset
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* registers setup/active/recovery timings.
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*/
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static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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ide_pio_data_t pio;
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u8 pio_mode, setup_count, arttim = 0;
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static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
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static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
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pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
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cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
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drive->name, mode_wanted, pio_mode, pio.cycle_time,
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pio.overridden ? " (overriding vendor mode)" : "");
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program_cycle_times(drive, pio.cycle_time,
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ide_pio_timings[pio_mode].active_time);
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setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
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1000 / system_bus_clock());
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/*
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* The primary channel has individual address setup timing registers
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* for each drive and the hardware selects the slowest timing itself.
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* The secondary channel has one common register and we have to select
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* the slowest address setup timing ourselves.
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*/
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if (hwif->channel) {
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ide_drive_t *drives = hwif->drives;
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drive->drive_data = setup_count;
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setup_count = max(drives[0].drive_data, drives[1].drive_data);
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}
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if (setup_count > 5) /* shouldn't actually happen... */
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setup_count = 5;
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cmdprintk("Final address setup count: %d\n", setup_count);
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/*
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* Program the address setup clocks into the ARTTIM registers.
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* Avoid clearing the secondary channel's interrupt bit.
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*/
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(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
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if (hwif->channel)
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arttim &= ~ARTTIM23_INTR_CH1;
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arttim &= ~0xc0;
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arttim |= setup_values[setup_count];
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(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
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cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
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return pio_mode;
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}
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@ -376,61 +360,64 @@ static u8 cmd64x_ratemask (ide_drive_t *drive)
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return mode;
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}
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static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 unit = drive->dn & 0x01;
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u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
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u8 unit = (drive->select.b.unit & 0x01);
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u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
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u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
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u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
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speed = ide_rate_filter(cmd64x_ratemask(drive), speed);
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if (speed >= XFER_SW_DMA_0) {
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(void) pci_read_config_byte(dev, pciD, ®D);
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(void) pci_read_config_byte(dev, pciU, ®U);
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regD &= ~(unit ? 0x40 : 0x20);
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regU &= ~(unit ? 0xCA : 0x35);
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(void) pci_write_config_byte(dev, pciD, regD);
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(void) pci_write_config_byte(dev, pciU, regU);
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(void) pci_read_config_byte(dev, pciD, ®D);
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(void) pci_read_config_byte(dev, pciU, ®U);
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}
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switch(speed) {
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case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
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case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
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case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
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case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
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case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
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case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
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case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
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case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
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case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
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case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
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case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
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case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
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case XFER_PIO_5:
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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(void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
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break;
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default:
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return 1;
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case XFER_UDMA_5:
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regU |= unit ? 0x0A : 0x05;
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break;
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case XFER_UDMA_4:
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regU |= unit ? 0x4A : 0x15;
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break;
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case XFER_UDMA_3:
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regU |= unit ? 0x8A : 0x25;
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break;
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case XFER_UDMA_2:
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regU |= unit ? 0x42 : 0x11;
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break;
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case XFER_UDMA_1:
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regU |= unit ? 0x82 : 0x21;
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break;
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case XFER_UDMA_0:
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regU |= unit ? 0xC2 : 0x31;
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break;
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case XFER_MW_DMA_2:
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program_cycle_times(drive, 120, 70);
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break;
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case XFER_MW_DMA_1:
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program_cycle_times(drive, 150, 80);
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break;
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case XFER_MW_DMA_0:
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program_cycle_times(drive, 480, 215);
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break;
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case XFER_PIO_5:
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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(void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
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break;
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default:
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return 1;
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}
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if (speed >= XFER_SW_DMA_0) {
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if (speed >= XFER_SW_DMA_0)
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(void) pci_write_config_byte(dev, pciU, regU);
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regD |= (unit ? 0x40 : 0x20);
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(void) pci_write_config_byte(dev, pciD, regD);
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}
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return (ide_config_drive_speed(drive, speed));
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return ide_config_drive_speed(drive, speed);
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}
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static int config_chipset_for_dma (ide_drive_t *drive)
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@ -665,7 +652,6 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
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hwif->ultra_mask = 0x3f;
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hwif->mwdma_mask = 0x07;
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hwif->swdma_mask = 0x07;
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if (dev->device == PCI_DEVICE_ID_CMD_643)
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hwif->ultra_mask = 0x80;
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