net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii
RGMII mode can be enable from dp83822 straps, and also writing bit 9 of register 0x17 - RMII and Status Register (RCSR). When phy_interface_is_rgmii rgmii mode must be enabled, same for contrary, this prevents malconfigurations of hw straps References: - https://www.ti.com/lit/gpn/dp83822i p66 Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com> Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -94,7 +94,8 @@
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#define DP83822_WOL_INDICATION_SEL BIT(8)
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#define DP83822_WOL_INDICATION_SEL BIT(8)
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#define DP83822_WOL_CLR_INDICATION BIT(11)
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#define DP83822_WOL_CLR_INDICATION BIT(11)
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/* RSCR bits */
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/* RCSR bits */
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#define DP83822_RGMII_MODE_EN BIT(9)
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#define DP83822_RX_CLK_SHIFT BIT(12)
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#define DP83822_RX_CLK_SHIFT BIT(12)
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#define DP83822_TX_CLK_SHIFT BIT(11)
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#define DP83822_TX_CLK_SHIFT BIT(11)
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@ -408,6 +409,12 @@ static int dp83822_config_init(struct phy_device *phydev)
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if (err)
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if (err)
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return err;
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return err;
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}
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}
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phy_set_bits_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
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} else {
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phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
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MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
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}
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}
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if (dp83822->fx_enabled) {
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if (dp83822->fx_enabled) {
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