[POWERPC] 8xx: Add pin and clock setting functions.
These let board code set up pins and clocks without having to put magic numbers directly into the registers. The clock function is mostly duplicated from the cpm2 version; hopefully this stuff can be merged at some point. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Scott Wood
Kumar Gala
Родитель
fb533d0c5a
Коммит
663edbd264
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@ -397,3 +397,204 @@ uint cpm_dpram_phys(u8 *addr)
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return (dpram_pbase + (uint)(addr - dpram_vbase));
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}
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EXPORT_SYMBOL(cpm_dpram_phys);
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struct cpm_ioport16 {
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__be16 dir, par, sor, dat, intr;
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__be16 res[3];
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};
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struct cpm_ioport32 {
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__be32 dir, par, sor;
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};
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static void cpm1_set_pin32(int port, int pin, int flags)
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{
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struct cpm_ioport32 __iomem *iop;
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pin = 1 << (31 - pin);
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if (port == CPM_PORTB)
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iop = (struct cpm_ioport32 __iomem *)
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&mpc8xx_immr->im_cpm.cp_pbdir;
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else
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iop = (struct cpm_ioport32 __iomem *)
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&mpc8xx_immr->im_cpm.cp_pedir;
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if (flags & CPM_PIN_OUTPUT)
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setbits32(&iop->dir, pin);
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else
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clrbits32(&iop->dir, pin);
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if (!(flags & CPM_PIN_GPIO))
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setbits32(&iop->par, pin);
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else
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clrbits32(&iop->par, pin);
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if (port == CPM_PORTE) {
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if (flags & CPM_PIN_SECONDARY)
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setbits32(&iop->sor, pin);
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else
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clrbits32(&iop->sor, pin);
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if (flags & CPM_PIN_OPENDRAIN)
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setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
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else
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clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
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}
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}
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static void cpm1_set_pin16(int port, int pin, int flags)
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{
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struct cpm_ioport16 __iomem *iop =
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(struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
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pin = 1 << (15 - pin);
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if (port != 0)
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iop += port - 1;
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if (flags & CPM_PIN_OUTPUT)
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setbits16(&iop->dir, pin);
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else
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clrbits16(&iop->dir, pin);
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if (!(flags & CPM_PIN_GPIO))
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setbits16(&iop->par, pin);
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else
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clrbits16(&iop->par, pin);
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if (port == CPM_PORTC) {
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if (flags & CPM_PIN_SECONDARY)
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setbits16(&iop->sor, pin);
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else
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clrbits16(&iop->sor, pin);
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}
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}
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void cpm1_set_pin(enum cpm_port port, int pin, int flags)
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{
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if (port == CPM_PORTB || port == CPM_PORTE)
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cpm1_set_pin32(port, pin, flags);
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else
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cpm1_set_pin16(port, pin, flags);
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}
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int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
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{
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int shift;
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int i, bits = 0;
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u32 __iomem *reg;
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u32 mask = 7;
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u8 clk_map[][3] = {
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{CPM_CLK_SCC1, CPM_BRG1, 0},
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{CPM_CLK_SCC1, CPM_BRG2, 1},
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{CPM_CLK_SCC1, CPM_BRG3, 2},
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{CPM_CLK_SCC1, CPM_BRG4, 3},
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{CPM_CLK_SCC1, CPM_CLK1, 4},
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{CPM_CLK_SCC1, CPM_CLK2, 5},
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{CPM_CLK_SCC1, CPM_CLK3, 6},
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{CPM_CLK_SCC1, CPM_CLK4, 7},
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{CPM_CLK_SCC2, CPM_BRG1, 0},
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{CPM_CLK_SCC2, CPM_BRG2, 1},
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{CPM_CLK_SCC2, CPM_BRG3, 2},
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{CPM_CLK_SCC2, CPM_BRG4, 3},
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{CPM_CLK_SCC2, CPM_CLK1, 4},
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{CPM_CLK_SCC2, CPM_CLK2, 5},
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{CPM_CLK_SCC2, CPM_CLK3, 6},
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{CPM_CLK_SCC2, CPM_CLK4, 7},
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{CPM_CLK_SCC3, CPM_BRG1, 0},
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{CPM_CLK_SCC3, CPM_BRG2, 1},
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{CPM_CLK_SCC3, CPM_BRG3, 2},
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{CPM_CLK_SCC3, CPM_BRG4, 3},
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{CPM_CLK_SCC3, CPM_CLK5, 4},
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{CPM_CLK_SCC3, CPM_CLK6, 5},
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{CPM_CLK_SCC3, CPM_CLK7, 6},
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{CPM_CLK_SCC3, CPM_CLK8, 7},
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{CPM_CLK_SCC4, CPM_BRG1, 0},
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{CPM_CLK_SCC4, CPM_BRG2, 1},
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{CPM_CLK_SCC4, CPM_BRG3, 2},
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{CPM_CLK_SCC4, CPM_BRG4, 3},
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{CPM_CLK_SCC4, CPM_CLK5, 4},
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{CPM_CLK_SCC4, CPM_CLK6, 5},
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{CPM_CLK_SCC4, CPM_CLK7, 6},
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{CPM_CLK_SCC4, CPM_CLK8, 7},
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{CPM_CLK_SMC1, CPM_BRG1, 0},
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{CPM_CLK_SMC1, CPM_BRG2, 1},
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{CPM_CLK_SMC1, CPM_BRG3, 2},
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{CPM_CLK_SMC1, CPM_BRG4, 3},
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{CPM_CLK_SMC1, CPM_CLK1, 4},
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{CPM_CLK_SMC1, CPM_CLK2, 5},
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{CPM_CLK_SMC1, CPM_CLK3, 6},
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{CPM_CLK_SMC1, CPM_CLK4, 7},
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{CPM_CLK_SMC2, CPM_BRG1, 0},
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{CPM_CLK_SMC2, CPM_BRG2, 1},
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{CPM_CLK_SMC2, CPM_BRG3, 2},
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{CPM_CLK_SMC2, CPM_BRG4, 3},
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{CPM_CLK_SMC2, CPM_CLK5, 4},
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{CPM_CLK_SMC2, CPM_CLK6, 5},
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{CPM_CLK_SMC2, CPM_CLK7, 6},
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{CPM_CLK_SMC2, CPM_CLK8, 7},
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};
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switch (target) {
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case CPM_CLK_SCC1:
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reg = &mpc8xx_immr->im_cpm.cp_sicr;
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shift = 0;
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break;
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case CPM_CLK_SCC2:
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reg = &mpc8xx_immr->im_cpm.cp_sicr;
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shift = 8;
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break;
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case CPM_CLK_SCC3:
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reg = &mpc8xx_immr->im_cpm.cp_sicr;
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shift = 16;
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break;
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case CPM_CLK_SCC4:
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reg = &mpc8xx_immr->im_cpm.cp_sicr;
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shift = 24;
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break;
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case CPM_CLK_SMC1:
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reg = &mpc8xx_immr->im_cpm.cp_simode;
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shift = 12;
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break;
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case CPM_CLK_SMC2:
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reg = &mpc8xx_immr->im_cpm.cp_simode;
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shift = 28;
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break;
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default:
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printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
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return -EINVAL;
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}
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if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
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shift += 3;
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for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
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if (clk_map[i][0] == target && clk_map[i][1] == clock) {
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bits = clk_map[i][2];
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break;
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}
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}
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if (i == ARRAY_SIZE(clk_map)) {
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printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
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return -EINVAL;
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}
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bits <<= shift;
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mask <<= shift;
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out_be32(reg, (in_be32(reg) & ~mask) | bits);
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return 0;
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}
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@ -691,4 +691,53 @@ extern void cpm_free_handler(int vec);
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#define IMAP_ADDR (get_immrbase())
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#define CPM_PIN_INPUT 0
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#define CPM_PIN_OUTPUT 1
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#define CPM_PIN_PRIMARY 0
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#define CPM_PIN_SECONDARY 2
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#define CPM_PIN_GPIO 4
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#define CPM_PIN_OPENDRAIN 8
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enum cpm_port {
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CPM_PORTA,
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CPM_PORTB,
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CPM_PORTC,
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CPM_PORTD,
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CPM_PORTE,
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};
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void cpm1_set_pin(enum cpm_port port, int pin, int flags);
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enum cpm_clk_dir {
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CPM_CLK_RX,
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CPM_CLK_TX,
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CPM_CLK_RTX
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};
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enum cpm_clk_target {
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CPM_CLK_SCC1,
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CPM_CLK_SCC2,
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CPM_CLK_SCC3,
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CPM_CLK_SCC4,
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CPM_CLK_SMC1,
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CPM_CLK_SMC2,
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};
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enum cpm_clk {
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CPM_BRG1, /* Baud Rate Generator 1 */
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CPM_BRG2, /* Baud Rate Generator 2 */
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CPM_BRG3, /* Baud Rate Generator 3 */
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CPM_BRG4, /* Baud Rate Generator 4 */
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CPM_CLK1, /* Clock 1 */
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CPM_CLK2, /* Clock 2 */
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CPM_CLK3, /* Clock 3 */
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CPM_CLK4, /* Clock 4 */
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CPM_CLK5, /* Clock 5 */
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CPM_CLK6, /* Clock 6 */
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CPM_CLK7, /* Clock 7 */
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CPM_CLK8, /* Clock 8 */
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};
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int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
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#endif /* __CPM_8XX__ */
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