drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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124764f174
Коммит
72a9987edc
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@ -3890,8 +3890,6 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, 0);
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/* HDP flush */
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cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
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}
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/**
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@ -3920,8 +3918,6 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(ring, upper_32_bits(addr));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, 0);
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/* HDP flush */
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cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
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}
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bool cik_semaphore_ring_emit(struct radeon_device *rdev,
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@ -837,11 +837,7 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
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/* Wait until IDLE & CLEAN */
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radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
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radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
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radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
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RADEON_HDP_READ_BUFFER_INVALIDATE);
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radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
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r100_ring_hdp_flush(rdev, ring);
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/* Emit fence sequence & fire IRQ */
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radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
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radeon_ring_write(ring, fence->seq);
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@ -1060,6 +1056,20 @@ void r100_gfx_set_wptr(struct radeon_device *rdev,
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(void)RREG32(RADEON_CP_RB_WPTR);
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}
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/**
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* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
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* rdev: radeon device structure
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* ring: ring buffer struct for emitting packets
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*/
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void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
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RADEON_HDP_READ_BUFFER_INVALIDATE);
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radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
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}
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static void r100_cp_load_microcode(struct radeon_device *rdev)
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{
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const __be32 *fw_data;
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@ -1749,6 +1749,7 @@ struct radeon_asic_ring {
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/* command emmit functions */
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void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
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void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
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void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
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bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
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struct radeon_semaphore *semaphore, bool emit_wait);
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void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
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@ -185,6 +185,7 @@ static struct radeon_asic_ring r100_gfx_ring = {
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.get_rptr = &r100_gfx_get_rptr,
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.get_wptr = &r100_gfx_get_wptr,
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.set_wptr = &r100_gfx_set_wptr,
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.hdp_flush = &r100_ring_hdp_flush,
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};
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static struct radeon_asic r100_asic = {
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@ -331,6 +332,7 @@ static struct radeon_asic_ring r300_gfx_ring = {
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.get_rptr = &r100_gfx_get_rptr,
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.get_wptr = &r100_gfx_get_wptr,
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.set_wptr = &r100_gfx_set_wptr,
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.hdp_flush = &r100_ring_hdp_flush,
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};
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static struct radeon_asic r300_asic = {
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@ -1987,7 +1989,7 @@ static struct radeon_asic ci_asic = {
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.resume = &cik_resume,
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.asic_reset = &cik_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.mmio_hdp_flush = NULL,
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.mmio_hdp_flush = &r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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@ -2091,7 +2093,7 @@ static struct radeon_asic kv_asic = {
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.resume = &cik_resume,
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.asic_reset = &cik_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.mmio_hdp_flush = NULL,
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.mmio_hdp_flush = &r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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@ -148,7 +148,8 @@ u32 r100_gfx_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void r100_gfx_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void r100_ring_hdp_flush(struct radeon_device *rdev,
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struct radeon_ring *ring);
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/*
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* r200,rv250,rs300,rv280
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*/
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@ -82,9 +82,11 @@
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* 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
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* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
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* 2.39.0 - Add INFO query for number of active CUs
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* 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
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* CS to GPU
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*/
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#define KMS_DRIVER_MAJOR 2
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#define KMS_DRIVER_MINOR 39
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#define KMS_DRIVER_MINOR 40
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#define KMS_DRIVER_PATCHLEVEL 0
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
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int radeon_driver_unload_kms(struct drm_device *dev);
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@ -183,11 +183,21 @@ int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsig
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*/
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void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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/* If we are emitting the HDP flush via the ring buffer, we need to
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* do it before padding.
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*/
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if (rdev->asic->ring[ring->idx]->hdp_flush)
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rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
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/* We pad to match fetch size */
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while (ring->wptr & ring->align_mask) {
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radeon_ring_write(ring, ring->nop);
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}
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mb();
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/* If we are emitting the HDP flush via MMIO, we need to do it after
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* all CPU writes to VRAM finished.
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*/
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if (rdev->asic->mmio_hdp_flush)
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rdev->asic->mmio_hdp_flush(rdev);
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radeon_ring_set_wptr(rdev, ring);
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}
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