ARM: SoC fixes for 6.5, part 3
As usual, mostly DT fixes for the major Arm platforms from Qualcomm and NXP, plus a bit for Rockchips and others: The qualcomm fixes mainly deal with their higher-end arm64 devices trees, fixing issues in L3 interconnect, crypto, thermal, UFS and a regression for the DSI phy. NXP i.MX has two correctness fixes for the 64-bit chips, dealing with the imx93 "anatop" module and the CSI interface. On the 32-bit side, there are functional fixes for RTC, display and SD card intefaces. Rockchip fixes are for wifi support on certain boards, a eMMC stability and DT build warnings. On TI OMAP, a regulator is described in DT to avoid problems with the ethernet phy initialization. The code changes include a missing MMIO serialization on OMAP, plus a few minor fixes on ASpeed and AMD/Zynq chips. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTe2VcACgkQYKtH/8kJ Uid+qxAAkNF+0roAULDQ9YCg8nnv9l6VN4AGu4K7PA/C8rouW8FbWmpc85xTBV9a rSm2AwdZEeHMb5S1hpdgu28MA4f3ja6IYIYSCjob4nE1mfgpVVwfxE6AXjUKApBp y6JN/jK/9W30JDLiReOFcsGNkM5Yqj80XKCBf+6/XLUfSWm90xgvXMFFte2p+AsV Qb4OInSIT06CtbkZ/DMJx9fFXPeB/lig5joLeuU7eChCXVF+GwcgRzBIueHvH4VS FbAEnprhlfDHfj4zvZAFKTXYhLDLCkWwxOHilGxauXykWhGP/4XY0qc6z1tk7y+5 r8SPRgEAX4D6D4PwvloxhTJ5WnyqIzk6cS+8WYxMiheurzDGVnoofYp+dWR5CNMj 2STXGzX7ZFkxIRZ3M7d8qz7GpzHsTnmQfg8SH4NiYsg/NptyfPLqdRPjYt1vhu+i zfVIA2tWmRGFDZbyTgFBpBoOz4EyBEyo31r/e2e8D5B7R9/7xC3rJS7wtjX5KWdV J6APuPKSmeag44gij7dK5vFtOI898FGkUiHEe3U0nUzNolWEogce1r6r1mdNdQsL HBUeTGI6CAElsX+WSpW0mYS1uLaDXz56fHj5Bm/681PobS69tk7qOv6WdOvyNpNZ 7xtBwfOKDYmNAt5QYEIIAITJ1lm4nQoPdAjsaLeL91/1Sa5M770= =QlRp -----END PGP SIGNATURE----- Merge tag 'soc-fixes-6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "As usual, mostly DT fixes for the major Arm platforms from Qualcomm and NXP, plus a bit for Rockchips and others: The qualcomm fixes mainly deal with their higher-end arm64 devices trees, fixing issues in L3 interconnect, crypto, thermal, UFS and a regression for the DSI phy. NXP i.MX has two correctness fixes for the 64-bit chips, dealing with the imx93 "anatop" module and the CSI interface. On the 32-bit side, there are functional fixes for RTC, display and SD card intefaces. Rockchip fixes are for wifi support on certain boards, a eMMC stability and DT build warnings. On TI OMAP, a regulator is described in DT to avoid problems with the ethernet phy initialization. The code changes include a missing MMIO serialization on OMAP, plus a few minor fixes on ASpeed and AMD/Zynq chips" * tag 'soc-fixes-6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (30 commits) ARM: dts: am335x-bone-common: Add vcc-supply for on-board eeprom ARM: dts: am335x-bone-common: Add GPIO PHY reset on revision C3 board soc: aspeed: socinfo: Add kfree for kstrdup soc: aspeed: uart-routing: Use __sysfs_match_string ARM: dts: integrator: fix PCI bus dtc warnings arm64: dts: imx93: Fix anatop node size arm64: dts: qcom: sc7180: Fix DSI0_PHY reg-names ARM: dts: imx: Set default tuning step for imx6sx usdhc arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration ARM: dts: imx: Set default tuning step for imx7d usdhc ARM: dts: imx6: phytec: fix RTC interrupt level ARM: dts: imx6sx: Remove LDB endpoint arm64: dts: rockchip: Fix Wifi/Bluetooth on ROCK Pi 4 boards ARM: zynq: Explicitly include correct DT includes arm64: dts: qcom: sa8775p-ride: Update L4C parameters arm64: dts: rockchip: minor whitespace cleanup around '=' arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+ arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4 arm64: dts: rockchip: add missing space before { on indiedroid nova ...
This commit is contained in:
Коммит
80706f5529
|
@ -158,7 +158,7 @@
|
|||
valid-mask = <0x003fffff>;
|
||||
};
|
||||
|
||||
pci: pciv3@62000000 {
|
||||
pci: pci@62000000 {
|
||||
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
|
@ -182,7 +182,7 @@
|
|||
pinctrl-0 = <&pinctrl_rtc_int>;
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -863,7 +863,6 @@
|
|||
reg = <0>;
|
||||
|
||||
ldb_from_lcdif1: endpoint {
|
||||
remote-endpoint = <&lcdif1_to_ldb>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -1010,6 +1009,8 @@
|
|||
<&clks IMX6SX_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1022,6 +1023,8 @@
|
|||
<&clks IMX6SX_CLK_USDHC2>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1034,6 +1037,8 @@
|
|||
<&clks IMX6SX_CLK_USDHC3>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1309,11 +1314,8 @@
|
|||
power-domains = <&pd_disp>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
port {
|
||||
lcdif1_to_ldb: endpoint {
|
||||
remote-endpoint = <&ldb_from_lcdif1>;
|
||||
};
|
||||
port {
|
||||
lcdif1_to_ldb: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1184,6 +1184,8 @@
|
|||
<&clks IMX7D_USDHC1_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-step = <2>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1196,6 +1198,8 @@
|
|||
<&clks IMX7D_USDHC2_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-step = <2>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1208,6 +1212,8 @@
|
|||
<&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-step = <2>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -145,6 +145,8 @@
|
|||
/* MDIO */
|
||||
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
|
||||
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
|
||||
/* Added to support GPIO controlled PHY reset */
|
||||
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -153,6 +155,8 @@
|
|||
/* MDIO reset value */
|
||||
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
|
||||
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
|
||||
/* Added to support GPIO controlled PHY reset */
|
||||
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -215,6 +219,7 @@
|
|||
baseboard_eeprom: baseboard_eeprom@50 {
|
||||
compatible = "atmel,24c256";
|
||||
reg = <0x50>;
|
||||
vcc-supply = <&ldo4_reg>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
@ -377,6 +382,10 @@
|
|||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
/* Support GPIO reset on revision C3 boards */
|
||||
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <300>;
|
||||
reset-deassert-us = <6500>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -8,8 +8,8 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include "common.h"
|
||||
|
||||
/* register offsets */
|
||||
|
|
|
@ -1221,10 +1221,9 @@
|
|||
compatible = "fsl,imx8mm-mipi-csi2";
|
||||
reg = <0x32e30000 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
|
||||
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
|
||||
<&clk IMX8MM_SYS_PLL2_1000M>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
|
||||
|
||||
clock-frequency = <333000000>;
|
||||
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MM_CLK_CSI1_ROOT>,
|
||||
|
|
|
@ -1175,10 +1175,8 @@
|
|||
compatible = "fsl,imx8mm-mipi-csi2";
|
||||
reg = <0x32e30000 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
|
||||
<&clk IMX8MN_CLK_CSI1_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
|
||||
<&clk IMX8MN_SYS_PLL2_1000M>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
|
||||
assigned-clock-rates = <333000000>;
|
||||
clock-frequency = <333000000>;
|
||||
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
|
||||
|
|
|
@ -340,7 +340,7 @@
|
|||
|
||||
anatop: anatop@44480000 {
|
||||
compatible = "fsl,imx93-anatop", "syscon";
|
||||
reg = <0x44480000 0x10000>;
|
||||
reg = <0x44480000 0x2000>;
|
||||
};
|
||||
|
||||
adc1: adc@44530000 {
|
||||
|
|
|
@ -121,7 +121,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pm8150l-thermal {
|
||||
pm8150l-pcb-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm8150l_adc_tm 1>;
|
||||
|
|
|
@ -153,8 +153,8 @@
|
|||
|
||||
vreg_l4c: ldo4 {
|
||||
regulator-name = "vreg_l4c";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
/*
|
||||
* FIXME: This should have regulator-allow-set-load but
|
||||
|
|
|
@ -3120,8 +3120,8 @@
|
|||
reg = <0 0x0ae94400 0 0x200>,
|
||||
<0 0x0ae94600 0 0x280>,
|
||||
<0 0x0ae94a00 0 0x1e0>;
|
||||
reg-names = "dsi0_phy",
|
||||
"dsi0_phy_lane",
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
|
|
@ -3561,7 +3561,7 @@
|
|||
};
|
||||
|
||||
osm_l3: interconnect@18321000 {
|
||||
compatible = "qcom,sc8180x-osm-l3";
|
||||
compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
|
||||
reg = <0 0x18321000 0 0x1400>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
|
|
|
@ -56,7 +56,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -85,7 +85,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -109,7 +109,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -133,7 +133,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -157,7 +157,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD4>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -181,7 +181,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD5>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -205,7 +205,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD6>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -229,7 +229,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
operating-points-v2 = <&cpu7_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD7>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
@ -4342,7 +4342,7 @@
|
|||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#interconnect-cells = <2>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq@18323000 {
|
||||
|
|
|
@ -107,7 +107,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -138,7 +138,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -163,7 +163,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -188,7 +188,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -213,7 +213,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -238,7 +238,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -263,7 +263,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -288,7 +288,7 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
operating-points-v2 = <&cpu7_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
|
@ -5679,7 +5679,7 @@
|
|||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#interconnect-cells = <2>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq@18591000 {
|
||||
|
|
|
@ -1744,6 +1744,8 @@
|
|||
qcom,controlled-remotely;
|
||||
iommus = <&apps_smmu 0x594 0x0011>,
|
||||
<&apps_smmu 0x596 0x0011>;
|
||||
/* FIXME: Probing BAM DMA causes some abort and system hang */
|
||||
status = "fail";
|
||||
};
|
||||
|
||||
crypto: crypto@1dfa000 {
|
||||
|
@ -1755,6 +1757,8 @@
|
|||
<&apps_smmu 0x596 0x0011>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "memory";
|
||||
/* FIXME: dependency BAM DMA is disabled */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipa: ipa@1e40000 {
|
||||
|
|
|
@ -291,14 +291,14 @@
|
|||
};
|
||||
power-domain@PX30_PD_MMC_NAND {
|
||||
reg = <PX30_PD_MMC_NAND>;
|
||||
clocks = <&cru HCLK_NANDC>,
|
||||
<&cru HCLK_EMMC>,
|
||||
<&cru HCLK_SDIO>,
|
||||
<&cru HCLK_SFC>,
|
||||
<&cru SCLK_EMMC>,
|
||||
<&cru SCLK_NANDC>,
|
||||
<&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SFC>;
|
||||
clocks = <&cru HCLK_NANDC>,
|
||||
<&cru HCLK_EMMC>,
|
||||
<&cru HCLK_SDIO>,
|
||||
<&cru HCLK_SFC>,
|
||||
<&cru SCLK_EMMC>,
|
||||
<&cru SCLK_NANDC>,
|
||||
<&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SFC>;
|
||||
pm_qos = <&qos_emmc>, <&qos_nand>,
|
||||
<&qos_sdio>, <&qos_sfc>;
|
||||
#power-domain-cells = <0>;
|
||||
|
|
|
@ -106,7 +106,6 @@
|
|||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <827000>;
|
||||
regulator-max-microvolt = <1340000>;
|
||||
regulator-init-microvolt = <1015000>;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
|
|
@ -105,7 +105,6 @@
|
|||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <827000>;
|
||||
regulator-max-microvolt = <1340000>;
|
||||
regulator-init-microvolt = <1015000>;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
|
|
@ -773,7 +773,7 @@
|
|||
compatible = "brcm,bcm4329-fmac";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_l>;
|
||||
|
|
|
@ -375,7 +375,6 @@
|
|||
vcc_sdio: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <3000000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_sdio";
|
||||
|
|
|
@ -548,9 +548,8 @@
|
|||
&sdhci {
|
||||
max-frequency = <150000000>;
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -45,7 +45,7 @@
|
|||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
clock-names = "lpo";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
|
@ -645,9 +645,9 @@
|
|||
};
|
||||
|
||||
&sdhci {
|
||||
max-frequency = <150000000>;
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
compatible = "brcm,bcm4329-fmac";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_l>;
|
||||
|
|
|
@ -356,7 +356,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_logic";
|
||||
|
@ -371,7 +370,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_gpu";
|
||||
|
@ -533,7 +531,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
|
|
@ -239,7 +239,7 @@
|
|||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
|
@ -416,7 +416,7 @@
|
|||
compatible = "brcm,bcm4329-fmac";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_h>;
|
||||
|
|
|
@ -218,7 +218,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
@ -233,7 +232,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
@ -259,7 +257,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
|
|
@ -264,7 +264,6 @@
|
|||
regulator-always-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
@ -278,7 +277,6 @@
|
|||
regulator-name = "vdd_gpu_npu";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
|
|
@ -366,7 +366,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_logic";
|
||||
|
@ -381,7 +380,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_gpu";
|
||||
|
|
|
@ -277,7 +277,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
|
@ -292,7 +291,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
|
|
|
@ -137,8 +137,8 @@
|
|||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible="ethernet-phy-ieee802.3-c22";
|
||||
reg= <0x0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -278,7 +278,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
|
@ -291,7 +290,6 @@
|
|||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
|
|
|
@ -234,7 +234,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-state-mem {
|
||||
|
@ -249,7 +248,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-state-mem {
|
||||
|
@ -272,7 +270,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-state-mem {
|
||||
|
|
|
@ -308,7 +308,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -322,7 +321,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -346,7 +344,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
|
|
@ -293,7 +293,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -307,7 +306,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -331,7 +329,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
|
|
@ -173,7 +173,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -187,7 +186,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -211,7 +209,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -330,7 +327,6 @@
|
|||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
|
|
|
@ -243,7 +243,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
@ -258,7 +257,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
@ -284,7 +282,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
|
|
|
@ -232,7 +232,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -246,7 +245,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -270,7 +268,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
|
|
@ -291,7 +291,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -305,7 +304,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -329,7 +327,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
|
|
@ -163,7 +163,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -177,7 +176,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -201,7 +199,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
|
|
@ -350,7 +350,6 @@
|
|||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -364,7 +363,6 @@
|
|||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -388,7 +386,6 @@
|
|||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
|
|
@ -337,7 +337,6 @@
|
|||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-init-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
|
||||
|
|
|
@ -125,19 +125,19 @@
|
|||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_b0{
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1{
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2{
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3{
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
|
|
|
@ -2142,6 +2142,8 @@ static int sysc_reset(struct sysc *ddata)
|
|||
sysc_val = sysc_read_sysconfig(ddata);
|
||||
sysc_val |= sysc_mask;
|
||||
sysc_write(ddata, sysc_offset, sysc_val);
|
||||
/* Flush posted write */
|
||||
sysc_val = sysc_read_sysconfig(ddata);
|
||||
}
|
||||
|
||||
if (ddata->cfg.srst_udelay)
|
||||
|
|
|
@ -137,6 +137,7 @@ static int __init aspeed_socinfo_init(void)
|
|||
|
||||
soc_dev = soc_device_register(attrs);
|
||||
if (IS_ERR(soc_dev)) {
|
||||
kfree(attrs->machine);
|
||||
kfree(attrs->soc_id);
|
||||
kfree(attrs->serial_number);
|
||||
kfree(attrs);
|
||||
|
|
|
@ -524,7 +524,7 @@ static ssize_t aspeed_uart_routing_store(struct device *dev,
|
|||
struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
|
||||
int val;
|
||||
|
||||
val = match_string(sel->options, -1, buf);
|
||||
val = __sysfs_match_string(sel->options, -1, buf);
|
||||
if (val < 0) {
|
||||
dev_err(dev, "invalid value \"%s\"\n", buf);
|
||||
return -EINVAL;
|
||||
|
|
Загрузка…
Ссылка в новой задаче