Merge branch 'for-v3.17/cm-prm-cleanup' of https://github.com/t-kristo/linux-pm into omap-for-v3.17/soc
This commit is contained in:
Tony Lindgren
Коммит
81c6d80661
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@ -44,8 +44,7 @@ struct omap3_scratchpad {
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};
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struct omap3_scratchpad_prcm_block {
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u32 prm_clksrc_ctrl;
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u32 prm_clksel;
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u32 prm_contents[2];
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u32 cm_contents[11];
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u32 prcm_block_size;
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};
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@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void)
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void __iomem *v_addr;
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u32 offset = 0;
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v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
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if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
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OMAP3430_GLOBAL_COLD_RST_MASK) {
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if (omap3xxx_prm_clear_global_cold_reset()) {
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for ( ; offset <= max_offset; offset += 0x4)
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writel_relaxed(0x0, (v_addr + offset));
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omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
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OMAP3430_GR_MOD,
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OMAP3_PRM_RSTST_OFFSET);
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}
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}
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@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void)
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scratchpad_contents.sdrc_block_offset = 0x64;
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/* Populate the PRCM block contents */
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prcm_block_contents.prm_clksrc_ctrl =
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omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
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OMAP3_PRM_CLKSRC_CTRL_OFFSET);
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prcm_block_contents.prm_clksel =
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omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
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OMAP3_PRM_CLKSEL_OFFSET);
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omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
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omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
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prcm_block_contents.prcm_block_size = 0x0;
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@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void)
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* Sets the bootmode for IVA2 to idle. This is needed by the PM code to
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* force disable IVA2 so that it does not prevent any low-power states.
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*/
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void omap3_ctrl_set_iva_bootmode_idle(void)
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static void __init omap3_ctrl_set_iva_bootmode_idle(void)
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{
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omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
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OMAP343X_CONTROL_IVA2_BOOTMOD);
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}
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/**
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* omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
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*
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* Sets up the pads controlling the stacked modem in such way that the
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* device can enter idle.
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*/
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static void __init omap3_ctrl_setup_d2d_padconf(void)
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{
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u16 mask, padconf;
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/*
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* In a stand alone OMAP3430 where there is not a stacked
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* modem for the D2D Idle Ack and D2D MStandby must be pulled
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* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
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* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
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*/
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mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
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padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
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padconf |= mask;
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omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
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padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
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padconf |= mask;
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omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
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}
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/**
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* omap3_ctrl_init - does static initializations for control module
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*
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* Initializes system control module. This sets up the sysconfig autoidle,
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* and sets up modem and iva2 so that they can be idled properly.
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*/
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void __init omap3_ctrl_init(void)
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{
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omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
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omap3_ctrl_set_iva_bootmode_idle();
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omap3_ctrl_setup_d2d_padconf();
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}
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#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
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@ -455,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
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extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
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extern void omap3630_ctrl_disable_rta(void);
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extern int omap3_ctrl_save_padconf(void);
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extern void omap3_ctrl_set_iva_bootmode_idle(void);
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void omap3_ctrl_init(void);
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extern void omap2_set_globals_control(void __iomem *ctrl,
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void __iomem *ctrl_pad);
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#else
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@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
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/* Clear old wake-up events */
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/* REVISIT: These write to reserved bits? */
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
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omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
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omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
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omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
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pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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@ -104,23 +104,18 @@ no_sleep:
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clk_enable(osc_ck);
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/* clear CORE wake-up events */
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
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omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
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/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
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omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
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omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
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/* MPU domain wake events */
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l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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if (l & 0x01)
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omap2_prm_write_mod_reg(0x01, OCP_MOD,
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OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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if (l & 0x20)
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omap2_prm_write_mod_reg(0x20, OCP_MOD,
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OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
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0x1);
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/* Mask future PRCM-to-MPU interrupts */
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omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
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0x20);
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
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@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void)
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* it is in retention mode. */
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if (omap2_allow_mpu_retention()) {
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/* REVISIT: These write to reserved bits? */
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
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omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
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omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
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omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
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/* Try to enter MPU retention */
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void)
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}
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}
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/*
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
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static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
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{
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u32 wkst, fclk, iclk, clken;
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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u16 grpsel_off = (regs == 3) ?
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
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int c = 0;
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
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wkst &= ~ignore_bits;
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if (wkst) {
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iclk = omap2_cm_read_mod_reg(module, iclk_off);
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fclk = omap2_cm_read_mod_reg(module, fclk_off);
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while (wkst) {
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clken = wkst;
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omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
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/*
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* For USBHOST, we don't know whether HOST1 or
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* HOST2 woke us up, so enable both f-clocks
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*/
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if (module == OMAP3430ES2_USBHOST_MOD)
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clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
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omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
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omap2_prm_write_mod_reg(wkst, module, wkst_off);
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= ~ignore_bits;
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c++;
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}
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omap2_cm_write_mod_reg(iclk, module, iclk_off);
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omap2_cm_write_mod_reg(fclk, module, fclk_off);
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}
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return c;
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}
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static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
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{
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int c;
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
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~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
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c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
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~(OMAP3430_ST_IO_MASK |
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OMAP3430_ST_IO_CHAIN_MASK));
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return c ? IRQ_HANDLED : IRQ_NONE;
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}
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@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
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* these are handled in a separate handler to avoid acking
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* IO events before parsing in mux code
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*/
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
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OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
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c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
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c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
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c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
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OMAP3430_ST_IO_MASK |
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OMAP3430_ST_IO_CHAIN_MASK);
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c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
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c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
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c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
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c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
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c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
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}
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return c ? IRQ_HANDLED : IRQ_NONE;
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@ -399,159 +353,11 @@ restore:
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#define omap3_pm_suspend NULL
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#endif /* CONFIG_SUSPEND */
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/**
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* omap3_iva_idle(): ensure IVA is in idle so it can be put into
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* retention
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*
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* In cases where IVA2 is activated by bootcode, it may prevent
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* full-chip retention or off-mode because it is not idle. This
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* function forces the IVA2 into idle state so it can go
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* into retention/off and thus allow full-chip retention/off.
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*
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**/
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static void __init omap3_iva_idle(void)
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{
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/* ensure IVA2 clock is disabled */
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omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
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/* if no clock activity, nothing else to do */
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if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
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OMAP3430_CLKACTIVITY_IVA2_MASK))
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return;
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/* Reset IVA2 */
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omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
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OMAP3430_RST2_IVA2_MASK |
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OMAP3430_RST3_IVA2_MASK,
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OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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/* Enable IVA2 clock */
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omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
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OMAP3430_IVA2_MOD, CM_FCLKEN);
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/* Set IVA2 boot mode to 'idle' */
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omap3_ctrl_set_iva_bootmode_idle();
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/* Un-reset IVA2 */
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omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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/* Disable IVA2 clock */
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omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
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/* Reset IVA2 */
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omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
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OMAP3430_RST2_IVA2_MASK |
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OMAP3430_RST3_IVA2_MASK,
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OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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}
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static void __init omap3_d2d_idle(void)
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{
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u16 mask, padconf;
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/* In a stand alone OMAP3430 where there is not a stacked
|
||||
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
||||
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
||||
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
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mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
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padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
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padconf |= mask;
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omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
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padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
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padconf |= mask;
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omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
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/* reset modem */
|
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omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
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OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
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CORE_MOD, OMAP2_RM_RSTCTRL);
|
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omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
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||||
|
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static void __init prcm_setup_regs(void)
|
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{
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u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
|
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OMAP3630_EN_UART4_MASK : 0;
|
||||
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
|
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OMAP3630_GRPSEL_UART4_MASK : 0;
|
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omap3_ctrl_init();
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|
||||
/* XXX This should be handled by hwmod code or SCM init code */
|
||||
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
||||
|
||||
/*
|
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* Enable control of expternal oscillator through
|
||||
* sys_clkreq. In the long run clock framework should
|
||||
* take care of this.
|
||||
*/
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
||||
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
|
||||
/* setup wakup source */
|
||||
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
||||
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
||||
WKUP_MOD, PM_WKEN);
|
||||
/* No need to write EN_IO, that is always enabled */
|
||||
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
||||
OMAP3430_GRPSEL_GPT1_MASK |
|
||||
OMAP3430_GRPSEL_GPT12_MASK,
|
||||
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Enable PM_WKEN to support DSS LPR */
|
||||
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
||||
OMAP3430_DSS_MOD, PM_WKEN);
|
||||
|
||||
/* Enable wakeups in PER */
|
||||
omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
|
||||
OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
|
||||
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
|
||||
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
|
||||
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
|
||||
OMAP3430_EN_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, PM_WKEN);
|
||||
/* and allow them to wake up MPU */
|
||||
omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
|
||||
OMAP3430_GRPSEL_GPIO2_MASK |
|
||||
OMAP3430_GRPSEL_GPIO3_MASK |
|
||||
OMAP3430_GRPSEL_GPIO4_MASK |
|
||||
OMAP3430_GRPSEL_GPIO5_MASK |
|
||||
OMAP3430_GRPSEL_GPIO6_MASK |
|
||||
OMAP3430_GRPSEL_UART3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP2_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Don't attach IVA interrupts */
|
||||
if (omap3_has_iva()) {
|
||||
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL);
|
||||
}
|
||||
|
||||
/* Clear any pending 'reset' flags */
|
||||
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
|
||||
|
||||
/* Clear any pending PRCM interrupts */
|
||||
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
|
||||
/*
|
||||
* We need to idle iva2_pwrdm even on am3703 with no iva2.
|
||||
*/
|
||||
omap3_iva_idle();
|
||||
|
||||
omap3_d2d_idle();
|
||||
omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
|
||||
}
|
||||
|
||||
void omap3_pm_off_mode_enable(int enable)
|
||||
|
|
|
|||
|
|
@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void)
|
|||
omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
|
||||
* @module: PRM module to clear wakeups from
|
||||
* @regs: register offset to clear
|
||||
* @wkst_mask: wakeup status mask to clear
|
||||
*
|
||||
* Clears wakeup status bits for a given module, so that the device can
|
||||
* re-enter idle.
|
||||
*/
|
||||
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
|
||||
{
|
||||
u32 wkst;
|
||||
|
||||
wkst = omap2_prm_read_mod_reg(module, regs);
|
||||
wkst &= wkst_mask;
|
||||
omap2_prm_write_mod_reg(wkst, module, regs);
|
||||
}
|
||||
|
||||
int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
|
||||
{
|
||||
omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
|
||||
|
|
|
|||
|
|
@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
|
|||
extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
|
||||
|
||||
extern void omap2xxx_prm_dpll_reset(void);
|
||||
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
|
||||
|
||||
extern int __init omap2xxx_prm_init(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@
|
|||
#include "prm2xxx_3xxx.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
#include "cm3xxx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
static const struct omap_prcm_irq omap3_prcm_irqs[] = {
|
||||
OMAP_PRCM_IRQ("wkup", 0, 0),
|
||||
|
|
@ -205,6 +207,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
|
|||
OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
|
||||
* @module: PRM module to clear wakeups from
|
||||
* @regs: register set to clear, 1 or 3
|
||||
* @ignore_bits: wakeup status bits to ignore
|
||||
*
|
||||
* The purpose of this function is to clear any wake-up events latched
|
||||
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
|
||||
* may occur whilst attempting to clear a PM_WKST_x register and thus
|
||||
* set another bit in this register. A while loop is used to ensure
|
||||
* that any peripheral wake-up events occurring while attempting to
|
||||
* clear the PM_WKST_x are detected and cleared.
|
||||
*/
|
||||
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
|
||||
{
|
||||
u32 wkst, fclk, iclk, clken;
|
||||
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
|
||||
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
|
||||
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
|
||||
u16 grpsel_off = (regs == 3) ?
|
||||
OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
|
||||
int c = 0;
|
||||
|
||||
wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
||||
wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
|
||||
wkst &= ~ignore_bits;
|
||||
if (wkst) {
|
||||
iclk = omap2_cm_read_mod_reg(module, iclk_off);
|
||||
fclk = omap2_cm_read_mod_reg(module, fclk_off);
|
||||
while (wkst) {
|
||||
clken = wkst;
|
||||
omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
|
||||
/*
|
||||
* For USBHOST, we don't know whether HOST1 or
|
||||
* HOST2 woke us up, so enable both f-clocks
|
||||
*/
|
||||
if (module == OMAP3430ES2_USBHOST_MOD)
|
||||
clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
|
||||
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
|
||||
omap2_prm_write_mod_reg(wkst, module, wkst_off);
|
||||
wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
||||
wkst &= ~ignore_bits;
|
||||
c++;
|
||||
}
|
||||
omap2_cm_write_mod_reg(iclk, module, iclk_off);
|
||||
omap2_cm_write_mod_reg(fclk, module, fclk_off);
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_prm_reset_modem - toggle reset signal for modem
|
||||
*
|
||||
* Toggles the reset signal to modem IP block. Required to allow
|
||||
* OMAP3430 without stacked modem to idle properly.
|
||||
*/
|
||||
void __init omap3_prm_reset_modem(void)
|
||||
{
|
||||
omap2_prm_write_mod_reg(
|
||||
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
||||
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
||||
CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_prm_init_pm - initialize PM related registers for PRM
|
||||
* @has_uart4: SoC has UART4
|
||||
* @has_iva: SoC has IVA
|
||||
*
|
||||
* Initializes PRM registers for PM use. Called from PM init.
|
||||
*/
|
||||
void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
|
||||
{
|
||||
u32 en_uart4_mask;
|
||||
u32 grpsel_uart4_mask;
|
||||
|
||||
/*
|
||||
* Enable control of expternal oscillator through
|
||||
* sys_clkreq. In the long run clock framework should
|
||||
* take care of this.
|
||||
*/
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
||||
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
|
||||
/* setup wakup source */
|
||||
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
||||
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
||||
WKUP_MOD, PM_WKEN);
|
||||
/* No need to write EN_IO, that is always enabled */
|
||||
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
||||
OMAP3430_GRPSEL_GPT1_MASK |
|
||||
OMAP3430_GRPSEL_GPT12_MASK,
|
||||
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Enable PM_WKEN to support DSS LPR */
|
||||
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
||||
OMAP3430_DSS_MOD, PM_WKEN);
|
||||
|
||||
if (has_uart4) {
|
||||
en_uart4_mask = OMAP3630_EN_UART4_MASK;
|
||||
grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
|
||||
}
|
||||
|
||||
/* Enable wakeups in PER */
|
||||
omap2_prm_write_mod_reg(en_uart4_mask |
|
||||
OMAP3430_EN_GPIO2_MASK |
|
||||
OMAP3430_EN_GPIO3_MASK |
|
||||
OMAP3430_EN_GPIO4_MASK |
|
||||
OMAP3430_EN_GPIO5_MASK |
|
||||
OMAP3430_EN_GPIO6_MASK |
|
||||
OMAP3430_EN_UART3_MASK |
|
||||
OMAP3430_EN_MCBSP2_MASK |
|
||||
OMAP3430_EN_MCBSP3_MASK |
|
||||
OMAP3430_EN_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, PM_WKEN);
|
||||
|
||||
/* and allow them to wake up MPU */
|
||||
omap2_prm_write_mod_reg(grpsel_uart4_mask |
|
||||
OMAP3430_GRPSEL_GPIO2_MASK |
|
||||
OMAP3430_GRPSEL_GPIO3_MASK |
|
||||
OMAP3430_GRPSEL_GPIO4_MASK |
|
||||
OMAP3430_GRPSEL_GPIO5_MASK |
|
||||
OMAP3430_GRPSEL_GPIO6_MASK |
|
||||
OMAP3430_GRPSEL_UART3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP2_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Don't attach IVA interrupts */
|
||||
if (has_iva) {
|
||||
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL);
|
||||
}
|
||||
|
||||
/* Clear any pending 'reset' flags */
|
||||
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
|
||||
OMAP2_RM_RSTST);
|
||||
|
||||
/* Clear any pending PRCM interrupts */
|
||||
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
|
||||
/* We need to idle iva2_pwrdm even on am3703 with no iva2. */
|
||||
omap3xxx_prm_iva_idle();
|
||||
|
||||
omap3_prm_reset_modem();
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
|
||||
*
|
||||
|
|
@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void)
|
|||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
|
||||
*
|
||||
* In cases where IVA2 is activated by bootcode, it may prevent
|
||||
* full-chip retention or off-mode because it is not idle. This
|
||||
* function forces the IVA2 into idle state so it can go
|
||||
* into retention/off and thus allow full-chip retention/off.
|
||||
*/
|
||||
void omap3xxx_prm_iva_idle(void)
|
||||
{
|
||||
/* ensure IVA2 clock is disabled */
|
||||
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* if no clock activity, nothing else to do */
|
||||
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
||||
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
||||
return;
|
||||
|
||||
/* Reset IVA2 */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
||||
OMAP3430_RST2_IVA2_MASK |
|
||||
OMAP3430_RST3_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
|
||||
/* Enable IVA2 clock */
|
||||
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* Un-reset IVA2 */
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
|
||||
/* Disable IVA2 clock */
|
||||
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* Reset IVA2 */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
||||
OMAP3430_RST2_IVA2_MASK |
|
||||
OMAP3430_RST3_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
|
||||
* and clears it if asserted
|
||||
*
|
||||
* Checks if cold-reset has occurred and clears the status bit if yes. Returns
|
||||
* 1 if cold-reset has occurred, 0 otherwise.
|
||||
*/
|
||||
int omap3xxx_prm_clear_global_cold_reset(void)
|
||||
{
|
||||
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
|
||||
OMAP3430_GLOBAL_COLD_RST_MASK) {
|
||||
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_RSTST_OFFSET);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void omap3_prm_save_scratchpad_contents(u32 *ptr)
|
||||
{
|
||||
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
|
||||
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSEL_OFFSET);
|
||||
}
|
||||
|
||||
/* Powerdomain low-level functions */
|
||||
|
||||
static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
|
|
|
|||
|
|
@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void);
|
|||
|
||||
extern int __init omap3xxx_prm_init(void);
|
||||
extern u32 omap3xxx_prm_get_reset_sources(void);
|
||||
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
|
||||
void omap3xxx_prm_iva_idle(void);
|
||||
void omap3_prm_reset_modem(void);
|
||||
int omap3xxx_prm_clear_global_cold_reset(void);
|
||||
void omap3_prm_save_scratchpad_contents(u32 *ptr);
|
||||
void omap3_prm_init_pm(bool has_uart4, bool has_iva);
|
||||
|
||||
#endif /* __ASSEMBLER */
|
||||
|
||||
|
|
|
|||
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