ARM: dts: exynos: Move Mali400 GPU node to "/soc"
Mali400 GPU hardware module is a standard hardware module integrated to Exynos3210/4210/4412 SoCs, so it should reside under the "/soc" node. The only SoC components which are placed in the DT root, are those, which are a part of CPUs: like ARM architected timers and ARM performance measurement units. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -126,39 +126,6 @@
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};
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};
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gpu: gpu@13000000 {
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compatible = "samsung,exynos4210-mali", "arm,mali-400";
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reg = <0x13000000 0x10000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pp2",
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"ppmmu2",
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"pp3",
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"ppmmu3",
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"pmu";
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clocks = <&cmu CLK_G3D>,
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<&cmu CLK_SCLK_G3D>;
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clock-names = "bus", "core";
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power-domains = <&pd_g3d>;
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status = "disabled";
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/* TODO: operating points for DVFS, assigned clock as 134 MHz */
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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@ -495,6 +462,39 @@
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status = "disabled";
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};
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gpu: gpu@13000000 {
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compatible = "samsung,exynos4210-mali", "arm,mali-400";
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reg = <0x13000000 0x10000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pp2",
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"ppmmu2",
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"pp3",
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"ppmmu3",
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"pmu";
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clocks = <&cmu CLK_G3D>,
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<&cmu CLK_SCLK_G3D>;
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clock-names = "bus", "core";
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power-domains = <&pd_g3d>;
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status = "disabled";
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/* TODO: operating points for DVFS, assigned clock as 134 MHz */
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};
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mfc: codec@13400000 {
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compatible = "samsung,mfc-v7";
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reg = <0x13400000 0x10000>;
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@ -51,20 +51,6 @@
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serial3 = &serial_3;
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};
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gpu: gpu@13000000 {
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compatible = "samsung,exynos4210-mali", "arm,mali-400";
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reg = <0x13000000 0x10000>;
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/*
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* CLK_G3D is not actually bus clock but a IP-level clock.
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* The bus clock is not described in hardware manual.
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*/
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clocks = <&clock CLK_G3D>,
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<&clock CLK_SCLK_G3D>;
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clock-names = "bus", "core";
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power-domains = <&pd_g3d>;
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status = "disabled";
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};
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pmu: pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&combiner>;
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@ -429,6 +415,20 @@
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};
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};
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gpu: gpu@13000000 {
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compatible = "samsung,exynos4210-mali", "arm,mali-400";
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reg = <0x13000000 0x10000>;
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/*
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* CLK_G3D is not actually bus clock but a IP-level clock.
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* The bus clock is not described in hardware manual.
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*/
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clocks = <&clock CLK_G3D>,
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<&clock CLK_SCLK_G3D>;
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clock-names = "bus", "core";
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power-domains = <&pd_g3d>;
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status = "disabled";
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};
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i2s1: i2s@13960000 {
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compatible = "samsung,s3c6410-i2s";
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reg = <0x13960000 0x100>;
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