ARM: dts: Configure system timers for ti81xx
We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Note that for ti81xx, also timer1 is of type 2 unlike on am335x where timer1 is type1 while the rest of the timers are type 2. Cc: devicetree@vger.kernel.org Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Graeme Smecher <gsmecher@threespeedlogic.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Rob Herring <robh@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
Родитель
e428e250fd
Коммит
83bd18b466
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@ -308,14 +308,30 @@
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ti,hwmods = "mcspi4";
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};
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timer1: timer@2e000 {
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compatible = "ti,dm814-timer";
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reg = <0x2e000 0x2000>;
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interrupts = <67>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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timer1_target: target-module@2e000 {
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compatible = "ti,sysc-omap4-timer", "ti,sysc";
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reg = <0x2e000 0x4>,
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<0x2e010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&timer1_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2e000 0x1000>;
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timer1: timer@0 {
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compatible = "ti,am335x-timer-1ms";
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reg = <0x0 0x400>;
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interrupts = <67>;
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ti,timer-alwon;
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clocks = <&timer1_fck>;
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clock-names = "fck";
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};
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};
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uart1: uart@20000 {
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@ -348,13 +364,29 @@
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dma-names = "tx", "rx";
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};
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timer2: timer@40000 {
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compatible = "ti,dm814-timer";
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reg = <0x40000 0x2000>;
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interrupts = <68>;
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ti,hwmods = "timer2";
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timer2_target: target-module@40000 {
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compatible = "ti,sysc-omap4-timer", "ti,sysc";
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reg = <0x40000 0x4>,
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<0x40010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&timer2_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x40000 0x1000>;
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timer2: timer@0 {
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compatible = "ti,dm814-timer";
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reg = <0 0x1000>;
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interrupts = <68>;
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clocks = <&timer2_fck>;
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clock-names = "fck";
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};
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};
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timer3: timer@42000 {
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@ -735,3 +767,23 @@
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};
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#include "dm814x-clocks.dtsi"
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/* Preferred always-on timer for clocksource */
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&timer1_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&timer1_fck>;
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assigned-clock-parents = <&devosc_ck>;
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};
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};
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/* Preferred timer for clockevent */
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&timer2_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&timer2_fck>;
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assigned-clock-parents = <&devosc_ck>;
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};
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};
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@ -440,23 +440,55 @@
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dma-names = "tx", "rx";
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};
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timer1: timer@4802e000 {
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compatible = "ti,dm816-timer";
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reg = <0x4802e000 0x2000>;
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interrupts = <67>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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clocks = <&timer1_fck>;
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timer1_target: target-module@4802e000 {
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compatible = "ti,sysc-omap4-timer", "ti,sysc";
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reg = <0x4802e000 0x4>,
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<0x4802e010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4802e000 0x1000>;
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timer1: timer@0 {
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compatible = "ti,dm816-timer";
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reg = <0 0x1000>;
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interrupts = <67>;
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ti,timer-alwon;
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clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
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clock-names = "fck";
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};
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};
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timer2: timer@48040000 {
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compatible = "ti,dm816-timer";
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reg = <0x48040000 0x2000>;
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interrupts = <68>;
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ti,hwmods = "timer2";
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clocks = <&timer2_fck>;
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timer2_target: target-module@48040000 {
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compatible = "ti,sysc-omap4-timer", "ti,sysc";
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reg = <0x48040000 0x4>,
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<0x48040010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x48040000 0x1000>;
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timer2: timer@0 {
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compatible = "ti,dm816-timer";
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reg = <0 0x1000>;
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interrupts = <68>;
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clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
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clock-names = "fck";
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};
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};
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timer3: timer@48042000 {
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@ -642,3 +674,23 @@
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};
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#include "dm816x-clocks.dtsi"
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/* Preferred always-on timer for clocksource */
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&timer1_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&timer1_fck>;
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assigned-clock-parents = <&sys_clkin_ck>;
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};
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};
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/* Preferred timer for clockevent */
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&timer2_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&timer2_fck>;
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assigned-clock-parents = <&sys_clkin_ck>;
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};
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};
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@ -201,7 +201,7 @@ DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)")
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.init_early = ti814x_init_early,
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.init_machine = omap_generic_init,
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.init_late = ti81xx_init_late,
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.init_time = omap3_gptimer_timer_init,
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.init_time = omap_init_time_of,
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.dt_compat = ti814x_boards_compat,
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.restart = ti81xx_restart,
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MACHINE_END
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@ -218,7 +218,7 @@ DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)")
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.init_early = ti816x_init_early,
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.init_machine = omap_generic_init,
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.init_late = ti81xx_init_late,
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.init_time = omap3_gptimer_timer_init,
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.init_time = omap_init_time_of,
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.dt_compat = ti816x_boards_compat,
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.restart = ti81xx_restart,
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MACHINE_END
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@ -690,76 +690,6 @@ static struct omap_hwmod_class dm816x_timer_hwmod_class = {
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.sysc = &dm816x_timer_sysc,
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};
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static struct omap_hwmod dm814x_timer1_hwmod = {
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.name = "timer1",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "timer1_fck",
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.class = &dm816x_timer_hwmod_class,
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.flags = HWMOD_NO_IDLEST,
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};
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static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm814x_timer1_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod dm816x_timer1_hwmod = {
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.name = "timer1",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "timer1_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_timer_hwmod_class,
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};
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static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm816x_timer1_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod dm814x_timer2_hwmod = {
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.name = "timer2",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "timer2_fck",
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.class = &dm816x_timer_hwmod_class,
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.flags = HWMOD_NO_IDLEST,
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};
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static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm814x_timer2_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod dm816x_timer2_hwmod = {
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.name = "timer2",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "timer2_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_timer_hwmod_class,
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};
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static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm816x_timer2_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod dm816x_timer3_hwmod = {
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.name = "timer3",
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.clkdm_name = "alwon_l3s_clkdm",
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@ -1288,8 +1218,6 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
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&dm814x_l4_ls__mmc1,
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&dm814x_l4_ls__mmc2,
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&ti81xx_l4_ls__rtc,
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&dm814x_l4_ls__timer1,
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&dm814x_l4_ls__timer2,
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&dm81xx_alwon_l3_slow__gpmc,
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&dm814x_default_l3_slow__usbss,
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&dm814x_alwon_l3_med__mmc3,
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@ -1318,8 +1246,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
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&dm81xx_l4_ls__elm,
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&ti81xx_l4_ls__rtc,
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&dm816x_l4_ls__mmc1,
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&dm816x_l4_ls__timer1,
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&dm816x_l4_ls__timer2,
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&dm816x_l4_ls__timer3,
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&dm816x_l4_ls__timer4,
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&dm816x_l4_ls__timer5,
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