Merge remote-tracking branch 'asoc/topic/cs42l73' into asoc-next
This commit is contained in:
Mark Brown
Коммит
85eb5dce82
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@ -0,0 +1,22 @@
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CS42L73 audio CODEC
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Required properties:
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- compatible : "cirrus,cs42l73"
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- reg : the I2C address of the device for I2C
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Optional properties:
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- reset_gpio : a GPIO spec for the reset pin.
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- chgfreq : Charge Pump Frequency values 0x00-0x0F
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Example:
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codec: cs42l73@4a {
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compatible = "cirrus,cs42l73";
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reg = <0x4a>;
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reset_gpio = <&gpio 10 0>;
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chgfreq = <0x05>;
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};
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@ -0,0 +1,22 @@
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/*
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* linux/sound/cs42l73.h -- Platform data for CS42L73
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*
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* Copyright (c) 2012 Cirrus Logic Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CS42L73_H
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#define __CS42L73_H
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struct cs42l73_platform_data {
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/* RST GPIO */
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unsigned int reset_gpio;
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unsigned int chgfreq;
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int jack_detection;
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unsigned int mclk_freq;
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};
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#endif /* __CS42L73_H */
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@ -17,6 +17,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/of_gpio.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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@ -28,6 +29,7 @@
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#include <sound/soc-dapm.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/cs42l73.h>
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#include "cs42l73.h"
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struct sp_config {
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@ -35,6 +37,7 @@ struct sp_config {
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u32 srate;
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};
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struct cs42l73_private {
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struct cs42l73_platform_data pdata;
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struct sp_config config[3];
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struct regmap *regmap;
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u32 sysclk;
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@ -310,15 +313,6 @@ static const struct soc_enum ng_delay_enum =
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SOC_ENUM_SINGLE(CS42L73_NGCAB, 0,
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ARRAY_SIZE(cs42l73_ng_delay_text), cs42l73_ng_delay_text);
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static const char * const charge_pump_freq_text[] = {
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"0", "1", "2", "3", "4",
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"5", "6", "7", "8", "9",
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"10", "11", "12", "13", "14", "15" };
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static const struct soc_enum charge_pump_enum =
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SOC_ENUM_SINGLE(CS42L73_CPFCHC, 4,
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ARRAY_SIZE(charge_pump_freq_text), charge_pump_freq_text);
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static const char * const cs42l73_mono_mix_texts[] = {
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"Left", "Right", "Mono Mix"};
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@ -511,8 +505,6 @@ static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
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SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
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SOC_ENUM("NG Delay", ng_delay_enum),
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SOC_ENUM("Charge Pump Frequency", charge_pump_enum),
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SOC_DOUBLE_R_TLV("XSP-IP Volume",
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CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
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attn_tlv),
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@ -1055,11 +1047,11 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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mmcc |= MS_MASTER;
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mmcc |= CS42L73_MS_MASTER;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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mmcc &= ~MS_MASTER;
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mmcc &= ~CS42L73_MS_MASTER;
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break;
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default:
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@ -1071,11 +1063,11 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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switch (format) {
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case SND_SOC_DAIFMT_I2S:
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spc &= ~SPDIF_PCM;
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spc &= ~CS42L73_SPDIF_PCM;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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if (mmcc & MS_MASTER) {
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if (mmcc & CS42L73_MS_MASTER) {
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dev_err(codec->dev,
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"PCM format in slave mode only\n");
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return -EINVAL;
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@ -1085,25 +1077,25 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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"PCM format is not supported on ASP port\n");
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return -EINVAL;
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}
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spc |= SPDIF_PCM;
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spc |= CS42L73_SPDIF_PCM;
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break;
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default:
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return -EINVAL;
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}
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if (spc & SPDIF_PCM) {
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if (spc & CS42L73_SPDIF_PCM) {
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/* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
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spc &= ~(PCM_MODE_MASK | PCM_BIT_ORDER);
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spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
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switch (format) {
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case SND_SOC_DAIFMT_DSP_B:
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if (inv == SND_SOC_DAIFMT_IB_IF)
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spc |= PCM_MODE0;
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spc |= CS42L73_PCM_MODE0;
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if (inv == SND_SOC_DAIFMT_IB_NF)
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spc |= PCM_MODE1;
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spc |= CS42L73_PCM_MODE1;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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if (inv == SND_SOC_DAIFMT_IB_IF)
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spc |= PCM_MODE1;
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spc |= CS42L73_PCM_MODE1;
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break;
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default:
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return -EINVAL;
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@ -1163,7 +1155,7 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
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int mclk_coeff;
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int srate = params_rate(params);
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if (priv->config[id].mmcc & MS_MASTER) {
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if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
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/* CS42L73 Master */
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/* MCLK -> srate */
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mclk_coeff =
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@ -1182,13 +1174,13 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
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priv->config[id].spc &= 0xFC;
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/* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
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if (priv->mclk >= 6400000)
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priv->config[id].spc |= MCK_SCLK_64FS;
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priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
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else
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priv->config[id].spc |= MCK_SCLK_MCLK;
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priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
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} else {
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/* CS42L73 Slave */
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priv->config[id].spc &= 0xFC;
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priv->config[id].spc |= MCK_SCLK_64FS;
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priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
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}
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/* Update ASRCs */
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priv->config[id].srate = srate;
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@ -1208,8 +1200,8 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
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switch (level) {
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case SND_SOC_BIAS_ON:
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snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0);
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snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 0);
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break;
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case SND_SOC_BIAS_PREPARE:
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@ -1220,11 +1212,11 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
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regcache_cache_only(cs42l73->regmap, false);
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regcache_sync(cs42l73->regmap);
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}
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
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break;
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case SND_SOC_BIAS_OFF:
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
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snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
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if (cs42l73->shutdwn_delay > 0) {
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mdelay(cs42l73->shutdwn_delay);
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cs42l73->shutdwn_delay = 0;
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@ -1233,7 +1225,7 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
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* down.
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*/
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}
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snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1);
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snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
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break;
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}
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codec->dapm.bias_level = level;
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@ -1367,11 +1359,16 @@ static int cs42l73_probe(struct snd_soc_codec *codec)
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return ret;
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}
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regcache_cache_only(cs42l73->regmap, true);
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cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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cs42l73->mclksel = CS42L73_CLKID_MCLK1; /* MCLK1 as master clk */
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/* Set Charge Pump Frequency */
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if (cs42l73->pdata.chgfreq)
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snd_soc_update_bits(codec, CS42L73_CPFCHC,
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CS42L73_CHARGEPUMP_MASK,
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cs42l73->pdata.chgfreq << 4);
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/* MCLK1 as master clk */
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cs42l73->mclksel = CS42L73_CLKID_MCLK1;
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cs42l73->mclk = 0;
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return ret;
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@ -1415,9 +1412,11 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
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const struct i2c_device_id *id)
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{
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struct cs42l73_private *cs42l73;
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struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
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int ret;
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unsigned int devid = 0;
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unsigned int reg;
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u32 val32;
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|
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cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private),
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GFP_KERNEL);
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@ -1426,14 +1425,49 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
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return -ENOMEM;
|
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}
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|
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i2c_set_clientdata(i2c_client, cs42l73);
|
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|
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cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
|
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if (IS_ERR(cs42l73->regmap)) {
|
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ret = PTR_ERR(cs42l73->regmap);
|
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dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
|
||||
return ret;
|
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}
|
||||
|
||||
if (pdata) {
|
||||
cs42l73->pdata = *pdata;
|
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} else {
|
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pdata = devm_kzalloc(&i2c_client->dev,
|
||||
sizeof(struct cs42l73_platform_data),
|
||||
GFP_KERNEL);
|
||||
if (!pdata) {
|
||||
dev_err(&i2c_client->dev, "could not allocate pdata\n");
|
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return -ENOMEM;
|
||||
}
|
||||
if (i2c_client->dev.of_node) {
|
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if (of_property_read_u32(i2c_client->dev.of_node,
|
||||
"chgfreq", &val32) >= 0)
|
||||
pdata->chgfreq = val32;
|
||||
}
|
||||
pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
|
||||
"reset-gpio", 0);
|
||||
cs42l73->pdata = *pdata;
|
||||
}
|
||||
|
||||
i2c_set_clientdata(i2c_client, cs42l73);
|
||||
|
||||
if (cs42l73->pdata.reset_gpio) {
|
||||
ret = gpio_request_one(cs42l73->pdata.reset_gpio,
|
||||
GPIOF_OUT_INIT_HIGH, "CS42L73 /RST");
|
||||
if (ret < 0) {
|
||||
dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
|
||||
cs42l73->pdata.reset_gpio, ret);
|
||||
return ret;
|
||||
}
|
||||
gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
|
||||
gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
|
||||
}
|
||||
|
||||
regcache_cache_bypass(cs42l73->regmap, true);
|
||||
|
||||
/* initialize codec */
|
||||
ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, ®);
|
||||
devid = (reg & 0xFF) << 12;
|
||||
|
|
@ -1444,7 +1478,6 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
|
|||
ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, ®);
|
||||
devid |= (reg & 0xF0) >> 4;
|
||||
|
||||
|
||||
if (devid != CS42L73_DEVID) {
|
||||
ret = -ENODEV;
|
||||
dev_err(&i2c_client->dev,
|
||||
|
|
@ -1462,7 +1495,7 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
|
|||
dev_info(&i2c_client->dev,
|
||||
"Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
|
||||
|
||||
regcache_cache_only(cs42l73->regmap, true);
|
||||
regcache_cache_bypass(cs42l73->regmap, false);
|
||||
|
||||
ret = snd_soc_register_codec(&i2c_client->dev,
|
||||
&soc_codec_dev_cs42l73, cs42l73_dai,
|
||||
|
|
@ -1478,6 +1511,12 @@ static int cs42l73_i2c_remove(struct i2c_client *client)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id cs42l73_of_match[] = {
|
||||
{ .compatible = "cirrus,cs42l73", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, cs42l73_of_match);
|
||||
|
||||
static const struct i2c_device_id cs42l73_id[] = {
|
||||
{"cs42l73", 0},
|
||||
{}
|
||||
|
|
@ -1489,6 +1528,7 @@ static struct i2c_driver cs42l73_i2c_driver = {
|
|||
.driver = {
|
||||
.name = "cs42l73",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = cs42l73_of_match,
|
||||
},
|
||||
.id_table = cs42l73_id,
|
||||
.probe = cs42l73_i2c_probe,
|
||||
|
|
|
|||
|
|
@ -128,59 +128,60 @@
|
|||
/* Bitfield Definitions */
|
||||
|
||||
/* CS42L73_PWRCTL1 */
|
||||
#define PDN_ADCB (1 << 7)
|
||||
#define PDN_DMICB (1 << 6)
|
||||
#define PDN_ADCA (1 << 5)
|
||||
#define PDN_DMICA (1 << 4)
|
||||
#define PDN_LDO (1 << 2)
|
||||
#define DISCHG_FILT (1 << 1)
|
||||
#define PDN (1 << 0)
|
||||
#define CS42L73_PDN_ADCB (1 << 7)
|
||||
#define CS42L73_PDN_DMICB (1 << 6)
|
||||
#define CS42L73_PDN_ADCA (1 << 5)
|
||||
#define CS42L73_PDN_DMICA (1 << 4)
|
||||
#define CS42L73_PDN_LDO (1 << 2)
|
||||
#define CS42L73_DISCHG_FILT (1 << 1)
|
||||
#define CS42L73_PDN (1 << 0)
|
||||
|
||||
/* CS42L73_PWRCTL2 */
|
||||
#define PDN_MIC2_BIAS (1 << 7)
|
||||
#define PDN_MIC1_BIAS (1 << 6)
|
||||
#define PDN_VSP (1 << 4)
|
||||
#define PDN_ASP_SDOUT (1 << 3)
|
||||
#define PDN_ASP_SDIN (1 << 2)
|
||||
#define PDN_XSP_SDOUT (1 << 1)
|
||||
#define PDN_XSP_SDIN (1 << 0)
|
||||
#define CS42L73_PDN_MIC2_BIAS (1 << 7)
|
||||
#define CS42L73_PDN_MIC1_BIAS (1 << 6)
|
||||
#define CS42L73_PDN_VSP (1 << 4)
|
||||
#define CS42L73_PDN_ASP_SDOUT (1 << 3)
|
||||
#define CS42L73_PDN_ASP_SDIN (1 << 2)
|
||||
#define CS42L73_PDN_XSP_SDOUT (1 << 1)
|
||||
#define CS42L73_PDN_XSP_SDIN (1 << 0)
|
||||
|
||||
/* CS42L73_PWRCTL3 */
|
||||
#define PDN_THMS (1 << 5)
|
||||
#define PDN_SPKLO (1 << 4)
|
||||
#define PDN_EAR (1 << 3)
|
||||
#define PDN_SPK (1 << 2)
|
||||
#define PDN_LO (1 << 1)
|
||||
#define PDN_HP (1 << 0)
|
||||
#define CS42L73_PDN_THMS (1 << 5)
|
||||
#define CS42L73_PDN_SPKLO (1 << 4)
|
||||
#define CS42L73_PDN_EAR (1 << 3)
|
||||
#define CS42L73_PDN_SPK (1 << 2)
|
||||
#define CS42L73_PDN_LO (1 << 1)
|
||||
#define CS42L73_PDN_HP (1 << 0)
|
||||
|
||||
/* Thermal Overload Detect. Requires interrupt ... */
|
||||
#define THMOVLD_150C 0
|
||||
#define THMOVLD_132C 1
|
||||
#define THMOVLD_115C 2
|
||||
#define THMOVLD_098C 3
|
||||
#define CS42L73_THMOVLD_150C 0
|
||||
#define CS42L73_THMOVLD_132C 1
|
||||
#define CS42L73_THMOVLD_115C 2
|
||||
#define CS42L73_THMOVLD_098C 3
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#define CS42L73_CHARGEPUMP_MASK (0xF0)
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/* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */
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#define SP_3ST (1 << 7)
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#define SPDIF_I2S (0 << 6)
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#define SPDIF_PCM (1 << 6)
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#define PCM_MODE0 (0 << 4)
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#define PCM_MODE1 (1 << 4)
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#define PCM_MODE2 (2 << 4)
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#define PCM_MODE_MASK (3 << 4)
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#define PCM_BIT_ORDER (1 << 3)
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#define MCK_SCLK_64FS (0 << 0)
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#define MCK_SCLK_MCLK (2 << 0)
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#define MCK_SCLK_PREMCLK (3 << 0)
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#define CS42L73_SP_3ST (1 << 7)
|
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#define CS42L73_SPDIF_I2S (0 << 6)
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#define CS42L73_SPDIF_PCM (1 << 6)
|
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#define CS42L73_PCM_MODE0 (0 << 4)
|
||||
#define CS42L73_PCM_MODE1 (1 << 4)
|
||||
#define CS42L73_PCM_MODE2 (2 << 4)
|
||||
#define CS42L73_PCM_MODE_MASK (3 << 4)
|
||||
#define CS42L73_PCM_BIT_ORDER (1 << 3)
|
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#define CS42L73_MCK_SCLK_64FS (0 << 0)
|
||||
#define CS42L73_MCK_SCLK_MCLK (2 << 0)
|
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#define CS42L73_MCK_SCLK_PREMCLK (3 << 0)
|
||||
|
||||
/* CS42L73_xSPMMCC */
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#define MS_MASTER (1 << 7)
|
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#define CS42L73_MS_MASTER (1 << 7)
|
||||
|
||||
|
||||
/* CS42L73_DMMCC */
|
||||
#define MCLKDIS (1 << 0)
|
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#define MCLKSEL_MCLK2 (1 << 4)
|
||||
#define MCLKSEL_MCLK1 (0 << 4)
|
||||
#define CS42L73_MCLKDIS (1 << 0)
|
||||
#define CS42L73_MCLKSEL_MCLK2 (1 << 4)
|
||||
#define CS42L73_MCLKSEL_MCLK1 (0 << 4)
|
||||
|
||||
/* CS42L73 MCLK derived from MCLK1 or MCLK2 */
|
||||
#define CS42L73_CLKID_MCLK1 0
|
||||
|
|
@ -194,28 +195,26 @@
|
|||
#define CS42L73_VSP 2
|
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|
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/* IS1, IM1 */
|
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#define MIC2_SDET (1 << 6)
|
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#define THMOVLD (1 << 4)
|
||||
#define DIGMIXOVFL (1 << 3)
|
||||
#define IPBOVFL (1 << 1)
|
||||
#define IPAOVFL (1 << 0)
|
||||
#define CS42L73_MIC2_SDET (1 << 6)
|
||||
#define CS42L73_THMOVLD (1 << 4)
|
||||
#define CS42L73_DIGMIXOVFL (1 << 3)
|
||||
#define CS42L73_IPBOVFL (1 << 1)
|
||||
#define CS42L73_IPAOVFL (1 << 0)
|
||||
|
||||
/* Analog Softramp */
|
||||
#define ANLGOSFT (1 << 0)
|
||||
#define CS42L73_ANLGOSFT (1 << 0)
|
||||
|
||||
/* HP A/B Analog Mute */
|
||||
#define HPA_MUTE (1 << 7)
|
||||
#define CS42L73_HPA_MUTE (1 << 7)
|
||||
/* LO A/B Analog Mute */
|
||||
#define LOA_MUTE (1 << 7)
|
||||
#define CS42L73_LOA_MUTE (1 << 7)
|
||||
/* Digital Mute */
|
||||
#define HLAD_MUTE (1 << 0)
|
||||
#define HLBD_MUTE (1 << 1)
|
||||
#define SPKD_MUTE (1 << 2)
|
||||
#define ESLD_MUTE (1 << 3)
|
||||
#define CS42L73_HLAD_MUTE (1 << 0)
|
||||
#define CS42L73_HLBD_MUTE (1 << 1)
|
||||
#define CS42L73_SPKD_MUTE (1 << 2)
|
||||
#define CS42L73_ESLD_MUTE (1 << 3)
|
||||
|
||||
/* Misc defines for codec */
|
||||
#define CS42L73_RESET_GPIO 143
|
||||
|
||||
#define CS42L73_DEVID 0x00042A73
|
||||
#define CS42L73_MCLKX_MIN 5644800
|
||||
#define CS42L73_MCLKX_MAX 38400000
|
||||
|
|
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