Merge tag 'DT-for-v3.15-part-1-v2' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt
Merge "STi DT changes part 1 v2" from Srinivas Kandagatla: Patches : 01-02 are DT patches, adding interrupt support to pin controller driver, Driver changes are already going via Linus W's pinctrl tree. Patches: 03 - 06 are DT patches for reset/softreset controller. Reset controller driver is Acked by Philipp Zabel. Patches: 07, 08 are DT patches, adding Ethernet controller support patches, actual driver changes are already in v3.14-rc4 via Dave Millers net tree. Patches: 09, 10 are DT patches for IR driver support, actual IR driver is already available since v3.12. Reason for the delay is due to dependency on reset controller driver/headers. * tag 'DT-for-v3.15-part-1-v2' of git://git.stlinux.com/devel/kernel/linux-sti: ARM: STi: STIH416: Add IR support. ARM: STi: STIH415: Add IR support. ARM: STi: STiH416: Add ethernet support. ARM: STi: STiH415: Add ethernet support. ARM: STi: STiH416: Add soft reset controller support. ARM: STi: STiH416: Add reset controller support. ARM: STi: STiH415: Add soft reset controller support. ARM: STi: STiH415: Add reset controller support. ARM: STi: STiH415: Add interrupt support for pin controller ARM: STi: STiH416: Add interrupt support for pin controller Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
98907c2d3d
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@ -0,0 +1,47 @@
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STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
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=============================================================================
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||||
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This binding describes a reset controller device that is used to enable and
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disable on-chip peripheral controllers such as USB and SATA, using
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"powerdown" control bits found in the STi family SoC system configuration
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registers. These have been grouped together into a single reset controller
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device for convenience.
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The actual action taken when powerdown is asserted is hardware dependent.
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||||
However, when asserted it may not be possible to access the hardware's
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||||
registers and after an assert/deassert sequence the hardware's previous state
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||||
may no longer be valid.
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||||
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||||
Please refer to reset.txt in this directory for common reset
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||||
controller binding usage.
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||||
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||||
Required properties:
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- compatible: Should be "st,<chip>-powerdown"
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ex: "st,stih415-powerdown", "st,stih416-powerdown"
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- #reset-cells: 1, see below
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example:
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powerdown: powerdown-controller {
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#reset-cells = <1>;
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compatible = "st,stih415-powerdown";
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};
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Specifying powerdown control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the powerdown device node and an
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index specifying which channel to use, as described in reset.txt
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example:
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usb1: usb@fe200000 {
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resets = <&powerdown STIH41X_USB1_POWERDOWN>;
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};
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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih415-resets.h
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include/dt-bindings/reset-controller/stih416-resets.h
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@ -0,0 +1,46 @@
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STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
|
||||
=============================================================================
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||||
|
||||
This binding describes a reset controller device that is used to enable and
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disable on-chip peripheral controllers such as USB and SATA, using
|
||||
"softreset" control bits found in the STi family SoC system configuration
|
||||
registers.
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||||
|
||||
The actual action taken when softreset is asserted is hardware dependent.
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||||
However, when asserted it may not be possible to access the hardware's
|
||||
registers and after an assert/deassert sequence the hardware's previous state
|
||||
may no longer be valid.
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||||
|
||||
Please refer to reset.txt in this directory for common reset
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||||
controller binding usage.
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Required properties:
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- compatible: Should be "st,<chip>-softreset" example:
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"st,stih415-softreset" or "st,stih416-softreset";
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- #reset-cells: 1, see below
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example:
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softreset: softreset-controller {
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#reset-cells = <1>;
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compatible = "st,stih415-softreset";
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};
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Specifying softreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the softreset device node and an
|
||||
index specifying which channel to use, as described in reset.txt
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example:
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ethernet0{
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resets = <&softreset STIH415_ETH0_SOFTRESET>;
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};
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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih415-resets.h
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include/dt-bindings/reset-controller/stih416-resets.h
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@ -34,5 +34,19 @@
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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CLKS_GMAC0_PHY: clockgenA1@7 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "CLKS_GMAC0_PHY";
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};
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CLKS_ETH1_PHY: clockgenA0@7 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "CLKS_ETH1_PHY";
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};
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};
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};
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|
|
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@ -7,6 +7,7 @@
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* publishhed by the Free Software Foundation.
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*/
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#include "st-pincfg.h"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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aliases {
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@ -45,35 +46,49 @@
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#size-cells = <1>;
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compatible = "st,stih415-sbc-pinctrl";
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st,syscfg = <&syscfg_sbc>;
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reg = <0xfe61f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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interrupts-names = "irqmux";
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ranges = <0 0xfe610000 0x5000>;
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PIO0: gpio@fe610000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO0";
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};
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PIO1: gpio@fe611000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO1";
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};
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PIO2: gpio@fe612000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO2";
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};
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PIO3: gpio@fe613000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO3";
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};
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PIO4: gpio@fe614000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO4";
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};
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@ -104,6 +119,64 @@
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};
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};
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};
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rc{
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pinctrl_ir: ir0 {
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st,pins {
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ir = <&PIO4 0 ALT2 IN>;
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};
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};
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};
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gmac1 {
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pinctrl_mii1: mii1 {
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st,pins {
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txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
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col = <&PIO0 7 ALT1 IN BYPASS 1000>;
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mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
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mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
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crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
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mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
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rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
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phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
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};
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};
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pinctrl_rgmii1: rgmii1-0 {
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st,pins {
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txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
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txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
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txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
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txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
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txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
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txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
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mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
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mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
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rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
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rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
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rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
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rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
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rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
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rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
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phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
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clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
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};
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};
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};
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};
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pin-controller-front {
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@ -111,53 +184,73 @@
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#size-cells = <1>;
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compatible = "st,stih415-front-pinctrl";
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st,syscfg = <&syscfg_front>;
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reg = <0xfee0f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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interrupts-names = "irqmux";
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ranges = <0 0xfee00000 0x8000>;
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PIO5: gpio@fee00000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO5";
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};
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PIO6: gpio@fee01000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO6";
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};
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PIO7: gpio@fee02000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO7";
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};
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PIO8: gpio@fee03000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO8";
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};
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PIO9: gpio@fee04000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO9";
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};
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PIO10: gpio@fee05000 {
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gpio-controller;
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#gpio-cells = <1>;
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO10";
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};
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PIO11: gpio@fee06000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x100>;
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st,bank-name = "PIO11";
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};
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PIO12: gpio@fee07000 {
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gpio-controller;
|
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#gpio-cells = <1>;
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
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||||
reg = <0x7000 0x100>;
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st,bank-name = "PIO12";
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||||
};
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|
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@ -186,41 +279,57 @@
|
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#size-cells = <1>;
|
||||
compatible = "st,stih415-rear-pinctrl";
|
||||
st,syscfg = <&syscfg_rear>;
|
||||
reg = <0xfe82f080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfe820000 0x8000>;
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||||
|
||||
PIO13: gpio@fe820000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO13";
|
||||
};
|
||||
PIO14: gpio@fe821000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO14";
|
||||
};
|
||||
PIO15: gpio@fe822000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO15";
|
||||
};
|
||||
PIO16: gpio@fe823000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x100>;
|
||||
st,bank-name = "PIO16";
|
||||
};
|
||||
PIO17: gpio@fe824000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x100>;
|
||||
st,bank-name = "PIO17";
|
||||
};
|
||||
PIO18: gpio@fe825000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x100>;
|
||||
st,bank-name = "PIO18";
|
||||
};
|
||||
|
|
@ -233,6 +342,77 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac0{
|
||||
pinctrl_mii0: mii0 {
|
||||
st,pins {
|
||||
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
|
||||
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
|
||||
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||||
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||||
|
||||
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
|
||||
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
|
||||
mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
|
||||
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||||
|
||||
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gmii0: gmii0 {
|
||||
st,pins {
|
||||
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
|
||||
mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
|
||||
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||||
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||||
|
||||
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||||
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||||
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||||
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||||
txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||||
txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||||
txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||||
txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||||
|
||||
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||||
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
|
||||
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
|
||||
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
|
||||
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||||
|
||||
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
|
||||
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
|
||||
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pin-controller-left {
|
||||
|
|
@ -240,23 +420,33 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih415-left-pinctrl";
|
||||
st,syscfg = <&syscfg_left>;
|
||||
reg = <0xfd6bf080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfd6b0000 0x3000>;
|
||||
|
||||
PIO100: gpio@fd6b0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO100";
|
||||
};
|
||||
PIO101: gpio@fd6b1000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO101";
|
||||
};
|
||||
PIO102: gpio@fd6b2000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO102";
|
||||
};
|
||||
|
|
@ -267,35 +457,49 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih415-right-pinctrl";
|
||||
st,syscfg = <&syscfg_right>;
|
||||
reg = <0xfd33f080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfd330000 0x5000>;
|
||||
|
||||
PIO103: gpio@fd330000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO103";
|
||||
};
|
||||
PIO104: gpio@fd331000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO104";
|
||||
};
|
||||
PIO105: gpio@fd332000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO105";
|
||||
};
|
||||
PIO106: gpio@fd333000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x100>;
|
||||
st,bank-name = "PIO106";
|
||||
};
|
||||
PIO107: gpio@fd334000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x100>;
|
||||
st,bank-name = "PIO107";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include "stih415-clock.dtsi"
|
||||
#include "stih415-pinctrl.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset-controller/stih415-resets.h>
|
||||
/ {
|
||||
|
||||
L2: cache-controller {
|
||||
|
|
@ -28,6 +29,16 @@
|
|||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
powerdown: powerdown-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "st,stih415-powerdown";
|
||||
};
|
||||
|
||||
softreset: softreset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "st,stih415-softreset";
|
||||
};
|
||||
|
||||
syscfg_sbc: sbc-syscfg@fe600000{
|
||||
compatible = "st,stih415-sbc-syscfg", "syscon";
|
||||
reg = <0xfe600000 0xb4>;
|
||||
|
|
@ -136,5 +147,64 @@
|
|||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet0: dwmac@fe810000 {
|
||||
device_type = "network";
|
||||
compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
|
||||
status = "disabled";
|
||||
|
||||
reg = <0xfe810000 0x8000>, <0x148 0x4>;
|
||||
reg-names = "stmmaceth", "sti-ethconf";
|
||||
|
||||
interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
||||
resets = <&softreset STIH415_ETH0_SOFTRESET>;
|
||||
reset-names = "stmmaceth";
|
||||
|
||||
snps,pbl = <32>;
|
||||
snps,mixed-burst;
|
||||
snps,force_sf_dma_mode;
|
||||
|
||||
st,syscon = <&syscfg_rear>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mii0>;
|
||||
clock-names = "stmmaceth";
|
||||
clocks = <&CLKS_GMAC0_PHY>;
|
||||
};
|
||||
|
||||
ethernet1: dwmac@fef08000 {
|
||||
device_type = "network";
|
||||
compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
|
||||
status = "disabled";
|
||||
reg = <0xfef08000 0x8000>, <0x74 0x4>;
|
||||
reg-names = "stmmaceth", "sti-ethconf";
|
||||
interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
||||
|
||||
snps,pbl = <32>;
|
||||
snps,mixed-burst;
|
||||
snps,force_sf_dma_mode;
|
||||
|
||||
st,syscon = <&syscfg_sbc>;
|
||||
|
||||
resets = <&softreset STIH415_ETH1_SOFTRESET>;
|
||||
reset-names = "stmmaceth";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mii1>;
|
||||
clock-names = "stmmaceth";
|
||||
clocks = <&CLKS_ETH1_PHY>;
|
||||
};
|
||||
|
||||
rc: rc@fe518000 {
|
||||
compatible = "st,comms-irb";
|
||||
reg = <0xfe518000 0x234>;
|
||||
interrupts = <0 203 0>;
|
||||
clocks = <&CLK_SYSIN>;
|
||||
rx-mode = "infrared";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ir>;
|
||||
resets = <&softreset STIH415_IRB_SOFTRESET>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,5 +37,19 @@
|
|||
clock-frequency = <100000000>;
|
||||
clock-output-names = "CLK_S_ICN_REG_0";
|
||||
};
|
||||
|
||||
CLK_S_GMAC0_PHY: clockgenA1@7 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "CLK_S_GMAC0_PHY";
|
||||
};
|
||||
|
||||
CLK_S_ETH1_PHY: clockgenA0@7 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "CLK_S_ETH1_PHY";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
* publishhed by the Free Software Foundation.
|
||||
*/
|
||||
#include "st-pincfg.h"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
/ {
|
||||
|
||||
aliases {
|
||||
|
|
@ -49,46 +50,69 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih416-sbc-pinctrl";
|
||||
st,syscfg = <&syscfg_sbc>;
|
||||
reg = <0xfe61f080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfe610000 0x6000>;
|
||||
|
||||
PIO0: gpio@fe610000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO0";
|
||||
};
|
||||
PIO1: gpio@fe611000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO1";
|
||||
};
|
||||
PIO2: gpio@fe612000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO2";
|
||||
};
|
||||
PIO3: gpio@fe613000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x100>;
|
||||
st,bank-name = "PIO3";
|
||||
};
|
||||
PIO4: gpio@fe614000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x100>;
|
||||
st,bank-name = "PIO4";
|
||||
};
|
||||
PIO40: gpio@fe615000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x100>;
|
||||
st,bank-name = "PIO40";
|
||||
st,retime-pin-mask = <0x7f>;
|
||||
};
|
||||
|
||||
rc{
|
||||
pinctrl_ir: ir0 {
|
||||
st,pins {
|
||||
ir = <&PIO4 0 ALT2 IN>;
|
||||
};
|
||||
};
|
||||
};
|
||||
sbc_serial1 {
|
||||
pinctrl_sbc_serial1: sbc_serial1 {
|
||||
st,pins {
|
||||
|
|
@ -115,6 +139,58 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac1 {
|
||||
pinctrl_mii1: mii1 {
|
||||
st,pins {
|
||||
txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
|
||||
col = <&PIO0 7 ALT1 IN BYPASS 1000>;
|
||||
|
||||
mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
|
||||
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
|
||||
crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
|
||||
mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
|
||||
rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
||||
|
||||
rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
|
||||
phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
|
||||
};
|
||||
};
|
||||
pinctrl_rgmii1: rgmii1-0 {
|
||||
st,pins {
|
||||
txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
|
||||
txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
|
||||
txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
|
||||
txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
|
||||
txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
|
||||
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
|
||||
|
||||
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
|
||||
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
|
||||
rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
|
||||
rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
|
||||
rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
|
||||
rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
|
||||
|
||||
rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
|
||||
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
|
||||
phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
|
||||
|
||||
clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pin-controller-front {
|
||||
|
|
@ -122,65 +198,89 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih416-front-pinctrl";
|
||||
st,syscfg = <&syscfg_front>;
|
||||
reg = <0xfee0f080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfee00000 0x10000>;
|
||||
|
||||
PIO5: gpio@fee00000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO5";
|
||||
};
|
||||
PIO6: gpio@fee01000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO6";
|
||||
};
|
||||
PIO7: gpio@fee02000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO7";
|
||||
};
|
||||
PIO8: gpio@fee03000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x100>;
|
||||
st,bank-name = "PIO8";
|
||||
};
|
||||
PIO9: gpio@fee04000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x100>;
|
||||
st,bank-name = "PIO9";
|
||||
};
|
||||
PIO10: gpio@fee05000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x100>;
|
||||
st,bank-name = "PIO10";
|
||||
};
|
||||
PIO11: gpio@fee06000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x100>;
|
||||
st,bank-name = "PIO11";
|
||||
};
|
||||
PIO12: gpio@fee07000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x100>;
|
||||
st,bank-name = "PIO12";
|
||||
};
|
||||
PIO30: gpio@fee08000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x100>;
|
||||
st,bank-name = "PIO30";
|
||||
};
|
||||
PIO31: gpio@fee09000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x9000 0x100>;
|
||||
st,bank-name = "PIO31";
|
||||
};
|
||||
|
|
@ -217,41 +317,57 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih416-rear-pinctrl";
|
||||
st,syscfg = <&syscfg_rear>;
|
||||
reg = <0xfe82f080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfe820000 0x6000>;
|
||||
|
||||
PIO13: gpio@fe820000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO13";
|
||||
};
|
||||
PIO14: gpio@fe821000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO14";
|
||||
};
|
||||
PIO15: gpio@fe822000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO15";
|
||||
};
|
||||
PIO16: gpio@fe823000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x100>;
|
||||
st,bank-name = "PIO16";
|
||||
};
|
||||
PIO17: gpio@fe824000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x100>;
|
||||
st,bank-name = "PIO17";
|
||||
};
|
||||
PIO18: gpio@fe825000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x100>;
|
||||
st,bank-name = "PIO18";
|
||||
st,retime-pin-mask = <0xf>;
|
||||
|
|
@ -265,6 +381,63 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac0 {
|
||||
pinctrl_mii0: mii0 {
|
||||
st,pins {
|
||||
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
|
||||
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||||
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||||
|
||||
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||||
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
|
||||
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
|
||||
mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
|
||||
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||||
|
||||
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||||
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gmii0: gmii0 {
|
||||
st,pins {
|
||||
};
|
||||
};
|
||||
pinctrl_rgmii0: rgmii0 {
|
||||
st,pins {
|
||||
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
|
||||
txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
|
||||
txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
|
||||
txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
|
||||
txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
|
||||
txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
|
||||
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
|
||||
mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
|
||||
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||||
|
||||
rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
|
||||
rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
|
||||
rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
|
||||
rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
|
||||
rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
|
||||
rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
||||
|
||||
clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pin-controller-fvdp-fe {
|
||||
|
|
@ -272,23 +445,33 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih416-fvdp-fe-pinctrl";
|
||||
st,syscfg = <&syscfg_fvdp_fe>;
|
||||
reg = <0xfd6bf080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfd6b0000 0x3000>;
|
||||
|
||||
PIO100: gpio@fd6b0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO100";
|
||||
};
|
||||
PIO101: gpio@fd6b1000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO101";
|
||||
};
|
||||
PIO102: gpio@fd6b2000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO102";
|
||||
};
|
||||
|
|
@ -299,29 +482,41 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stih416-fvdp-lite-pinctrl";
|
||||
st,syscfg = <&syscfg_fvdp_lite>;
|
||||
reg = <0xfd33f080 0x4>;
|
||||
reg-names = "irqmux";
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-names = "irqmux";
|
||||
ranges = <0 0xfd330000 0x5000>;
|
||||
|
||||
PIO103: gpio@fd330000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x100>;
|
||||
st,bank-name = "PIO103";
|
||||
};
|
||||
PIO104: gpio@fd331000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x100>;
|
||||
st,bank-name = "PIO104";
|
||||
};
|
||||
PIO105: gpio@fd332000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x100>;
|
||||
st,bank-name = "PIO105";
|
||||
};
|
||||
PIO106: gpio@fd333000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x100>;
|
||||
st,bank-name = "PIO106";
|
||||
};
|
||||
|
|
@ -329,6 +524,8 @@
|
|||
PIO107: gpio@fd334000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x100>;
|
||||
st,bank-name = "PIO107";
|
||||
st,retime-pin-mask = <0xf>;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include "stih416-clock.dtsi"
|
||||
#include "stih416-pinctrl.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset-controller/stih416-resets.h>
|
||||
/ {
|
||||
L2: cache-controller {
|
||||
compatible = "arm,pl310-cache";
|
||||
|
|
@ -27,6 +28,16 @@
|
|||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
powerdown: powerdown-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "st,stih416-powerdown";
|
||||
};
|
||||
|
||||
softreset: softreset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "st,stih416-softreset";
|
||||
};
|
||||
|
||||
syscfg_sbc:sbc-syscfg@fe600000{
|
||||
compatible = "st,stih416-sbc-syscfg", "syscon";
|
||||
reg = <0xfe600000 0x1000>;
|
||||
|
|
@ -145,5 +156,61 @@
|
|||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet0: dwmac@fe810000 {
|
||||
device_type = "network";
|
||||
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
|
||||
status = "disabled";
|
||||
reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
|
||||
reg-names = "stmmaceth", "sti-ethconf";
|
||||
|
||||
interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
||||
|
||||
snps,pbl = <32>;
|
||||
snps,mixed-burst;
|
||||
|
||||
st,syscon = <&syscfg_rear>;
|
||||
resets = <&softreset STIH416_ETH0_SOFTRESET>;
|
||||
reset-names = "stmmaceth";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mii0>;
|
||||
clock-names = "stmmaceth";
|
||||
clocks = <&CLK_S_GMAC0_PHY>;
|
||||
};
|
||||
|
||||
ethernet1: dwmac@fef08000 {
|
||||
device_type = "network";
|
||||
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
|
||||
status = "disabled";
|
||||
reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
|
||||
reg-names = "stmmaceth", "sti-ethconf";
|
||||
interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
||||
|
||||
snps,pbl = <32>;
|
||||
snps,mixed-burst;
|
||||
|
||||
st,syscon = <&syscfg_sbc>;
|
||||
|
||||
resets = <&softreset STIH416_ETH1_SOFTRESET>;
|
||||
reset-names = "stmmaceth";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mii1>;
|
||||
clock-names = "stmmaceth";
|
||||
clocks = <&CLK_S_ETH1_PHY>;
|
||||
};
|
||||
|
||||
rc: rc@fe518000 {
|
||||
compatible = "st,comms-irb";
|
||||
reg = <0xfe518000 0x234>;
|
||||
interrupts = <0 203 0>;
|
||||
rx-mode = "infrared";
|
||||
clocks = <&CLK_SYSIN>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ir>;
|
||||
resets = <&softreset STIH416_IRB_SOFTRESET>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
|
||||
aliases {
|
||||
ttyAS0 = &serial2;
|
||||
ethernet0 = ðernet0;
|
||||
ethernet1 = ðernet1;
|
||||
};
|
||||
|
||||
soc {
|
||||
|
|
@ -46,5 +48,25 @@
|
|||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet0: dwmac@fe810000 {
|
||||
status = "okay";
|
||||
phy-mode = "mii";
|
||||
pinctrl-0 = <&pinctrl_mii0>;
|
||||
|
||||
snps,reset-gpio = <&PIO106 2>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 10000>;
|
||||
};
|
||||
|
||||
ethernet1: dwmac@fef08000 {
|
||||
status = "disabled";
|
||||
phy-mode = "mii";
|
||||
st,tx-retime-src = "txclk";
|
||||
|
||||
snps,reset-gpio = <&PIO4 7>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
aliases {
|
||||
ttyAS0 = &sbc_serial1;
|
||||
ethernet1 = ðernet1;
|
||||
};
|
||||
soc {
|
||||
sbc_serial1: serial@fe531000 {
|
||||
|
|
@ -60,5 +61,17 @@
|
|||
i2c@fe541000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet1: dwmac@fef08000 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
st,tx-retime-src = "clk_125";
|
||||
snps,reset-gpio = <&PIO3 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 10000>;
|
||||
|
||||
pinctrl-0 = <&pinctrl_rgmii1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This header provides constants for the reset controller
|
||||
* based peripheral powerdown requests on the STMicroelectronics
|
||||
* STiH415 SoC.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
|
||||
|
||||
#define STIH415_EMISS_POWERDOWN 0
|
||||
#define STIH415_NAND_POWERDOWN 1
|
||||
#define STIH415_KEYSCAN_POWERDOWN 2
|
||||
#define STIH415_USB0_POWERDOWN 3
|
||||
#define STIH415_USB1_POWERDOWN 4
|
||||
#define STIH415_USB2_POWERDOWN 5
|
||||
#define STIH415_SATA0_POWERDOWN 6
|
||||
#define STIH415_SATA1_POWERDOWN 7
|
||||
#define STIH415_PCIE_POWERDOWN 8
|
||||
|
||||
#define STIH415_ETH0_SOFTRESET 0
|
||||
#define STIH415_ETH1_SOFTRESET 1
|
||||
#define STIH415_IRB_SOFTRESET 2
|
||||
#define STIH415_USB0_SOFTRESET 3
|
||||
#define STIH415_USB1_SOFTRESET 4
|
||||
#define STIH415_USB2_SOFTRESET 5
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* This header provides constants for the reset controller
|
||||
* based peripheral powerdown requests on the STMicroelectronics
|
||||
* STiH416 SoC.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
|
||||
|
||||
#define STIH416_EMISS_POWERDOWN 0
|
||||
#define STIH416_NAND_POWERDOWN 1
|
||||
#define STIH416_KEYSCAN_POWERDOWN 2
|
||||
#define STIH416_USB0_POWERDOWN 3
|
||||
#define STIH416_USB1_POWERDOWN 4
|
||||
#define STIH416_USB2_POWERDOWN 5
|
||||
#define STIH416_USB3_POWERDOWN 6
|
||||
#define STIH416_SATA0_POWERDOWN 7
|
||||
#define STIH416_SATA1_POWERDOWN 8
|
||||
#define STIH416_PCIE0_POWERDOWN 9
|
||||
#define STIH416_PCIE1_POWERDOWN 10
|
||||
|
||||
#define STIH416_ETH0_SOFTRESET 0
|
||||
#define STIH416_ETH1_SOFTRESET 1
|
||||
#define STIH416_IRB_SOFTRESET 2
|
||||
#define STIH416_USB0_SOFTRESET 3
|
||||
#define STIH416_USB1_SOFTRESET 4
|
||||
#define STIH416_USB2_SOFTRESET 5
|
||||
#define STIH416_USB3_SOFTRESET 6
|
||||
#define STIH416_SATA0_SOFTRESET 7
|
||||
#define STIH416_SATA1_SOFTRESET 8
|
||||
#define STIH416_PCIE0_SOFTRESET 9
|
||||
#define STIH416_PCIE1_SOFTRESET 10
|
||||
#define STIH416_AUD_DAC_SOFTRESET 11
|
||||
#define STIH416_HDTVOUT_SOFTRESET 12
|
||||
#define STIH416_VTAC_M_RX_SOFTRESET 13
|
||||
#define STIH416_VTAC_A_RX_SOFTRESET 14
|
||||
#define STIH416_SYNC_HD_SOFTRESET 15
|
||||
#define STIH416_SYNC_SD_SOFTRESET 16
|
||||
#define STIH416_BLITTER_SOFTRESET 17
|
||||
#define STIH416_GPU_SOFTRESET 18
|
||||
#define STIH416_VTAC_M_TX_SOFTRESET 19
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#define STIH416_VTAC_A_TX_SOFTRESET 20
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#define STIH416_VTG_AUX_SOFTRESET 21
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#define STIH416_JPEG_DEC_SOFTRESET 22
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#define STIH416_HVA_SOFTRESET 23
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#define STIH416_COMPO_M_SOFTRESET 24
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#define STIH416_COMPO_A_SOFTRESET 25
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#define STIH416_VP8_DEC_SOFTRESET 26
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#define STIH416_VTG_MAIN_SOFTRESET 27
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
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