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ARM: dts: amlogic updates for v5.9 

- power-domain and MMC updates
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Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

ARM: dts: amlogic updates for v5.9
- power-domain and MMC updates

* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: dts: meson8b: odroidc1: enable the SDHC controller
  ARM: dts: meson8b: ec100: enable the SDHC controller
  ARM: dts: meson: add the SDHC MMC controller
  ARM: dts: meson8b: add power domain controller
  ARM: dts: meson8m2: add resets for the power domain controller
  ARM: dts: meson8: add power domain controller

Link: https://lore.kernel.org/r/7hd04uf2o8.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-07-17 19:57:03 +02:00
Родитель 6760a29c88 d6a3873c7b
Коммит a0660529ac
6 изменённых файлов: 160 добавлений и 0 удалений
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7
arch/arm/boot/dts/meson.dtsi
Просмотреть файл

@ -140,6 +140,13 @@
status = "disabled";
};
sdhc: mmc@8e00 {
compatible = "amlogic,meson-mx-sdhc";
reg = <0x8e00 0x42>;
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
gpio_intc: interrupt-controller@9880 {
compatible = "amlogic,meson-gpio-intc";
reg = <0x9880 0x10>;

32
arch/arm/boot/dts/meson8.dtsi
Просмотреть файл

@ -6,6 +6,7 @@
#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include "meson.dtsi"
@ -385,6 +386,15 @@
};
};
sdxc_b_pins: sdxc-b {
mux {
groups = "sdxc_d0_b", "sdxc_d13_b",
"sdxc_clk_b", "sdxc_cmd_b";
function = "sdxc_b";
bias-pull-up;
};
};
spi_nor_pins: nor {
mux {
groups = "nor_d", "nor_q", "nor_c", "nor_cs";
@ -454,6 +464,8 @@
&ethmac {
clocks = <&clkc CLKID_ETH>;
clock-names = "stmmaceth";
power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
};
&gpio_intc {
@ -469,6 +481,16 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
pwrc: power-controller {
compatible = "amlogic,meson8-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&pmu>;
clocks = <&clkc CLKID_VPU>;
clock-names = "vpu";
assigned-clocks = <&clkc CLKID_VPU>;
assigned-clock-rates = <364285714>;
};
};
&hwrng {
@ -547,6 +569,16 @@
nvmem-cell-names = "temperature_calib";
};
&sdhc {
compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
clocks = <&xtal>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_SDHC>;
clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
};
&sdio {
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;

25
arch/arm/boot/dts/meson8b-ec100.dts
Просмотреть файл

@ -27,6 +27,11 @@
reg = <0x40000000 0x40000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
gpio-keys {
compatible = "gpio-keys-polled";
#address-cells = <1>;
@ -299,6 +304,26 @@
vref-supply = <&vcc_1v8>;
};
&sdhc {
status = "okay";
pinctrl-0 = <&sdxc_c_pins>;
pinctrl-names = "default";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
disable-wp;
non-removable;
no-sdio;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_3v3>;
};
&sdio {
status = "okay";

26
arch/arm/boot/dts/meson8b-odroidc1.dts
Просмотреть файл

@ -15,6 +15,7 @@
aliases {
serial0 = &uart_AO;
mmc0 = &sd_card_slot;
mmc1 = &sdhc;
};
chosen {
@ -26,6 +27,11 @@
reg = <0x40000000 0x40000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
blue {
@ -310,6 +316,26 @@
vref-supply = <&vcc_1v8>;
};
&sdhc {
status = "okay";
pinctrl-0 = <&sdxc_c_pins>;
pinctrl-names = "default";
bus-width = <8>;
max-frequency = <100000000>;
disable-wp;
cap-mmc-highspeed;
mmc-hs200-1_8v;
no-sdio;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
};
&sdio {
status = "okay";

47
arch/arm/boot/dts/meson8b.dtsi
Просмотреть файл

@ -7,6 +7,7 @@
#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include "meson.dtsi"
@ -362,6 +363,16 @@
};
};
sdxc_c_pins: sdxc-c {
mux {
groups = "sdxc_d0_c", "sdxc_d13_c",
"sdxc_d47_c", "sdxc_clk_c",
"sdxc_cmd_c";
function = "sdxc_c";
bias-pull-up;
};
};
pwm_c1_pins: pwm-c1 {
mux {
groups = "pwm_c1";
@ -433,6 +444,8 @@
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
};
&gpio_intc {
@ -449,6 +462,30 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
pwrc: power-controller {
compatible = "amlogic,meson8b-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&pmu>;
resets = <&reset RESET_DBLK>,
<&reset RESET_PIC_DC>,
<&reset RESET_HDMI_APB>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC_4>,
<&reset RESET_VENCL>,
<&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_RDMA>;
reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
"venci", "vencp", "vdac", "vencl", "viu",
"venc", "rdma";
clocks = <&clkc CLKID_VPU>;
clock-names = "vpu";
assigned-clocks = <&clkc CLKID_VPU>;
assigned-clock-rates = <182142857>;
};
};
&hwrng {
@ -527,6 +564,16 @@
nvmem-cell-names = "temperature_calib";
};
&sdhc {
compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
clocks = <&xtal>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_SDHC>;
clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
};
&sdio {
compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;

23
arch/arm/boot/dts/meson8m2.dtsi
Просмотреть файл

@ -61,10 +61,33 @@
};
};
&pwrc {
compatible = "amlogic,meson8m2-pwrc";
resets = <&reset RESET_DBLK>,
<&reset RESET_PIC_DC>,
<&reset RESET_HDMI_APB>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC_4>,
<&reset RESET_VENCL>,
<&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_RDMA>;
reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
"vencp", "vdac", "vencl", "viu", "venc", "rdma";
assigned-clocks = <&clkc CLKID_VPU>;
assigned-clock-rates = <364000000>;
};
&saradc {
compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
};
&sdhc {
compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
};
&usb0_phy {
compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
};