[PATCH] S2io: New link handling scheme for Xframe II
Hi, The below patch implements a new "Link state change handling" scheme supported by the Xframe II adapter. It also bumps up the driver version to 2.0.2.0. Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com> Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
raghavendra.koushik@neterion.com
Jeff Garzik
Родитель
b6e3f9828b
Коммит
a371a07de9
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@ -167,7 +167,11 @@ typedef struct _XENA_dev_config {
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u8 unused4[0x08];
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u64 gpio_int_reg;
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#define GPIO_INT_REG_LINK_DOWN BIT(1)
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#define GPIO_INT_REG_LINK_UP BIT(2)
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u64 gpio_int_mask;
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#define GPIO_INT_MASK_LINK_DOWN BIT(1)
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#define GPIO_INT_MASK_LINK_UP BIT(2)
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u64 gpio_alarms;
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u8 unused5[0x38];
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@ -279,8 +283,10 @@ typedef struct _XENA_dev_config {
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u64 gpio_control;
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#define GPIO_CTRL_GPIO_0 BIT(8)
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u64 misc_control;
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#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
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u8 unused7_1[0x240 - 0x200];
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u8 unused7_1[0x240 - 0x208];
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u64 wreq_split_mask;
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#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
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@ -67,7 +67,7 @@
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/* S2io Driver name & version. */
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static char s2io_driver_name[] = "Neterion";
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static char s2io_driver_version[] = "Version 1.7.7";
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static char s2io_driver_version[] = "Version 2.0.2.0";
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static inline int RXD_IS_UP2DT(RxD_t *rxdp)
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{
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@ -1456,8 +1456,28 @@ static int init_nic(struct s2io_nic *nic)
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writeq(val64, &bar0->wreq_split_mask);
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}
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/* Setting Link stability period to 64 ms */
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if (nic->device_type == XFRAME_II_DEVICE) {
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val64 = MISC_LINK_STABILITY_PRD(3);
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writeq(val64, &bar0->misc_control);
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}
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return SUCCESS;
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}
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#define LINK_UP_DOWN_INTERRUPT 1
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#define MAC_RMAC_ERR_TIMER 2
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#if defined(CONFIG_MSI_MODE) || defined(CONFIG_MSIX_MODE)
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#define s2io_link_fault_indication(x) MAC_RMAC_ERR_TIMER
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#else
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int s2io_link_fault_indication(nic_t *nic)
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{
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if (nic->device_type == XFRAME_II_DEVICE)
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return LINK_UP_DOWN_INTERRUPT;
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else
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return MAC_RMAC_ERR_TIMER;
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}
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#endif
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/**
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* en_dis_able_nic_intrs - Enable or Disable the interrupts
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@ -1485,11 +1505,22 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
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temp64 &= ~((u64) val64);
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writeq(temp64, &bar0->general_int_mask);
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/*
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* Disabled all PCIX, Flash, MDIO, IIC and GPIO
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* If Hercules adapter enable GPIO otherwise
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* disabled all PCIX, Flash, MDIO, IIC and GPIO
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* interrupts for now.
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* TODO
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*/
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writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
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if (s2io_link_fault_indication(nic) ==
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LINK_UP_DOWN_INTERRUPT ) {
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temp64 = readq(&bar0->pic_int_mask);
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temp64 &= ~((u64) PIC_INT_GPIO);
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writeq(temp64, &bar0->pic_int_mask);
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temp64 = readq(&bar0->gpio_int_mask);
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temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
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writeq(temp64, &bar0->gpio_int_mask);
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} else {
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writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
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}
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/*
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* No MSI Support is available presently, so TTI and
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* RTI interrupts are also disabled.
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@ -1580,17 +1611,8 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
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writeq(temp64, &bar0->general_int_mask);
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/*
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* All MAC block error interrupts are disabled for now
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* except the link status change interrupt.
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* TODO
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*/
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val64 = MAC_INT_STATUS_RMAC_INT;
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temp64 = readq(&bar0->mac_int_mask);
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temp64 &= ~((u64) val64);
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writeq(temp64, &bar0->mac_int_mask);
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val64 = readq(&bar0->mac_rmac_err_mask);
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val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
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writeq(val64, &bar0->mac_rmac_err_mask);
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} else if (flag == DISABLE_INTRS) {
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/*
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* Disable MAC Intrs in the general intr mask register
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@ -1879,8 +1901,10 @@ static int start_nic(struct s2io_nic *nic)
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}
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/* Enable select interrupts */
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interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
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RX_MAC_INTR | MC_INTR;
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interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | MC_INTR;
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interruptible |= TX_PIC_INTR | RX_PIC_INTR;
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interruptible |= TX_MAC_INTR | RX_MAC_INTR;
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en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
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/*
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@ -2004,8 +2028,9 @@ static void stop_nic(struct s2io_nic *nic)
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config = &nic->config;
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/* Disable all interrupts */
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interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
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RX_MAC_INTR | MC_INTR;
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interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | MC_INTR;
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interruptible |= TX_PIC_INTR | RX_PIC_INTR;
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interruptible |= TX_MAC_INTR | RX_MAC_INTR;
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en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
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/* Disable PRCs */
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@ -2618,10 +2643,12 @@ static void alarm_intr_handler(struct s2io_nic *nic)
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register u64 val64 = 0, err_reg = 0;
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/* Handling link status change error Intr */
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err_reg = readq(&bar0->mac_rmac_err_reg);
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writeq(err_reg, &bar0->mac_rmac_err_reg);
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if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
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schedule_work(&nic->set_link_task);
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if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
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err_reg = readq(&bar0->mac_rmac_err_reg);
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writeq(err_reg, &bar0->mac_rmac_err_reg);
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if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
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schedule_work(&nic->set_link_task);
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}
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}
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/* Handling Ecc errors */
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@ -2947,7 +2974,7 @@ int s2io_open(struct net_device *dev)
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* Nic is initialized
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*/
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netif_carrier_off(dev);
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sp->last_link_state = 0; /* Unkown link state */
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sp->last_link_state = LINK_DOWN;
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/* Initialize H/W and enable interrupts */
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if (s2io_card_up(sp)) {
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@ -3159,6 +3186,53 @@ s2io_alarm_handle(unsigned long data)
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mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
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}
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static void s2io_txpic_intr_handle(nic_t *sp)
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{
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XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
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u64 val64;
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val64 = readq(&bar0->pic_int_status);
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if (val64 & PIC_INT_GPIO) {
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val64 = readq(&bar0->gpio_int_reg);
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if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
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(val64 & GPIO_INT_REG_LINK_UP)) {
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val64 |= GPIO_INT_REG_LINK_DOWN;
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val64 |= GPIO_INT_REG_LINK_UP;
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writeq(val64, &bar0->gpio_int_reg);
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goto masking;
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}
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if (((sp->last_link_state == LINK_UP) &&
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(val64 & GPIO_INT_REG_LINK_DOWN)) ||
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((sp->last_link_state == LINK_DOWN) &&
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(val64 & GPIO_INT_REG_LINK_UP))) {
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val64 = readq(&bar0->gpio_int_mask);
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val64 |= GPIO_INT_MASK_LINK_DOWN;
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val64 |= GPIO_INT_MASK_LINK_UP;
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writeq(val64, &bar0->gpio_int_mask);
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s2io_set_link((unsigned long)sp);
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}
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masking:
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if (sp->last_link_state == LINK_UP) {
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/*enable down interrupt */
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val64 = readq(&bar0->gpio_int_mask);
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/* unmasks link down intr */
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val64 &= ~GPIO_INT_MASK_LINK_DOWN;
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/* masks link up intr */
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val64 |= GPIO_INT_MASK_LINK_UP;
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writeq(val64, &bar0->gpio_int_mask);
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} else {
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/*enable UP Interrupt */
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val64 = readq(&bar0->gpio_int_mask);
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/* unmasks link up interrupt */
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val64 &= ~GPIO_INT_MASK_LINK_UP;
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/* masks link down interrupt */
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val64 |= GPIO_INT_MASK_LINK_DOWN;
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writeq(val64, &bar0->gpio_int_mask);
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}
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}
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}
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/**
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* s2io_isr - ISR handler of the device .
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* @irq: the irq of the device.
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@ -3241,6 +3315,8 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
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tx_intr_handler(&mac_control->fifos[i]);
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}
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if (reason & GEN_INTR_TXPIC)
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s2io_txpic_intr_handle(sp);
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/*
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* If the Rx buffer count is below the panic threshold then
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* reallocate the buffers from the interrupt handler itself,
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@ -4644,11 +4720,13 @@ static void s2io_set_link(unsigned long data)
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}
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subid = nic->pdev->subsystem_device;
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/*
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* Allow a small delay for the NICs self initiated
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* cleanup to complete.
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*/
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msleep(100);
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if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
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/*
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* Allow a small delay for the NICs self initiated
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* cleanup to complete.
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*/
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msleep(100);
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}
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val64 = readq(&bar0->adapter_status);
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if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
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@ -4666,13 +4744,16 @@ static void s2io_set_link(unsigned long data)
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val64 |= ADAPTER_LED_ON;
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writeq(val64, &bar0->adapter_control);
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}
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val64 = readq(&bar0->adapter_status);
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if (!LINK_IS_UP(val64)) {
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DBG_PRINT(ERR_DBG, "%s:", dev->name);
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DBG_PRINT(ERR_DBG, " Link down");
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DBG_PRINT(ERR_DBG, "after ");
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DBG_PRINT(ERR_DBG, "enabling ");
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DBG_PRINT(ERR_DBG, "device \n");
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if (s2io_link_fault_indication(nic) ==
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MAC_RMAC_ERR_TIMER) {
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val64 = readq(&bar0->adapter_status);
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if (!LINK_IS_UP(val64)) {
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DBG_PRINT(ERR_DBG, "%s:", dev->name);
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DBG_PRINT(ERR_DBG, " Link down");
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DBG_PRINT(ERR_DBG, "after ");
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DBG_PRINT(ERR_DBG, "enabling ");
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DBG_PRINT(ERR_DBG, "device \n");
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}
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}
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if (nic->device_enabled_once == FALSE) {
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nic->device_enabled_once = TRUE;
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