ARM: footbridge: remove addin mode
This does not appear to have been used in many years, we can
kill off some of the uglier code.
Among other things, it avoids a randconfig issue when both modes
are disabled:
arch/arm/mach-footbridge/common.c:149:24: error: 'ebsa285_host_io_desc' defined but not used [-Werror=unused-variable]
149 | static struct map_desc ebsa285_host_io_desc[] __initdata = {
| ^~~~~~~~~~~~~~~~~~~~
arch/arm/mach-footbridge/common.c:136:24: error: 'fb_common_io_desc' defined but not used [-Werror=unused-variable]
136 | static struct map_desc fb_common_io_desc[] __initdata = {
| ^~~~~~~~~~~~~~~~~
The recently added phys_to_dma() functions are now trivial and
could probably be removed again as a follow-up, if anyone knows
how.
Cc: Christoph Hellwig <hch@lst.de>
Tested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Родитель
568035b01c
Коммит
b519c9c7e6
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@ -81,19 +81,6 @@
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#define SA110_CNTL_XCSDIR(x) ((x)<<28)
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#define SA110_CNTL_PCICFN (1 << 31)
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/*
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* footbridge_cfn_mode() is used when we want
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* to check whether we are the central function
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*/
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#define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
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#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
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#define footbridge_cfn_mode() __footbridge_cfn_mode()
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#elif defined(CONFIG_FOOTBRIDGE_HOST)
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#define footbridge_cfn_mode() (1)
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#else
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#define footbridge_cfn_mode() (0)
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#endif
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#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
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#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
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#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
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@ -8,31 +8,17 @@ config ARCH_CATS
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depends on UNUSED_BOARD_FILES
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select CLKEVT_I8253
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select CLKSRC_I8253
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select FOOTBRIDGE_HOST
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select ISA
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select ISA_DMA
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select FORCE_PCI
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help
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Say Y here if you intend to run this kernel on the CATS.
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Saying N will reduce the size of the Footbridge kernel.
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config ARCH_EBSA285_ADDIN
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bool "EBSA285 (addin mode)"
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select ARCH_EBSA285
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select FOOTBRIDGE_ADDIN
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help
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Say Y here if you intend to run this kernel on the EBSA285 card
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in addin mode.
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Saying N will reduce the size of the Footbridge kernel.
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config ARCH_EBSA285_HOST
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bool "EBSA285 (host mode)"
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select ARCH_EBSA285
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select FOOTBRIDGE_HOST
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select ISA
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select ISA_DMA
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select ARCH_MAY_HAVE_PC_FDC
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select FORCE_PCI
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help
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@ -45,9 +31,7 @@ config ARCH_NETWINDER
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bool "NetWinder"
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select CLKEVT_I8253
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select CLKSRC_I8253
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select FOOTBRIDGE_HOST
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select ISA
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select ISA_DMA
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select FORCE_PCI
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help
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Say Y here if you intend to run this kernel on the Rebel.COM
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@ -61,19 +45,11 @@ endmenu
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# Footbridge support
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config FOOTBRIDGE
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def_bool y
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select ARCH_HAS_PHYS_TO_DMA
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bool
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# Footbridge in host mode
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config FOOTBRIDGE_HOST
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bool
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select ARCH_MIGHT_HAVE_PC_SERIO
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select ISA_DMA
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# Footbridge in addin mode
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config FOOTBRIDGE_ADDIN
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bool
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# EBSA285 board in either host or addin mode
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config ARCH_EBSA285
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bool
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@ -9,7 +9,7 @@ obj-y := common.o dma.o isa-irq.o
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pci-y += dc21285.o
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pci-$(CONFIG_ARCH_CATS) += cats-pci.o
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pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
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pci-$(CONFIG_ARCH_EBSA285) += ebsa285-pci.o
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pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
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obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
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@ -198,9 +198,6 @@ void __init footbridge_init_irq(void)
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__fb_init_irq();
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if (!footbridge_cfn_mode())
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return;
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if (machine_is_ebsa285())
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/* The following is dependent on which slot
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* you plug the Southbridge card into. We
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@ -221,21 +218,13 @@ void __init footbridge_init_irq(void)
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* commented out since there is a "No Fix" problem with it. Not mapping
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* it means that we have extra bullet protection on our feet.
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*/
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static struct map_desc fb_common_io_desc[] __initdata = {
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static struct map_desc ebsa285_host_io_desc[] __initdata = {
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{
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.virtual = ARMCSR_BASE,
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.pfn = __phys_to_pfn(DC21285_ARMCSR_BASE),
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.length = ARMCSR_SIZE,
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.type = MT_DEVICE,
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}
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};
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/*
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* The mapping when the footbridge is in host mode. We don't map any of
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* this when we are in add-in mode.
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*/
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static struct map_desc ebsa285_host_io_desc[] __initdata = {
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#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
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},
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{
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.virtual = PCIMEM_BASE,
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.pfn = __phys_to_pfn(DC21285_PCI_MEM),
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@ -257,26 +246,12 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
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.length = PCIIACK_SIZE,
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.type = MT_DEVICE,
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},
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#endif
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};
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void __init footbridge_map_io(void)
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{
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/*
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* Set up the common mapping first; we need this to
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* determine whether we're in host mode or not.
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*/
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iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
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/*
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* Now, work out what we've got to map in addition on this
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* platform.
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*/
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if (footbridge_cfn_mode()) {
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iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
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pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
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}
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iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
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pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
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vga_base = PCIMEM_BASE;
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}
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@ -307,48 +282,12 @@ void footbridge_restart(enum reboot_mode mode, const char *cmd)
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}
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}
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#ifdef CONFIG_FOOTBRIDGE_ADDIN
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static inline unsigned long fb_bus_sdram_offset(void)
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{
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return *CSR_PCISDRAMBASE & 0xfffffff0;
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}
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/*
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* These two functions convert virtual addresses to PCI addresses and PCI
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* addresses to virtual addresses. Note that it is only legal to use these
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* on memory obtained via get_zeroed_page or kmalloc.
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*/
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unsigned long __virt_to_bus(unsigned long res)
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{
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WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
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return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
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}
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EXPORT_SYMBOL(__virt_to_bus);
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unsigned long __bus_to_virt(unsigned long res)
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{
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res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
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WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
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return res;
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}
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EXPORT_SYMBOL(__bus_to_virt);
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#else
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static inline unsigned long fb_bus_sdram_offset(void)
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{
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return BUS_OFFSET;
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}
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#endif /* CONFIG_FOOTBRIDGE_ADDIN */
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dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr + (fb_bus_sdram_offset() - PHYS_OFFSET);
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return paddr + (BUS_OFFSET - PHYS_OFFSET);
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}
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phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
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{
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return dev_addr - (fb_bus_sdram_offset() - PHYS_OFFSET);
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return dev_addr - (BUS_OFFSET - PHYS_OFFSET);
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}
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@ -245,9 +245,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
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{
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struct resource *res;
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if (nr || !footbridge_cfn_mode())
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return 0;
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res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
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if (!res) {
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printk("out of memory for root bus resources");
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@ -278,7 +275,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
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void __init dc21285_preinit(void)
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{
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unsigned int mem_size, mem_mask;
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int cfn_mode;
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pcibios_min_mem = 0x81000000;
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@ -298,21 +294,15 @@ void __init dc21285_preinit(void)
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*CSR_CSRBASEOFFSET = 0;
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*CSR_PCIADDR_EXTN = 0;
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cfn_mode = __footbridge_cfn_mode();
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printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
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"%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
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"central function" : "addin");
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"central function mode\n", *CSR_CLASSREV & 0xff);
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if (footbridge_cfn_mode()) {
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/*
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* Clear any existing errors - we aren't
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* interested in historical data...
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*/
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*CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
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SA110_CNTL_RXSERR;
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*CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
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}
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/*
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* Clear any existing errors - we aren't
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* interested in historical data...
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*/
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*CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | SA110_CNTL_RXSERR;
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*CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
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timer_setup(&serr_timer, dc21285_enable_error, 0);
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timer_setup(&perr_timer, dc21285_enable_error, 0);
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@ -331,29 +321,18 @@ void __init dc21285_preinit(void)
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dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
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"PCI data parity", NULL);
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if (cfn_mode) {
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/*
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* Map our SDRAM at a known address in PCI space, just in case
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* the firmware had other ideas. Using a nonzero base is
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* necessary, since some VGA cards forcefully use PCI addresses
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* in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
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*/
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*CSR_PCICSRBASE = 0xf4000000;
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*CSR_PCICSRIOBASE = 0;
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*CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
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*CSR_PCIROMBASE = 0;
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*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
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} else if (footbridge_cfn_mode() != 0) {
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/*
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* If we are not compiled to accept "add-in" mode, then
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* we are using a constant virt_to_bus translation which
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* can not hope to cater for the way the host BIOS has
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* set up the machine.
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*/
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panic("PCI: this kernel is compiled for central "
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"function mode only");
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}
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/*
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* Map our SDRAM at a known address in PCI space, just in case
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* the firmware had other ideas. Using a nonzero base is
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* necessary, since some VGA cards forcefully use PCI addresses
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* in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
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*/
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*CSR_PCICSRBASE = 0xf4000000;
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*CSR_PCICSRIOBASE = 0;
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*CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
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*CSR_PCIROMBASE = 0;
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*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
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}
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void __init dc21285_postinit(void)
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@ -50,8 +50,7 @@ static int __init fb_dma_init(void)
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dma[_DC21285_DMA(1)].d_ops = &fb_dma_ops;
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#endif
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#ifdef CONFIG_ISA_DMA
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if (footbridge_cfn_mode())
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isa_init_dma();
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isa_init_dma();
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#endif
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return 0;
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}
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@ -16,22 +16,6 @@
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#if defined(CONFIG_FOOTBRIDGE_ADDIN)
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/*
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* If we may be using add-in footbridge mode, then we must
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* use the out-of-line translation that makes use of the
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* PCI BAR
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*/
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#ifndef __ASSEMBLY__
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extern unsigned long __virt_to_bus(unsigned long);
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extern unsigned long __bus_to_virt(unsigned long);
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#endif
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#define __virt_to_bus __virt_to_bus
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#define __bus_to_virt __bus_to_virt
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#elif defined(CONFIG_FOOTBRIDGE_HOST)
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/*
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* The footbridge is programmed to expose the system RAM at 0xe0000000.
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* The requirement is that the RAM isn't placed at bus address 0, which
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@ -41,12 +25,6 @@ extern unsigned long __bus_to_virt(unsigned long);
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#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
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#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
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#else
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#error "Undefined footbridge mode"
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#endif
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/*
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* Cache flushing area.
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*/
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@ -79,9 +79,6 @@ static int __init footbridge_isa_init(void)
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{
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int err = 0;
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if (!footbridge_cfn_mode())
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return 0;
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/* Personal server doesn't have RTC */
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if (!machine_is_personal_server()) {
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isa_rtc_init();
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