scsi: mpt3sas: For NVME device, issue a protocol level reset
1) Manufacturing Page 11 contains parameters to control internal firmware behavior. Based on AddlFlags2 field FW/Driver behaviour can be changed, (flag tm_custom_handling is used for this) a) For PCIe device, protocol level reset should be used if flag tm_custom_handling is 0. Since Abort Task Set, LUN reset and Target reset will result in a protocol level reset. Drivers should issue only one type of this reset, if that fails then it should escalate to a controller reset (diag reset/OCR). b) If the driver has control over the TM reset timeout value, then driver should use the value exposed in PCIe Device Page 2 for pcie device (field ControllerResetTO). Signed-off-by: Chaitra P B <chaitra.basappa@broadcom.com> Signed-off-by: Suganath Prabu S <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Chaitra P B
Martin K. Petersen
Родитель
65928d1f41
Коммит
c1a6c5ac42
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@ -4142,6 +4142,7 @@ _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
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Mpi2ConfigReply_t mpi_reply;
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u32 iounit_pg1_flags;
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ioc->nvme_abort_timeout = 30;
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mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
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if (ioc->ir_firmware)
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mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
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@ -4160,6 +4161,18 @@ _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
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mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
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&ioc->manu_pg11);
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}
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if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
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ioc->tm_custom_handling = 1;
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else {
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ioc->tm_custom_handling = 0;
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if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
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ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
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else if (ioc->manu_pg11.NVMeAbortTO >
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NVME_TASK_ABORT_MAX_TIMEOUT)
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ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
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else
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ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
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}
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mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
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mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
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@ -146,8 +146,12 @@
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#define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */
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#define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */
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#define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */
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#define NVME_TASK_ABORT_MIN_TIMEOUT 6
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#define NVME_TASK_ABORT_MAX_TIMEOUT 60
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#define NVME_TASK_MNGT_CUSTOM_MASK (0x0010)
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#define NVME_PRP_PAGE_SIZE 4096 /* Page size */
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/*
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* reset phases
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*/
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@ -363,7 +367,15 @@ struct Mpi2ManufacturingPage11_t {
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u8 EEDPTagMode; /* 09h */
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u8 Reserved3; /* 0Ah */
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u8 Reserved4; /* 0Bh */
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__le32 Reserved5[23]; /* 0Ch-60h*/
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__le32 Reserved5[8]; /* 0Ch-2Ch */
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u16 AddlFlags2; /* 2Ch */
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u8 AddlFlags3; /* 2Eh */
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u8 Reserved6; /* 2Fh */
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__le32 Reserved7[7]; /* 30h - 4Bh */
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u8 NVMeAbortTO; /* 4Ch */
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u8 Reserved8; /* 4Dh */
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u16 Reserved9; /* 4Eh */
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__le32 Reserved10[4]; /* 50h - 60h */
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};
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/**
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@ -573,6 +585,7 @@ struct _pcie_device {
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u8 enclosure_level;
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u8 connector_name[4];
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u8 *serial_number;
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u8 reset_timeout;
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struct kref refcount;
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};
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/**
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@ -1211,6 +1224,10 @@ struct MPT3SAS_ADAPTER {
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void *event_log;
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u32 event_masks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];
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u8 tm_custom_handling;
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u8 nvme_abort_timeout;
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/* static config pages */
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struct mpt3sas_facts facts;
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struct mpt3sas_port_facts *pfacts;
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@ -1473,10 +1490,11 @@ u8 mpt3sas_scsih_event_callback(struct MPT3SAS_ADAPTER *ioc, u8 msix_index,
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u32 reply);
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void mpt3sas_scsih_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase);
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int mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
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u64 lun, u8 type, u16 smid_task, u16 msix_task, ulong timeout);
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int mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle, u64 lun,
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u8 type, u16 smid_task, u16 msix_task, u8 timeout, u8 tr_method);
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int mpt3sas_scsih_issue_locked_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
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u64 lun, u8 type, u16 smid_task, u16 msix_task, ulong timeout);
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u64 lun, u8 type, u16 smid_task, u16 msix_task,
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u8 timeout, u8 tr_method);
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void mpt3sas_scsih_set_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle);
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void mpt3sas_scsih_clear_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle);
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@ -644,9 +644,10 @@ _ctl_do_mpt_command(struct MPT3SAS_ADAPTER *ioc, struct mpt3_ioctl_command karg,
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MPI2RequestHeader_t *mpi_request = NULL, *request;
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MPI2DefaultReply_t *mpi_reply;
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Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request = NULL;
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struct _pcie_device *pcie_device = NULL;
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u32 ioc_state;
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u16 smid;
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unsigned long timeout;
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u8 timeout;
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u8 issue_reset;
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u32 sz, sz_arg;
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void *psge;
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@ -659,6 +660,7 @@ _ctl_do_mpt_command(struct MPT3SAS_ADAPTER *ioc, struct mpt3_ioctl_command karg,
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long ret;
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u16 wait_state_count;
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u16 device_handle = MPT3SAS_INVALID_DEVICE_HANDLE;
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u8 tr_method = MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE;
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issue_reset = 0;
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@ -1074,14 +1076,26 @@ _ctl_do_mpt_command(struct MPT3SAS_ADAPTER *ioc, struct mpt3_ioctl_command karg,
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ioc->name,
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le16_to_cpu(mpi_request->FunctionDependent1));
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mpt3sas_halt_firmware(ioc);
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pcie_device = mpt3sas_get_pdev_by_handle(ioc,
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le16_to_cpu(mpi_request->FunctionDependent1));
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if (pcie_device && (!ioc->tm_custom_handling))
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mpt3sas_scsih_issue_locked_tm(ioc,
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le16_to_cpu(mpi_request->FunctionDependent1), 0,
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MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 0, 30);
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le16_to_cpu(mpi_request->FunctionDependent1),
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0, MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0,
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0, pcie_device->reset_timeout,
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tr_method);
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else
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mpt3sas_scsih_issue_locked_tm(ioc,
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le16_to_cpu(mpi_request->FunctionDependent1),
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0, MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0,
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0, 30, MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET);
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} else
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mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
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}
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out:
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if (pcie_device)
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pcie_device_put(pcie_device);
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/* free memory associated with sg buffers */
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if (data_in)
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@ -2632,6 +2632,7 @@ mpt3sas_scsih_clear_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle)
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* @smid_task: smid assigned to the task
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* @msix_task: MSIX table index supplied by the OS
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* @timeout: timeout in seconds
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* @tr_method: Target Reset Method
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* Context: user
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*
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* A generic API for sending task management requests to firmware.
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@ -2642,8 +2643,8 @@ mpt3sas_scsih_clear_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle)
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* Return SUCCESS or FAILED.
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*/
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int
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mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
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u64 lun, u8 type, u16 smid_task, u16 msix_task, ulong timeout)
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mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle, u64 lun,
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u8 type, u16 smid_task, u16 msix_task, u8 timeout, u8 tr_method)
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{
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Mpi2SCSITaskManagementRequest_t *mpi_request;
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Mpi2SCSITaskManagementReply_t *mpi_reply;
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@ -2689,8 +2690,8 @@ mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
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}
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dtmprintk(ioc, pr_info(MPT3SAS_FMT
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"sending tm: handle(0x%04x), task_type(0x%02x), smid(%d)\n",
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ioc->name, handle, type, smid_task));
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"sending tm: handle(0x%04x), task_type(0x%02x), smid(%d), timeout(%d), tr_method(0x%x)\n",
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ioc->name, handle, type, smid_task, timeout, tr_method));
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ioc->tm_cmds.status = MPT3_CMD_PENDING;
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mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
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ioc->tm_cmds.smid = smid;
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@ -2699,6 +2700,7 @@ mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
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mpi_request->Function = MPI2_FUNCTION_SCSI_TASK_MGMT;
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mpi_request->DevHandle = cpu_to_le16(handle);
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mpi_request->TaskType = type;
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mpi_request->MsgFlags = tr_method;
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mpi_request->TaskMID = cpu_to_le16(smid_task);
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int_to_scsilun(lun, (struct scsi_lun *)mpi_request->LUN);
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mpt3sas_scsih_set_tm_flag(ioc, handle);
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@ -2745,13 +2747,14 @@ out:
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}
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int mpt3sas_scsih_issue_locked_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
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u64 lun, u8 type, u16 smid_task, u16 msix_task, ulong timeout)
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u64 lun, u8 type, u16 smid_task, u16 msix_task,
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u8 timeout, u8 tr_method)
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{
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int ret;
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mutex_lock(&ioc->tm_cmds.mutex);
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ret = mpt3sas_scsih_issue_tm(ioc, handle, lun, type, smid_task,
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msix_task, timeout);
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msix_task, timeout, tr_method);
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mutex_unlock(&ioc->tm_cmds.mutex);
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return ret;
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@ -2854,6 +2857,8 @@ scsih_abort(struct scsi_cmnd *scmd)
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u16 handle;
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int r;
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u8 timeout = 30;
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struct _pcie_device *pcie_device = NULL;
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sdev_printk(KERN_INFO, scmd->device,
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"attempting task abort! scmd(%p)\n", scmd);
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_scsih_tm_display_info(ioc, scmd);
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@ -2888,15 +2893,20 @@ scsih_abort(struct scsi_cmnd *scmd)
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mpt3sas_halt_firmware(ioc);
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handle = sas_device_priv_data->sas_target->handle;
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pcie_device = mpt3sas_get_pdev_by_handle(ioc, handle);
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if (pcie_device && (!ioc->tm_custom_handling))
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timeout = ioc->nvme_abort_timeout;
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r = mpt3sas_scsih_issue_locked_tm(ioc, handle, scmd->device->lun,
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MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK,
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st->smid, st->msix_io, 30);
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st->smid, st->msix_io, timeout, 0);
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/* Command must be cleared after abort */
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if (r == SUCCESS && st->cb_idx != 0xFF)
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r = FAILED;
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out:
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sdev_printk(KERN_INFO, scmd->device, "task abort: %s scmd(%p)\n",
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((r == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);
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if (pcie_device)
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pcie_device_put(pcie_device);
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return r;
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}
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@ -2912,7 +2922,10 @@ scsih_dev_reset(struct scsi_cmnd *scmd)
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struct MPT3SAS_ADAPTER *ioc = shost_priv(scmd->device->host);
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struct MPT3SAS_DEVICE *sas_device_priv_data;
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struct _sas_device *sas_device = NULL;
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struct _pcie_device *pcie_device = NULL;
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u16 handle;
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u8 tr_method = 0;
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u8 tr_timeout = 30;
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int r;
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struct scsi_target *starget = scmd->device->sdev_target;
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@ -2950,8 +2963,16 @@ scsih_dev_reset(struct scsi_cmnd *scmd)
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goto out;
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}
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pcie_device = mpt3sas_get_pdev_by_handle(ioc, handle);
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if (pcie_device && (!ioc->tm_custom_handling)) {
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tr_timeout = pcie_device->reset_timeout;
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tr_method = MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE;
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} else
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tr_method = MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET;
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r = mpt3sas_scsih_issue_locked_tm(ioc, handle, scmd->device->lun,
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MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET, 0, 0, 30);
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MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET, 0, 0,
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tr_timeout, tr_method);
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/* Check for busy commands after reset */
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if (r == SUCCESS && atomic_read(&scmd->device->device_busy))
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r = FAILED;
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@ -2961,6 +2982,8 @@ scsih_dev_reset(struct scsi_cmnd *scmd)
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if (sas_device)
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sas_device_put(sas_device);
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if (pcie_device)
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pcie_device_put(pcie_device);
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return r;
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}
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@ -2977,7 +3000,10 @@ scsih_target_reset(struct scsi_cmnd *scmd)
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struct MPT3SAS_ADAPTER *ioc = shost_priv(scmd->device->host);
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struct MPT3SAS_DEVICE *sas_device_priv_data;
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struct _sas_device *sas_device = NULL;
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struct _pcie_device *pcie_device = NULL;
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u16 handle;
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u8 tr_method = 0;
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u8 tr_timeout = 30;
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int r;
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struct scsi_target *starget = scmd->device->sdev_target;
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struct MPT3SAS_TARGET *target_priv_data = starget->hostdata;
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@ -3014,8 +3040,16 @@ scsih_target_reset(struct scsi_cmnd *scmd)
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goto out;
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}
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pcie_device = mpt3sas_get_pdev_by_handle(ioc, handle);
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if (pcie_device && (!ioc->tm_custom_handling)) {
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tr_timeout = pcie_device->reset_timeout;
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tr_method = MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE;
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} else
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tr_method = MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET;
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r = mpt3sas_scsih_issue_locked_tm(ioc, handle, 0,
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MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 0, 30);
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MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, 0, 0,
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tr_timeout, tr_method);
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/* Check for busy commands after reset */
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if (r == SUCCESS && atomic_read(&starget->target_busy))
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r = FAILED;
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@ -3025,7 +3059,8 @@ scsih_target_reset(struct scsi_cmnd *scmd)
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if (sas_device)
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sas_device_put(sas_device);
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if (pcie_device)
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pcie_device_put(pcie_device);
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return r;
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}
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@ -3559,6 +3594,7 @@ _scsih_tm_tr_send(struct MPT3SAS_ADAPTER *ioc, u16 handle)
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unsigned long flags;
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struct _tr_list *delayed_tr;
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u32 ioc_state;
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u8 tr_method = 0;
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if (ioc->pci_error_recovery) {
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dewtprintk(ioc, pr_info(MPT3SAS_FMT
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@ -3601,6 +3637,11 @@ _scsih_tm_tr_send(struct MPT3SAS_ADAPTER *ioc, u16 handle)
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sas_address = pcie_device->wwid;
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}
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spin_unlock_irqrestore(&ioc->pcie_device_lock, flags);
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if (pcie_device && (!ioc->tm_custom_handling))
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tr_method =
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MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE;
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else
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tr_method = MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET;
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}
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if (sas_target_priv_data) {
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dewtprintk(ioc, pr_info(MPT3SAS_FMT
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@ -3664,6 +3705,7 @@ _scsih_tm_tr_send(struct MPT3SAS_ADAPTER *ioc, u16 handle)
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mpi_request->Function = MPI2_FUNCTION_SCSI_TASK_MGMT;
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mpi_request->DevHandle = cpu_to_le16(handle);
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mpi_request->TaskType = MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET;
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mpi_request->MsgFlags = tr_method;
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set_bit(handle, ioc->device_remove_in_progress);
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mpt3sas_base_put_smid_hi_priority(ioc, smid, 0);
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mpt3sas_trigger_master(ioc, MASTER_TRIGGER_DEVICE_REMOVAL);
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@ -6938,6 +6980,11 @@ _scsih_pcie_add_device(struct MPT3SAS_ADAPTER *ioc, u16 handle)
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|||
}
|
||||
pcie_device->nvme_mdts =
|
||||
le32_to_cpu(pcie_device_pg2.MaximumDataTransferSize);
|
||||
if (pcie_device_pg2.ControllerResetTO)
|
||||
pcie_device->reset_timeout =
|
||||
pcie_device_pg2.ControllerResetTO;
|
||||
else
|
||||
pcie_device->reset_timeout = 30;
|
||||
|
||||
if (ioc->wait_for_discovery_to_complete)
|
||||
_scsih_pcie_device_init_add(ioc, pcie_device);
|
||||
|
|
@ -7190,6 +7237,9 @@ _scsih_pcie_device_status_change_event_debug(struct MPT3SAS_ADAPTER *ioc,
|
|||
case MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION:
|
||||
reason_str = "internal async notification";
|
||||
break;
|
||||
case MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED:
|
||||
reason_str = "pcie hot reset failed";
|
||||
break;
|
||||
default:
|
||||
reason_str = "unknown reason";
|
||||
break;
|
||||
|
|
@ -7444,7 +7494,7 @@ _scsih_sas_broadcast_primitive_event(struct MPT3SAS_ADAPTER *ioc,
|
|||
spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
|
||||
r = mpt3sas_scsih_issue_tm(ioc, handle, lun,
|
||||
MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK, st->smid,
|
||||
st->msix_io, 30);
|
||||
st->msix_io, 30, 0);
|
||||
if (r == FAILED) {
|
||||
sdev_printk(KERN_WARNING, sdev,
|
||||
"mpt3sas_scsih_issue_tm: FAILED when sending "
|
||||
|
|
@ -7485,7 +7535,7 @@ _scsih_sas_broadcast_primitive_event(struct MPT3SAS_ADAPTER *ioc,
|
|||
|
||||
r = mpt3sas_scsih_issue_tm(ioc, handle, sdev->lun,
|
||||
MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, st->smid,
|
||||
st->msix_io, 30);
|
||||
st->msix_io, 30, 0);
|
||||
if (r == FAILED || st->cb_idx != 0xFF) {
|
||||
sdev_printk(KERN_WARNING, sdev,
|
||||
"mpt3sas_scsih_issue_tm: ABORT_TASK: FAILED : "
|
||||
|
|
|
|||
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