net: mvpp2: split xlg and gmac pcs
Split the XLG and GMAC PCS implementations and switch between them during the mac_prepare() method. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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Родитель
94bfe438bc
Коммит
c596d2cd13
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@ -5381,9 +5381,10 @@ static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs)
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return container_of(pcs, struct mvpp2_port, phylink_pcs);
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}
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static void mvpp22_xlg_pcs_get_state(struct mvpp2_port *port,
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struct phylink_link_state *state)
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static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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u32 val;
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state->speed = SPEED_10000;
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@ -5401,9 +5402,24 @@ static void mvpp22_xlg_pcs_get_state(struct mvpp2_port *port,
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state->pause |= MLO_PAUSE_RX;
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}
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static void mvpp2_gmac_pcs_get_state(struct mvpp2_port *port,
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static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs,
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unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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return 0;
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}
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static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
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.pcs_get_state = mvpp2_xlg_pcs_get_state,
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.pcs_config = mvpp2_xlg_pcs_config,
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};
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static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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u32 val;
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val = readl(port->base + MVPP2_GMAC_STATUS0);
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@ -5435,29 +5451,12 @@ static void mvpp2_gmac_pcs_get_state(struct mvpp2_port *port,
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state->pause |= MLO_PAUSE_TX;
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}
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static void mvpp2_phylink_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
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u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
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mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
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if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
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mvpp22_xlg_pcs_get_state(port, state);
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return;
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}
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}
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mvpp2_gmac_pcs_get_state(port, state);
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}
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static int mvpp2_gmac_pcs_config(struct mvpp2_port *port, unsigned int mode,
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static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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u32 mask, val, an, old_an, changed;
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mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
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@ -5509,25 +5508,7 @@ static int mvpp2_gmac_pcs_config(struct mvpp2_port *port, unsigned int mode,
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return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
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}
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static int mvpp2_phylink_pcs_config(struct phylink_pcs *pcs,
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unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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int ret;
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if (mvpp2_is_xlg(interface))
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ret = 0;
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else
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ret = mvpp2_gmac_pcs_config(port, mode, interface, advertising,
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permit_pause_to_mac);
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return ret;
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}
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static void mvpp2_phylink_pcs_an_restart(struct phylink_pcs *pcs)
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static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
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{
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struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
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u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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@ -5538,10 +5519,10 @@ static void mvpp2_phylink_pcs_an_restart(struct phylink_pcs *pcs)
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port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static const struct phylink_pcs_ops mvpp2_phylink_pcs_ops = {
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.pcs_get_state = mvpp2_phylink_pcs_get_state,
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.pcs_config = mvpp2_phylink_pcs_config,
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.pcs_an_restart = mvpp2_phylink_pcs_an_restart,
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static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
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.pcs_get_state = mvpp2_gmac_pcs_get_state,
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.pcs_config = mvpp2_gmac_pcs_config,
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.pcs_an_restart = mvpp2_gmac_pcs_an_restart,
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};
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static void mvpp2_phylink_validate(struct phylink_config *config,
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@ -5711,8 +5692,8 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
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}
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static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
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phy_interface_t interface)
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static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
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phy_interface_t interface)
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{
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struct mvpp2_port *port = mvpp2_phylink_to_port(config);
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@ -5758,9 +5739,31 @@ static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
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}
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}
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/* Select the appropriate PCS operations depending on the
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* configured interface mode. We will only switch to a mode
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* that the validate() checks have already passed.
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*/
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if (mvpp2_is_xlg(interface))
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port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops;
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else
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port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops;
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return 0;
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}
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static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
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phy_interface_t interface)
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{
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struct mvpp2_port *port = mvpp2_phylink_to_port(config);
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int ret;
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ret = mvpp2__mac_prepare(config, mode, interface);
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if (ret == 0)
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phylink_set_pcs(port->phylink, &port->phylink_pcs);
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return ret;
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}
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static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
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const struct phylink_link_state *state)
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{
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@ -5934,12 +5937,12 @@ static void mvpp2_acpi_start(struct mvpp2_port *port)
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struct phylink_link_state state = {
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.interface = port->phy_interface,
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};
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mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND,
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port->phy_interface);
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mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND,
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port->phy_interface);
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mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
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mvpp2_phylink_pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
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port->phy_interface, state.advertising,
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false);
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port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
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port->phy_interface,
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state.advertising, false);
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mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
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port->phy_interface);
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mvpp2_mac_link_up(&port->phylink_config, NULL,
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@ -6171,9 +6174,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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goto err_free_port_pcpu;
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}
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port->phylink = phylink;
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port->phylink_pcs.ops = &mvpp2_phylink_pcs_ops;
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phylink_set_pcs(phylink, &port->phylink_pcs);
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} else {
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port->phylink = NULL;
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}
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