Renesas ARM Based SoC DT Updates for v3.17
Increased hardware coverage: * Add R-Car sounds support to r8a7790 SoC * Add PCIe support to r8a7790 and r8a7791 SoCs * Increase I2C support of Henninger and lager boards * DVFS support to Koelsch board * Add SYS-DMAC clocks to r8a7791 SoCs * Add USB 3.0 clocks to r8a7791 and r8a7790 SoCs * Add LED labels to armadillo800eva board Cleanup: * Remove early_printk from marzen command line -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTp4AmAAoJENfPZGlqN0++qXoQAKQd5bKocjp41iXD8WoM+Ndy SNleodySSK52fNYTdibhsP2GC4z5qoXt2lJc1pmyM2oHP5czaeKiNFIA92twHmk4 AXA+wr4KuPOzDcKmu1UsVPZRmFcOcpW4ec8z3moM49/dfq6K3uEto89SBKTgA2r4 iRU4RiVntG5j3it5/40j1GzhcrLuVzngTteZxF/HQK/jFnvvXITeAoZBCl2/oc0g wttoW56D3BbxyaVHzbpRmZCJZrBI461vbhCmI+qhLqZVnqKE2uxCjf+ogY0FkbOu U70wqoI7Sa+cdFk9PlYvUJIC24FPj3ztQAU2Nf4WqTmwc9M2ouzXSlPYjm5MO6HF h4UUZFadSdo8s0kykGvlXA4Lo+AFy32efLycu98v8K1fwq8N9of3N6F9Ck03INV9 j+C0z2n5nzpwwmej+sat4U2N1mv+YvpG2BEwku14Fj5nqt7gPVDs+JdiibSTnqlF U3rzAeO1reDuyQLfCKyqDrqGnGMATWJnOt+B9BbUpqw4eiDI6ChVEPMwa8pcuvPs qGrqWafCJ1qtt7RqRrqVcpJncf3CQ2cF3wX5Z8crLg1oOlpWOrGbQl62vYVjz/Pr /iJ8mrvN9+kWKhsybgkqr5APDPDcwxonJEuTV+llGNo9jPjz9nW6a1g1JuVWtRW0 F+X8oBfRjktxslRRUqnU =nQsS -----END PGP SIGNATURE----- Merge tag 'renesas-dt-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Renesas ARM Based SoC DT Updates for v3.17" from Simon Horman: Increased hardware coverage: - Add R-Car sounds support to r8a7790 SoC - Add PCIe support to r8a7790 and r8a7791 SoCs - Increase I2C support of Henninger and lager boards - DVFS support to Koelsch board - Add SYS-DMAC clocks to r8a7791 SoCs - Add USB 3.0 clocks to r8a7791 and r8a7790 SoCs - Add LED labels to armadillo800eva board Cleanup: - Remove early_printk from marzen command line * tag 'renesas-dt-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (29 commits) ARM: shmobile: r8a7791: add R-Car sound support on DTSI ARM: shmobile: henninger: Enable PCIe Controller & PCIe bus clock ARM: shmobile: koelsch: Enable PCIe Controller & PCIe bus clock ARM: shmobile: r8a7791: Add PCIe Controller device node ARM: shmobile: r8a7791: Add default PCIe bus clock ARM: shmobile: r8a7791: Add PCIEC clock device tree node ARM: shmobile: r8a7790: Add PCIe Controller device node ARM: shmobile: r8a7790: Add default PCIe bus clock ARM: shmobile: r8a7790: Add PCIEC clock device tree node ARM: shmobile: r8a7791: add MSTP10 support on DTSI ARM: shmobile: r8a7791: add audio clock on DTSI ARM: shmobile: r8a7790: add R-Car sound support on DTSI ARM: shmobile: r8a7790: add MSTP10 support on DTSI ARM: shmobile: henninger: add I2C2 DT support ARM: shmobile: koelsch: Remove duplicate i2c6 nodes ARM: shmobile: lager: Remove duplicate i2c3 nodes ARM: shmobile: Lager memory map update ARM: shmobile: lager: Move i2c[12]_pins nodes to pfc node ARM: shmobile: lager: add i2c1, i2c2 pins ARM: shmobile: lager: enable i2c devices ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
cc7b990440
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@ -104,17 +104,21 @@
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leds {
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compatible = "gpio-leds";
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led1 {
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gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
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};
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led2 {
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gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
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};
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led3 {
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gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
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gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
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label = "LED3";
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};
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led4 {
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gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
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label = "LED4";
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};
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led5 {
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gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
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label = "LED5";
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};
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led6 {
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gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
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label = "LED6";
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};
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};
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@ -17,7 +17,7 @@
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compatible = "renesas,marzen", "renesas,r8a7779";
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chosen {
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bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
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bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
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};
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memory {
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@ -29,12 +29,12 @@
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x80000000>;
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reg = <0 0x40000000 0 0x40000000>;
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};
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memory@180000000 {
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device_type = "memory";
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reg = <1 0x80000000 0 0x80000000>;
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reg = <1 0x40000000 0 0xc0000000>;
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};
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lbsc {
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@ -204,6 +204,21 @@
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"msiof1_tx";
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renesas,function = "msiof1";
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};
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i2c1_pins: i2c1 {
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renesas,groups = "i2c1";
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renesas,function = "i2c1";
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};
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i2c2_pins: i2c2 {
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renesas,groups = "i2c2";
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renesas,function = "i2c2";
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};
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i2c3_pins: i2c3 {
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renesas,groups = "i2c3";
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renesas,function = "i2c3";
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};
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};
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ðer {
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@ -317,3 +332,39 @@
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cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&cpu0 {
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cpu0-supply = <&vdd_dvfs>;
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};
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&i2c0 {
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status = "ok";
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};
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&i2c1 {
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status = "ok";
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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&i2c2 {
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status = "ok";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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status = "okay";
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vdd_dvfs: regulator@68 {
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compatible = "diasemi,da9210";
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reg = <0x68>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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@ -44,6 +44,17 @@
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1300000000>;
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voltage-tolerance = <1>; /* 1% */
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clocks = <&cpg_clocks R8A7790_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1400000 1000000>,
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<1225000 1000000>,
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<1050000 1000000>,
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< 875000 1000000>,
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< 700000 1000000>,
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< 350000 1000000>;
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};
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cpu1: cpu@1 {
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@ -476,6 +487,15 @@
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clock-output-names = "extal";
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "pcie_bus";
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status = "disabled";
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};
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency clocks by
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* default. Boards that provide audio clocks should override them.
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@ -754,17 +774,17 @@
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
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<&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
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<&hp_clk>, <&hp_clk>, <&rclk_clk>;
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<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
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R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
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R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1
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R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
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>;
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clock-output-names =
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"iic2", "tpu0", "mmcif1", "sdhi3",
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"sdhi2", "sdhi1", "sdhi0", "mmcif0",
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"iic0", "iic1", "cmt1";
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"iic0", "pciec", "iic1", "ssusb", "cmt1";
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};
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mstp5_clks: mstp5_clks@e6150144 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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@ -824,6 +844,39 @@
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"rcan1", "rcan0", "qspi_mod", "iic3",
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"i2c3", "i2c2", "i2c1", "i2c0";
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};
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mstp10_clks: mstp10_clks@e6150998 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
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clocks = <&p_clk>,
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<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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<&p_clk>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
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<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7790_CLK_SSI_ALL
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R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
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R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
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R8A7790_CLK_SCU_ALL
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R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
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R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
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R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
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>;
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clock-output-names =
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"ssi-all",
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"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
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"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
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"scu-all",
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"scu-dvc1", "scu-dvc0",
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"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
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"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
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};
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};
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qspi: spi@e6b10000 {
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@ -876,4 +929,85 @@
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#size-cells = <0>;
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status = "disabled";
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};
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pciec: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7790";
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
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0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
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0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
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0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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/* Map all possible DDR as inbound ranges */
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
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0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
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interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
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<0 117 IRQ_TYPE_LEVEL_HIGH>,
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<0 118 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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status = "disabled";
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};
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rcar_sound: rcar_sound@0xec500000 {
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#sound-dai-cells = <1>;
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compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
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interrupt-parent = <&gic>;
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reg = <0 0xec500000 0 0x1000>, /* SCU */
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<0 0xec5a0000 0 0x100>, /* ADG */
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<0 0xec540000 0 0x1000>, /* SSIU */
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<0 0xec541000 0 0x1280>; /* SSI */
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clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
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<&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
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<&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
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<&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
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<&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
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<&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
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<&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
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<&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
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<&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
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<&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
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<&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
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<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
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clock-names = "ssi-all",
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"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
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"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
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"src.9", "src.8", "src.7", "src.6", "src.5",
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"src.4", "src.3", "src.2", "src.1", "src.0",
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"clk_a", "clk_b", "clk_c", "clk_i";
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status = "disabled";
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rcar_sound,src {
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src0: src@0 { };
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src1: src@1 { };
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src2: src@2 { };
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src3: src@3 { };
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src4: src@4 { };
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src5: src@5 { };
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src6: src@6 { };
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src7: src@7 { };
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src8: src@8 { };
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src9: src@9 { };
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};
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rcar_sound,ssi {
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ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
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ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
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ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
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ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
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ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
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ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
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ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
|
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ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
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ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
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ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
};
|
||||
};
|
||||
};
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||||
|
|
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|||
|
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@ -110,6 +110,11 @@
|
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renesas,function = "sdhi2";
|
||||
};
|
||||
|
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i2c2_pins: i2c2 {
|
||||
renesas,groups = "i2c2";
|
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renesas,function = "i2c2";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
|
|
@ -170,6 +175,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -217,3 +230,11 @@
|
|||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -215,25 +215,6 @@
|
|||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "renesas,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -293,6 +274,11 @@
|
|||
"msiof0_tx";
|
||||
renesas,function = "msiof0";
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6 {
|
||||
renesas,groups = "i2c6";
|
||||
renesas,function = "i2c6";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
|
|
@ -408,3 +394,46 @@
|
|||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "renesas,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
vdd_dvfs: regulator@68 {
|
||||
compatible = "diasemi,da9210";
|
||||
reg = <0x68>;
|
||||
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_dvfs>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,6 +45,17 @@
|
|||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1500000000>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7791_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
operating-points = <1500000 1000000>,
|
||||
<1312500 1000000>,
|
||||
<1125000 1000000>,
|
||||
< 937500 1000000>,
|
||||
< 750000 1000000>,
|
||||
< 375000 1000000>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
|
@ -521,6 +532,38 @@
|
|||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency clocks by
|
||||
* default. Boards that provide audio clocks should override them.
|
||||
*/
|
||||
audio_clk_a: audio_clk_a {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_a";
|
||||
};
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_b";
|
||||
};
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_c";
|
||||
};
|
||||
|
||||
/* External PCIe clock - can be overridden by the board */
|
||||
pcie_bus_clk: pcie_bus_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7791-cpg-clocks",
|
||||
|
|
@ -743,30 +786,34 @@
|
|||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&mp_clk>, <&mp_clk>, <&mp_clk>;
|
||||
<&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
|
||||
R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
|
||||
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
|
||||
R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
||||
"scifb1", "msiof1", "scifb2";
|
||||
"scifb1", "msiof1", "scifb2",
|
||||
"sys-dmac1", "sys-dmac0";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
|
||||
<&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
|
||||
<&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
|
||||
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
|
||||
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
|
||||
R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
|
||||
>;
|
||||
clock-output-names =
|
||||
"tpu0", "sdhi2", "sdhi1", "sdhi0",
|
||||
"mmcif0", "i2c7", "i2c8", "cmt1";
|
||||
"mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
|
||||
};
|
||||
mstp5_clks: mstp5_clks@e6150144 {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
@ -828,6 +875,39 @@
|
|||
"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
|
||||
"i2c1", "i2c0";
|
||||
};
|
||||
mstp10_clks: mstp10_clks@e6150998 {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
|
||||
clocks = <&p_clk>,
|
||||
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
||||
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
||||
<&p_clk>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7791_CLK_SSI_ALL
|
||||
R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
|
||||
R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
|
||||
R8A7791_CLK_SCU_ALL
|
||||
R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
|
||||
R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
|
||||
R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
|
||||
>;
|
||||
clock-output-names =
|
||||
"ssi-all",
|
||||
"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
|
||||
"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
|
||||
"scu-all",
|
||||
"scu-dvc1", "scu-dvc0",
|
||||
"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
|
||||
"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
|
||||
};
|
||||
mstp11_clks: mstp11_clks@e615099c {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
||||
|
|
@ -880,4 +960,85 @@
|
|||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a7791";
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
|
||||
0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
|
||||
0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
|
||||
0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
|
||||
/* Map all possible DDR as inbound ranges */
|
||||
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
|
||||
0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
|
||||
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcar_sound: rcar_sound@0xec500000 {
|
||||
#sound-dai-cells = <1>;
|
||||
compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x1280>; /* SSI */
|
||||
clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
|
||||
<&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
|
||||
<&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
|
||||
<&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
|
||||
<&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
|
||||
<&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
|
||||
<&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
|
||||
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
|
||||
clock-names = "ssi-all",
|
||||
"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
|
||||
"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
|
||||
"src.9", "src.8", "src.7", "src.6", "src.5",
|
||||
"src.4", "src.3", "src.2", "src.1", "src.0",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
rcar_sound,src {
|
||||
src0: src@0 { };
|
||||
src1: src@1 { };
|
||||
src2: src@2 { };
|
||||
src3: src@3 { };
|
||||
src4: src@4 { };
|
||||
src5: src@5 { };
|
||||
src6: src@6 { };
|
||||
src7: src@7 { };
|
||||
src8: src@8 { };
|
||||
src9: src@9 { };
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@
|
|||
#define R8A7790_CLK_SDHI0 14
|
||||
#define R8A7790_CLK_MMCIF0 15
|
||||
#define R8A7790_CLK_IIC0 18
|
||||
#define R8A7790_CLK_PCIEC 19
|
||||
#define R8A7790_CLK_IIC1 23
|
||||
#define R8A7790_CLK_SSUSB 28
|
||||
#define R8A7790_CLK_CMT1 29
|
||||
|
|
@ -107,4 +108,30 @@
|
|||
#define R8A7790_CLK_I2C1 30
|
||||
#define R8A7790_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7790_CLK_SSI_ALL 5
|
||||
#define R8A7790_CLK_SSI9 6
|
||||
#define R8A7790_CLK_SSI8 7
|
||||
#define R8A7790_CLK_SSI7 8
|
||||
#define R8A7790_CLK_SSI6 9
|
||||
#define R8A7790_CLK_SSI5 10
|
||||
#define R8A7790_CLK_SSI4 11
|
||||
#define R8A7790_CLK_SSI3 12
|
||||
#define R8A7790_CLK_SSI2 13
|
||||
#define R8A7790_CLK_SSI1 14
|
||||
#define R8A7790_CLK_SSI0 15
|
||||
#define R8A7790_CLK_SCU_ALL 17
|
||||
#define R8A7790_CLK_SCU_DVC1 18
|
||||
#define R8A7790_CLK_SCU_DVC0 19
|
||||
#define R8A7790_CLK_SCU_SRC9 22
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#define R8A7790_CLK_SCU_SRC8 23
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#define R8A7790_CLK_SCU_SRC7 24
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#define R8A7790_CLK_SCU_SRC6 25
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#define R8A7790_CLK_SCU_SRC5 26
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#define R8A7790_CLK_SCU_SRC4 27
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#define R8A7790_CLK_SCU_SRC3 28
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#define R8A7790_CLK_SCU_SRC2 29
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#define R8A7790_CLK_SCU_SRC1 30
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#define R8A7790_CLK_SCU_SRC0 31
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||||
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#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
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||||
|
|
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|||
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@ -53,6 +53,7 @@
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|||
#define R8A7791_CLK_SDHI0 14
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||||
#define R8A7791_CLK_MMCIF0 15
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||||
#define R8A7791_CLK_IIC0 18
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||||
#define R8A7791_CLK_PCIEC 19
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||||
#define R8A7791_CLK_IIC1 23
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||||
#define R8A7791_CLK_SSUSB 28
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||||
#define R8A7791_CLK_CMT1 29
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@ -107,6 +108,32 @@
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#define R8A7791_CLK_I2C1 30
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||||
#define R8A7791_CLK_I2C0 31
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||||
|
||||
/* MSTP10 */
|
||||
#define R8A7791_CLK_SSI_ALL 5
|
||||
#define R8A7791_CLK_SSI9 6
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||||
#define R8A7791_CLK_SSI8 7
|
||||
#define R8A7791_CLK_SSI7 8
|
||||
#define R8A7791_CLK_SSI6 9
|
||||
#define R8A7791_CLK_SSI5 10
|
||||
#define R8A7791_CLK_SSI4 11
|
||||
#define R8A7791_CLK_SSI3 12
|
||||
#define R8A7791_CLK_SSI2 13
|
||||
#define R8A7791_CLK_SSI1 14
|
||||
#define R8A7791_CLK_SSI0 15
|
||||
#define R8A7791_CLK_SCU_ALL 17
|
||||
#define R8A7791_CLK_SCU_DVC1 18
|
||||
#define R8A7791_CLK_SCU_DVC0 19
|
||||
#define R8A7791_CLK_SCU_SRC9 22
|
||||
#define R8A7791_CLK_SCU_SRC8 23
|
||||
#define R8A7791_CLK_SCU_SRC7 24
|
||||
#define R8A7791_CLK_SCU_SRC6 25
|
||||
#define R8A7791_CLK_SCU_SRC5 26
|
||||
#define R8A7791_CLK_SCU_SRC4 27
|
||||
#define R8A7791_CLK_SCU_SRC3 28
|
||||
#define R8A7791_CLK_SCU_SRC2 29
|
||||
#define R8A7791_CLK_SCU_SRC1 30
|
||||
#define R8A7791_CLK_SCU_SRC0 31
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7791_CLK_SCIFA3 6
|
||||
#define R8A7791_CLK_SCIFA4 7
|
||||
|
|
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