ASoC: mxs-sgtl5000: Remove MCLK restriction
According to the sgtl5000 datasheet the MCLK frequency range restriction of 8 to 27 MHz only applies when the PLL is used - synchronous SYS_MCLK input mode. mxs-sgtl5000 machine sets the codec as slave, and mx28 generates MCLK in the range of 256*fs, 384*fs or 512*fs, which is called asynchronous SYS_MCLK input. In asynchronous SYS_MCLK we cannot have the 8 to 27 MHz check because if we want to play a 8KHz sample rate track, with a MCLK of 8k * 512 = 4.096MHz the current check would return -EINVAL, which is not correct. Remove the 8 to 27MHz frequency check, since this only applies to the synchronous SYS_MCLK input case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -49,13 +49,6 @@ static int mxs_sgtl5000_hw_params(struct snd_pcm_substream *substream,
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break;
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break;
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}
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}
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/* Sgtl5000 sysclk should be >= 8MHz and <= 27M */
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if (mclk < 8000000 || mclk > 27000000) {
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dev_err(codec_dai->dev, "Invalid mclk frequency: %u.%03uMHz\n",
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mclk / 1000000, mclk / 1000 % 1000);
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return -EINVAL;
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}
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/* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */
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/* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */
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ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0);
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ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0);
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if (ret) {
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if (ret) {
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