RDMA/hns: Fix coding style issues
Just format the code without modifying anything, including fixing some redundant and missing blanks and spaces and changing the variable definition order. Link: https://lore.kernel.org/r/1607650657-35992-8-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Lang Cheng
Jason Gunthorpe
Родитель
29b52027ac
Коммит
dc93a0d987
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@ -36,9 +36,9 @@
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#include "hns_roce_device.h"
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#include "hns_roce_cmd.h"
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#define CMD_POLL_TOKEN 0xffff
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#define CMD_MAX_NUM 32
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#define CMD_TOKEN_MASK 0x1f
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#define CMD_POLL_TOKEN 0xffff
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#define CMD_MAX_NUM 32
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#define CMD_TOKEN_MASK 0x1f
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static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, u32 in_modifier,
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@ -93,8 +93,8 @@ static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
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void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
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u64 out_param)
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{
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struct hns_roce_cmd_context
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*context = &hr_dev->cmd.context[token & hr_dev->cmd.token_mask];
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struct hns_roce_cmd_context *context =
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&hr_dev->cmd.context[token % hr_dev->cmd.max_cmds];
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if (token != context->token)
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return;
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@ -164,8 +164,8 @@ static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
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int ret;
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down(&hr_dev->cmd.event_sem);
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ret = __hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,
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in_modifier, op_modifier, op, timeout);
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ret = __hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param, in_modifier,
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op_modifier, op, timeout);
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up(&hr_dev->cmd.event_sem);
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return ret;
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@ -231,9 +231,8 @@ int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev)
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struct hns_roce_cmdq *hr_cmd = &hr_dev->cmd;
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int i;
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hr_cmd->context = kmalloc_array(hr_cmd->max_cmds,
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sizeof(*hr_cmd->context),
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GFP_KERNEL);
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hr_cmd->context =
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kcalloc(hr_cmd->max_cmds, sizeof(*hr_cmd->context), GFP_KERNEL);
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if (!hr_cmd->context)
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return -ENOMEM;
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@ -262,8 +261,8 @@ void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev)
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hr_cmd->use_events = 0;
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}
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struct hns_roce_cmd_mailbox
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*hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev)
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struct hns_roce_cmd_mailbox *
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hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_cmd_mailbox *mailbox;
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@ -271,8 +270,8 @@ struct hns_roce_cmd_mailbox
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if (!mailbox)
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return ERR_PTR(-ENOMEM);
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mailbox->buf = dma_pool_alloc(hr_dev->cmd.pool, GFP_KERNEL,
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&mailbox->dma);
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mailbox->buf =
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dma_pool_alloc(hr_dev->cmd.pool, GFP_KERNEL, &mailbox->dma);
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if (!mailbox->buf) {
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kfree(mailbox);
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return ERR_PTR(-ENOMEM);
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@ -143,8 +143,8 @@ int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
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unsigned long in_modifier, u8 op_modifier, u16 op,
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unsigned long timeout);
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struct hns_roce_cmd_mailbox
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*hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
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struct hns_roce_cmd_mailbox *
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hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
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void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
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struct hns_roce_cmd_mailbox *mailbox);
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@ -40,9 +40,9 @@
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static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
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{
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struct ib_device *ibdev = &hr_dev->ib_dev;
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struct hns_roce_cmd_mailbox *mailbox;
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struct hns_roce_cq_table *cq_table;
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struct ib_device *ibdev = &hr_dev->ib_dev;
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u64 mtts[MTT_MIN_COUNT] = { 0 };
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dma_addr_t dma_handle;
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int ret;
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@ -209,9 +209,9 @@ int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
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{
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struct device *dev = hr_dev->dev;
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u32 chunk_ba_num;
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u32 chunk_size;
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u32 table_idx;
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u32 bt_num;
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u32 chunk_size;
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if (get_hem_table_config(hr_dev, mhop, table->type))
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return -EINVAL;
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@ -343,15 +343,15 @@ static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
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{
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spinlock_t *lock = &hr_dev->bt_cmd_lock;
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struct device *dev = hr_dev->dev;
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long end;
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unsigned long flags;
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struct hns_roce_hem_iter iter;
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void __iomem *bt_cmd;
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__le32 bt_cmd_val[2];
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__le32 bt_cmd_h = 0;
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unsigned long flags;
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__le32 bt_cmd_l;
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u64 bt_ba;
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int ret = 0;
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u64 bt_ba;
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long end;
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/* Find the HEM(Hardware Entry Memory) entry */
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unsigned long i = (obj & (table->num_obj - 1)) /
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@ -651,8 +651,8 @@ int hns_roce_table_get(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, unsigned long obj)
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{
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struct device *dev = hr_dev->dev;
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int ret = 0;
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unsigned long i;
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int ret = 0;
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if (hns_roce_check_whether_mhop(hr_dev, table->type))
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return hns_roce_table_mhop_get(hr_dev, table, obj);
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@ -800,14 +800,14 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_chunk *chunk;
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struct hns_roce_hem_mhop mhop;
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struct hns_roce_hem *hem;
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void *addr = NULL;
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unsigned long mhop_obj = obj;
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unsigned long obj_per_chunk;
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unsigned long idx_offset;
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int offset, dma_offset;
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void *addr = NULL;
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u32 hem_idx = 0;
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int length;
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int i, j;
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u32 hem_idx = 0;
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if (!table->lowmem)
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return NULL;
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@ -977,8 +977,8 @@ static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
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{
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struct hns_roce_hem_mhop mhop;
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u32 buf_chunk_size;
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int i;
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u64 obj;
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int i;
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if (hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop))
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return;
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@ -1313,8 +1313,8 @@ static int hem_list_alloc_root_bt(struct hns_roce_dev *hr_dev,
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const struct hns_roce_buf_region *regions,
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int region_cnt)
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{
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struct roce_hem_item *hem, *temp_hem, *root_hem;
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struct list_head temp_list[HNS_ROCE_MAX_BT_REGION];
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struct roce_hem_item *hem, *temp_hem, *root_hem;
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const struct hns_roce_buf_region *r;
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struct list_head temp_root;
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struct list_head temp_btm;
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@ -1419,8 +1419,8 @@ int hns_roce_hem_list_request(struct hns_roce_dev *hr_dev,
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{
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const struct hns_roce_buf_region *r;
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int ofs, end;
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int ret;
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int unit;
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int ret;
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int i;
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if (region_cnt > HNS_ROCE_MAX_BT_REGION) {
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@ -175,4 +175,4 @@ static inline dma_addr_t hns_roce_hem_addr(struct hns_roce_hem_iter *iter)
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return sg_dma_address(&iter->chunk->mem[iter->page_idx]);
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}
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#endif /*_HNS_ROCE_HEM_H*/
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#endif /* _HNS_ROCE_HEM_H */
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@ -239,7 +239,7 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp,
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break;
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}
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/*Ctrl field, ctrl set type: sig, solic, imm, fence */
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/* Ctrl field, ctrl set type: sig, solic, imm, fence */
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/* SO wait for conforming application scenarios */
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ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
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cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
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@ -300,7 +300,7 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp,
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}
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ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
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} else {
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/*sqe num is two */
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/* sqe num is two */
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for (i = 0; i < wr->num_sge; i++)
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set_data_seg(dseg + i, wr->sg_list + i);
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@ -1165,7 +1165,7 @@ static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
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}
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raq->e_raq_buf->map = addr;
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/* Configure raq extended address. 48bit 4K align*/
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/* Configure raq extended address. 48bit 4K align */
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roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
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/* Configure raq_shift */
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@ -2760,7 +2760,6 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
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roce_set_field(context->qpc_bytes_16,
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QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
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QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
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} else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
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roce_set_field(context->qpc_bytes_4,
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QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
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@ -3795,7 +3794,6 @@ static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
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int event_type;
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while ((aeqe = next_aeqe_sw_v1(eq))) {
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/* Make sure we read the AEQ entry after we have checked the
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* ownership bit
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*/
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@ -3900,7 +3898,6 @@ static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
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u32 cqn;
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while ((ceqe = next_ceqe_sw_v1(eq))) {
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/* Make sure we read CEQ entry after we have checked the
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* ownership bit
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*/
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@ -419,7 +419,7 @@ struct hns_roce_wqe_data_seg {
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struct hns_roce_wqe_raddr_seg {
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__le32 rkey;
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__le32 len;/* reserved */
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__le32 len; /* reserved */
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__le64 raddr;
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};
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@ -1025,8 +1025,8 @@ static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hnae3_handle *handle = priv->handle;
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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unsigned long instance_stage; /* the current instance stage */
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unsigned long reset_stage; /* the current reset stage */
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unsigned long instance_stage; /* the current instance stage */
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unsigned long reset_stage; /* the current reset stage */
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unsigned long reset_cnt;
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bool sw_resetting;
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bool hw_resetting;
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@ -2451,7 +2451,6 @@ static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
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if (i < (pg_num - 1))
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entry[i].blk_ba1_nxt_ptr |=
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(i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S;
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}
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link_tbl->npages = pg_num;
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link_tbl->pg_sz = buf_chk_sz;
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@ -5619,16 +5618,14 @@ static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
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case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
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hns_roce_cq_event(hr_dev, cqn, event_type);
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break;
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case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
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break;
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case HNS_ROCE_EVENT_TYPE_MB:
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hns_roce_cmd_event(hr_dev,
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le16_to_cpu(aeqe->event.cmd.token),
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aeqe->event.cmd.status,
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le64_to_cpu(aeqe->event.cmd.out_param));
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break;
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case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
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case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
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break;
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case HNS_ROCE_EVENT_TYPE_FLR:
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break;
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default:
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@ -449,7 +449,7 @@ struct hns_roce_srq_context {
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#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
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#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
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enum{
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enum {
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V2_MPT_ST_VALID = 0x1,
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V2_MPT_ST_FREE = 0x2,
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};
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@ -1094,9 +1094,9 @@ struct hns_roce_v2_ud_send_wqe {
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u8 sgid_index;
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u8 smac_index;
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u8 dgid[GID_LEN_V2];
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};
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#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
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#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
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#define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
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#define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
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@ -555,8 +555,8 @@ error_failed_setup_mtu_mac:
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static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
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{
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int ret;
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struct device *dev = hr_dev->dev;
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int ret;
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ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
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HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
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@ -713,8 +713,8 @@ err_unmap_dmpt:
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*/
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static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
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{
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int ret;
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struct device *dev = hr_dev->dev;
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int ret;
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spin_lock_init(&hr_dev->sm_lock);
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spin_lock_init(&hr_dev->bt_cmd_lock);
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@ -838,8 +838,8 @@ void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
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int hns_roce_init(struct hns_roce_dev *hr_dev)
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{
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int ret;
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struct device *dev = hr_dev->dev;
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int ret;
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if (hr_dev->hw->reset) {
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ret = hr_dev->hw->reset(hr_dev, true);
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@ -167,10 +167,10 @@ static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
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static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
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struct hns_roce_mr *mr)
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{
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int ret;
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unsigned long mtpt_idx = key_to_hw_index(mr->key);
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struct device *dev = hr_dev->dev;
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struct hns_roce_cmd_mailbox *mailbox;
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struct device *dev = hr_dev->dev;
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int ret;
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/* Allocate mailbox memory */
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mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
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@ -113,8 +113,8 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
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static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
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enum hns_roce_event type)
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{
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struct ib_event event;
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struct ib_qp *ibqp = &hr_qp->ibqp;
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struct ib_event event;
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if (ibqp->event_handler) {
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event.device = ibqp->device;
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@ -239,7 +239,6 @@ static int alloc_srq_idx(struct hns_roce_dev *hr_dev, struct hns_roce_srq *srq,
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err = -ENOMEM;
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goto err_idx_mtr;
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}
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}
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return 0;
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