Drop code for CRISv10 CPU simulator
That simulator is dead and redundant. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
This commit is contained in:
Jesper Nilsson
Родитель
e7672be573
Коммит
e269a86941
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@ -122,12 +122,6 @@ config ETRAX100LX_V2
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help
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Support version 2 of the ETRAX 100LX.
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config SVINTO_SIM
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bool "ETRAX-100LX-for-xsim-simulator"
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select ARCH_USES_GETTIMEOFFSET
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help
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Support the xsim ETRAX Simulator.
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config ETRAXFS
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bool "ETRAX-FS-V32"
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help
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@ -1,4 +1,3 @@
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# $Id: Makefile,v 1.6 2004/12/13 12:21:51 starvik Exp $
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#
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# Makefile for the linux kernel.
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#
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@ -19,7 +19,6 @@
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#include <linux/delay.h>
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#include <linux/tty.h>
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#include <arch/svinto.h>
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#include <asm/io.h> /* Get SIMCOUT. */
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extern void reset_watchdog(void);
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@ -318,12 +317,6 @@ console_write(struct console *co, const char *buf, unsigned int len)
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if (!port)
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return;
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#ifdef CONFIG_SVINTO_SIM
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/* no use to simulate the serial debug output */
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SIMCOUT(buf, len);
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return;
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#endif
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console_write_direct(co, buf, len);
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}
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@ -457,7 +457,7 @@ IRQ1_interrupt:
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ba _Rexit ; Return the standard way
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nop
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wdog:
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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;; Check if we're waiting for reset to happen, as signalled by
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;; hard_reset_now setting cause_of_death to a magic value. If so, just
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;; get stuck until reset happens.
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@ -523,7 +523,7 @@ _watchdogmsg:
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.ascii "Oops: bitten by watchdog\n\0"
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.previous
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#endif /* CONFIG_ETRAX_WATCHDOG and not CONFIG_SVINTO_SIM */
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#endif /* CONFIG_ETRAX_WATCHDOG */
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spurious_interrupt:
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di
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@ -168,13 +168,11 @@ _inflash:
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#endif
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;; Set up waitstates etc according to kernel configuration.
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#ifndef CONFIG_SVINTO_SIM
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move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
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move.d $r0, [R_WAITSTATES]
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move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
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move.d $r0, [R_BUS_CONFIG]
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#endif
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;; We need to initialze DRAM registers before we start using the DRAM
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@ -466,7 +464,6 @@ no_command_line:
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move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
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#ifndef CONFIG_SVINTO_SIM
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move.d $r0,[R_GEN_CONFIG]
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#if 0
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@ -701,8 +698,6 @@ no_command_line:
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move.b $r0,[R_SERIAL3_TR_CTRL]
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#endif
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#endif /* CONFIG_SVINTO_SIM */
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jump start_kernel ; jump into the C-function start_kernel in init/main.c
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.data
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@ -5,7 +5,7 @@
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*
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* Authors: Bjorn Wesen (bjornw@axis.com)
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*
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* This file contains the interrupt vectors and some
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* This file contains the interrupt vectors and some
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* helper functions
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*
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*/
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@ -182,19 +182,14 @@ void do_multiple_IRQ(struct pt_regs* regs)
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setting the irq vector table.
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*/
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void __init
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init_IRQ(void)
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void __init init_IRQ(void)
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{
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int i;
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/* clear all interrupt masks */
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#ifndef CONFIG_SVINTO_SIM
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*R_IRQ_MASK0_CLR = 0xffffffff;
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*R_IRQ_MASK1_CLR = 0xffffffff;
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*R_IRQ_MASK2_CLR = 0xffffffff;
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#endif
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*R_VECT_MASK_CLR = 0xffffffff;
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for (i = 0; i < 256; i++)
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@ -211,25 +206,20 @@ init_IRQ(void)
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executed by the associated break handler, rather than just a jump
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address. therefore we need to setup a default breakpoint handler
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for all breakpoints */
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for (i = 0; i < 16; i++)
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set_break_vector(i, do_sigtrap);
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/* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
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set_int_vector(15, multiple_interrupt);
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/* 0 and 1 which are special breakpoint/NMI traps */
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/* 0 and 1 which are special breakpoint/NMI traps */
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set_int_vector(0, hwbreakpoint);
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set_int_vector(1, IRQ1_interrupt);
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/* and irq 14 which is the mmu bus fault handler */
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set_int_vector(14, mmu_bus_fault);
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/* setup the system-call trap, which is reached by BREAK 13 */
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set_break_vector(13, system_call);
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/* setup a breakpoint handler for debugging used for both user and
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@ -14,7 +14,6 @@
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <arch/svinto.h>
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#include <linux/init.h>
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#include <arch/system.h>
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#include <linux/ptrace.h>
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@ -56,14 +55,14 @@ void hard_reset_now (void)
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* code to know about it than the watchdog handler in entry.S and
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* this code, implementing hard reset through the watchdog.
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*/
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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extern int cause_of_death;
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#endif
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printk("*** HARD RESET ***\n");
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local_irq_disable();
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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cause_of_death = 0xbedead;
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#else
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/* Since we dont plan to keep on resetting the watchdog,
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@ -14,7 +14,6 @@
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <arch/svinto.h>
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#include <asm/types.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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@ -34,7 +33,7 @@ unsigned long get_ns_in_jiffie(void)
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local_irq_save(flags);
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timer_count = *R_TIMER0_DATA;
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presc_count = *R_TIM_PRESC_STATUS;
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presc_count = *R_TIM_PRESC_STATUS;
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/* presc_count might be wrapped */
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t1 = *R_TIMER0_DATA;
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@ -50,7 +49,7 @@ unsigned long get_ns_in_jiffie(void)
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presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
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}
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ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
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ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
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( (presc_count) * (1000000000/PRESCALE_FREQ));
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return ns;
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}
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@ -80,7 +79,7 @@ static u32 cris_v10_gettimeoffset(void)
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* by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
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* and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
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* described in the table below:
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*
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*
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* Watchdog Value written:
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* state: To enable: To key: Operation:
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* -------- ---------- ------- ----------
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@ -89,15 +88,15 @@ static u32 cris_v10_gettimeoffset(void)
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* started 0 ~key Stop watchdog
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* started 1 ~key Restart watchdog with key = ~key.
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* started X new_key_val Change key to new_key_val.
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*
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*
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* Note: '~' is the bitwise NOT operator.
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*
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*
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*/
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/* right now, starting the watchdog is the same as resetting it */
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#define start_watchdog reset_watchdog
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#ifdef CONFIG_ETRAX_WATCHDOG
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static int watchdog_key = 0; /* arbitrary number */
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#endif
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@ -107,10 +106,9 @@ static int watchdog_key = 0; /* arbitrary number */
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#define WATCHDOG_MIN_FREE_PAGES 8
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void
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reset_watchdog(void)
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void reset_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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/* only keep watchdog happy as long as we have memory left! */
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if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
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/* reset the watchdog with the inverse of the old key */
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@ -123,28 +121,23 @@ reset_watchdog(void)
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/* stop the watchdog - we still need the correct key */
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void
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stop_watchdog(void)
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void stop_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#ifdef CONFIG_ETRAX_WATCHDOG
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watchdog_key ^= 0x7; /* invert key, which is 3 bits */
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*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
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IO_STATE(R_WATCHDOG, enable, stop);
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#endif
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#endif
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}
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extern void cris_do_profile(struct pt_regs *regs);
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "xtime_update()" routine every clocktick
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*/
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//static unsigned short myjiff; /* used by our debug routine print_timestamp */
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extern void cris_do_profile(struct pt_regs *regs);
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static inline irqreturn_t
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timer_interrupt(int irq, void *dev_id)
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static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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/* acknowledge the timer irq */
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@ -160,20 +153,18 @@ timer_interrupt(int irq, void *dev_id)
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IO_STATE( R_TIMER_CTRL, tm0, run) |
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IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
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#else
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*R_TIMER_CTRL = r_timer_ctrl_shadow |
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IO_STATE(R_TIMER_CTRL, i0, clr);
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*R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
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#endif
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/* reset watchdog otherwise it resets us! */
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reset_watchdog();
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/* Update statistics. */
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update_process_times(user_mode(regs));
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/* call the real timer interrupt handler */
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xtime_update(1);
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cris_do_profile(regs); /* Save profiling information */
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return IRQ_HANDLED;
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}
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@ -186,16 +177,15 @@ static struct irqaction irq2 = {
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.name = "timer",
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};
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void __init
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time_init(void)
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{
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void __init time_init(void)
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{
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arch_gettimeoffset = cris_v10_gettimeoffset;
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/* probe for the RTC and read it if it exists
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* Before the RTC can be probed the loops_per_usec variable needs
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* to be initialized to make usleep work. A better value for
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* loops_per_usec is calculated by the kernel later once the
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* clock has started.
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/* probe for the RTC and read it if it exists
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* Before the RTC can be probed the loops_per_usec variable needs
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* to be initialized to make usleep work. A better value for
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* loops_per_usec is calculated by the kernel later once the
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* clock has started.
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*/
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loops_per_usec = 50;
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@ -206,7 +196,7 @@ time_init(void)
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* Remember that linux/timex.h contains #defines that rely on the
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* timer settings below (hz and divide factor) !!!
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*/
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#ifdef USE_CASCADE_TIMERS
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*R_TIMER_CTRL =
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IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
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@ -217,8 +207,8 @@ time_init(void)
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IO_STATE( R_TIMER_CTRL, i0, nop) |
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IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
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IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
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*R_TIMER_CTRL = r_timer_ctrl_shadow =
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*R_TIMER_CTRL = r_timer_ctrl_shadow =
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IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
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IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
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IO_STATE( R_TIMER_CTRL, i1, nop) |
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@ -228,18 +218,18 @@ time_init(void)
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IO_STATE( R_TIMER_CTRL, tm0, run) |
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IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
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#else
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*R_TIMER_CTRL =
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IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
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*R_TIMER_CTRL =
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IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
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IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
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IO_STATE(R_TIMER_CTRL, i1, nop) |
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IO_STATE(R_TIMER_CTRL, i1, nop) |
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IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
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IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
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IO_STATE(R_TIMER_CTRL, i0, nop) |
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IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
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IO_STATE(R_TIMER_CTRL, clksel0, flexible);
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*R_TIMER_CTRL = r_timer_ctrl_shadow =
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IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
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IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
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IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
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IO_STATE(R_TIMER_CTRL, i1, nop) |
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IO_STATE(R_TIMER_CTRL, tm1, run) |
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@ -251,16 +241,14 @@ time_init(void)
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*R_TIMER_PRESCALE = PRESCALE_VALUE;
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#endif
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*R_IRQ_MASK0_SET =
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IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
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/* now actually register the timer irq handler that calls timer_interrupt() */
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/* unmask the timer irq */
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*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
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/* now actually register the irq handler that calls timer_interrupt() */
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setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
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/* enable watchdog if we should use one */
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#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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printk("Enabling watchdog...\n");
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start_watchdog();
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@ -273,9 +261,7 @@ time_init(void)
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driver or infrastructure support yet. */
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asm ("setf m");
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*R_IRQ_MASK0_SET =
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IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
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*R_VECT_MASK_SET =
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IO_STATE(R_VECT_MASK_SET, nmi, set);
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*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
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*R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
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#endif
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}
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@ -5,9 +5,7 @@
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* Note: This file may not modify r9 because r9 is used to carry
|
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* information from the decompresser to the kernel
|
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*
|
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* Copyright (C) 2000, 2001 Axis Communications AB
|
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*
|
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* Authors: Mikael Starvik (starvik@axis.com)
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* Copyright (C) 2000-2012 Axis Communications AB
|
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*
|
||||
*/
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||||
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@ -18,16 +16,15 @@
|
|||
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||||
|
||||
;; WARNING! The registers r8 and r9 are used as parameters carrying
|
||||
;; information from the decompressor (if the kernel was compressed).
|
||||
;; information from the decompressor (if the kernel was compressed).
|
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;; They should not be used in the code below.
|
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|
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#ifndef CONFIG_SVINTO_SIM
|
||||
move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
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move.d $r0, [R_WAITSTATES]
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||||
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move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
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move.d $r0, [R_BUS_CONFIG]
|
||||
|
||||
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#ifndef CONFIG_ETRAX_SDRAM
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move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
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move.d $r0, [R_DRAM_CONFIG]
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||||
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@ -38,14 +35,14 @@
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;; Samsung SDRAMs seem to require to be initialized twice to work properly.
|
||||
moveq 2, $r6
|
||||
_sdram_init:
|
||||
|
||||
|
||||
; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
|
||||
|
||||
|
||||
; Bank configuration
|
||||
move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
|
||||
move.d $r0, [R_SDRAM_CONFIG]
|
||||
|
||||
; Calculate value of mrs_data
|
||||
; Calculate value of mrs_data
|
||||
; CAS latency = 2 && bus_width = 32 => 0x40
|
||||
; CAS latency = 3 && bus_width = 32 => 0x60
|
||||
; CAS latency = 2 && bus_width = 16 => 0x20
|
||||
|
|
@ -56,22 +53,22 @@ _sdram_init:
|
|||
and.d 0x00ff0000, $r2
|
||||
bne _set_timing
|
||||
lsrq 16, $r2
|
||||
|
||||
|
||||
move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
|
||||
move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
|
||||
move.d $r1, $r3
|
||||
and.d 0x03, $r1 ; Get CAS latency
|
||||
and.d 0x03, $r1 ; Get CAS latency
|
||||
and.d 0x1000, $r3 ; 50 or 100 MHz?
|
||||
beq _speed_50
|
||||
nop
|
||||
_speed_100:
|
||||
_speed_100:
|
||||
cmp.d 0x00, $r1 ; CAS latency = 2?
|
||||
beq _bw_check
|
||||
nop
|
||||
or.d 0x20, $r2 ; CAS latency = 3
|
||||
or.d 0x20, $r2 ; CAS latency = 3
|
||||
ba _bw_check
|
||||
nop
|
||||
_speed_50:
|
||||
_speed_50:
|
||||
cmp.d 0x01, $r1 ; CAS latency = 2?
|
||||
beq _bw_check
|
||||
nop
|
||||
|
|
@ -86,19 +83,19 @@ _bw_check:
|
|||
; Set timing parameters. Starts master clock
|
||||
_set_timing:
|
||||
move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
|
||||
and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
|
||||
and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
|
||||
or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
|
||||
move.d $r1, $r5
|
||||
or.d 0x0000c000, $r1 ; ref = disable
|
||||
lslq 16, $r2 ; mrs data starts at bit 16
|
||||
or.d $r2, $r1
|
||||
move.d $r1, [R_SDRAM_TIMING]
|
||||
|
||||
or.d $r2, $r1
|
||||
move.d $r1, [R_SDRAM_TIMING]
|
||||
|
||||
; Wait 200us
|
||||
move.d 10000, $r2
|
||||
1: bne 1b
|
||||
subq 1, $r2
|
||||
|
||||
|
||||
; Issue initialization command sequence
|
||||
move.d _sdram_commands_start, $r2
|
||||
and.d 0x000fffff, $r2 ; Make sure commands are read from flash
|
||||
|
|
@ -144,7 +141,6 @@ _sdram_commands_start:
|
|||
.byte 2 ; refresh
|
||||
.byte 0 ; nop
|
||||
.byte 1 ; mrs
|
||||
.byte 0 ; nop
|
||||
_sdram_commands_end:
|
||||
#endif
|
||||
.byte 0 ; nop
|
||||
_sdram_commands_end:
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -50,7 +50,6 @@
|
|||
|
||||
nop
|
||||
di
|
||||
#ifndef CONFIG_SVINTO_SIM
|
||||
;; setup port PA and PB default initial directions and data
|
||||
;; (so we can flash LEDs, and so that DTR and others are set)
|
||||
|
||||
|
|
@ -67,7 +66,6 @@
|
|||
;; We need to setup the bus registers before we start using the DRAM
|
||||
#include "../../lib/dram_init.S"
|
||||
|
||||
#endif
|
||||
;; Setup the stack to a suitably high address.
|
||||
;; We assume 8 MB is the minimum DRAM in an eLinux
|
||||
;; product and put the sp at the top for now.
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
#ifndef _ASM_ARCH_CRIS_IO_H
|
||||
#define _ASM_ARCH_CRIS_IO_H
|
||||
|
||||
#include <arch/svinto.h>
|
||||
|
||||
/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
|
||||
|
||||
extern unsigned long gen_config_ii_shadow;
|
||||
|
|
@ -34,7 +32,7 @@ extern volatile unsigned long *port_csp4_addr;
|
|||
|
||||
/* The LED's on various Etrax-based products are set differently. */
|
||||
|
||||
#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM)
|
||||
#if defined(CONFIG_ETRAX_NO_LEDS)
|
||||
#undef CONFIG_ETRAX_PA_LEDS
|
||||
#undef CONFIG_ETRAX_PB_LEDS
|
||||
#undef CONFIG_ETRAX_CSP0_LEDS
|
||||
|
|
@ -171,29 +169,4 @@ extern volatile unsigned long *port_csp4_addr;
|
|||
#define SOFT_SHUTDOWN()
|
||||
#endif
|
||||
|
||||
/* Console I/O for simulated etrax100. Use #ifdef so erroneous
|
||||
use will be evident. */
|
||||
#ifdef CONFIG_SVINTO_SIM
|
||||
/* Let's use the ucsim interface since it lets us do write(2, ...) */
|
||||
#define SIMCOUT(s,len) \
|
||||
asm ("moveq 4,$r9 \n\t" \
|
||||
"moveq 2,$r10 \n\t" \
|
||||
"move.d %0,$r11 \n\t" \
|
||||
"move.d %1,$r12 \n\t" \
|
||||
"push $irp \n\t" \
|
||||
"move 0f,$irp \n\t" \
|
||||
"jump -6809 \n" \
|
||||
"0: \n\t" \
|
||||
"pop $irp" \
|
||||
: : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory")
|
||||
#define TRACE_ON() __extension__ \
|
||||
({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \
|
||||
(255)); _Foofoo; })
|
||||
|
||||
#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0)
|
||||
#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0)
|
||||
#define CRIS_CYCLES() __extension__ \
|
||||
({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;})
|
||||
#endif /* ! defined CONFIG_SVINTO_SIM */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
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