SoCFPGA DTS updates for v5.8

- Leave the FPGA bridges disabled in base dtsi
 - Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi
 -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAl6+6cMUHGRpbmd1eWVu
 QGtlcm5lbC5vcmcACgkQGZQEC4GjKPQy2w/+KAzDC9PsZ+cx8qcb0t8BmB3N424G
 tIIHXD+dITnJomeu+W9Z/BHBTwHTfEnH2jaVjCpIb7bQtm8u2abf/cNz7PLdza5+
 6CX+uRWlerq42vWZuJAlT0PmTe1bi03+if7YRW09AlmR8z0LZ5kkyaJWhauPVC/V
 8eIvGEoOc75d9r8f+M2w+Q+mq3skIVFJuQyY5pFQCzS2QAgKO6K6gYzj5vTTnDrH
 9hZ13tPWTg7GioqoeApfzd2tOTdjADTS33C24/gwroWJuN9VxJnArTwhyfU5mWbQ
 SRQKNcPHxJIcITV9vvCY+B6dUG6PqAJzxH3lh2aA3ktpkPMqjLxg1tssrJFUgTK8
 NrrmNQ4cw75v0Y9Q0KSsNxiToTABnROTEpPkuNARq3uk3kEjyzxX/9Jp7e/eW/7k
 VnOU5x7OgyI8L6AoEmRlnkF4EBmsLrCMlwPBLcoLLNJz+VZ4qiNpShEzlfesqW6Q
 1/1FL9xBMH86djma0WT54fZnCWSiIDjORKQ3zbIrNJqkA9CK2Do0X7KCzhsbPHKn
 3J9cPxrGBJ+4cprQZj1Uc1rce33JaYQytryNXbfAQat37Sp50sEe1YrtmiMmY/ab
 TnzaIGqludJBZr+czrCPq35kjf8WoUfVGuyTT8/zKUsKxl2HYIAEvEs4ebCnLZ+X
 a8UTu+xKVlHk/tw=
 =UMA8
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.8
- Leave the FPGA bridges disabled in base dtsi
- Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi

* tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges
  ARM: dts: socfgpa: set bridges status to disabled

Link: https://lore.kernel.org/r/20200515193029.11318-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arch/arm/boot/dts/socfpga.dtsi

@@ -531,6 +531,7 @@
 			reg = <0xff400000 0x100000>;
 			resets = <&rst LWHPS2FPGA_RESET>;
 			clocks = <&l4_main_clk>;
+			status = "disabled";
 		};
 
 		fpga_bridge1: fpga_bridge@ff500000 {
@@ -538,6 +539,21 @@
 			reg = <0xff500000 0x10000>;
 			resets = <&rst HPS2FPGA_RESET>;
 			clocks = <&l4_main_clk>;
+			status = "disabled";
+		};
+
+		fpga_bridge2: fpga-bridge@ff600000 {
+			compatible = "altr,socfpga-fpga2hps-bridge";
+			reg = <0xff600000 0x100000>;
+			resets = <&rst FPGA2HPS_RESET>;
+			clocks = <&l4_main_clk>;
+			status = "disabled";
+		};
+
+		fpga_bridge3: fpga-bridge@ffc25080 {
+			compatible = "altr,socfpga-fpga2sdram-bridge";
+			reg = <0xffc25080 0x4>;
+			status = "disabled";
 		};
 
 		fpgamgr0: fpgamgr@ff706000 {