spi: lantiq: switch to use modern name
Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230807124105.3429709-21-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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810ee62dd8
Коммит
ea11a8bb79
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@ -92,7 +92,7 @@
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#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
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#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
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#define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
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#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
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#define LTQ_SPI_STAT_MS BIT(1) /* Host/target select bit */
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#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
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#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
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LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
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@ -110,8 +110,8 @@
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#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
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#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
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#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
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#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
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#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
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#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set host select bit */
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#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear host select bit */
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#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
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#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
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#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
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@ -163,7 +163,7 @@ struct lantiq_ssc_hwcfg {
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};
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struct lantiq_ssc_spi {
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struct spi_master *master;
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struct spi_controller *host;
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struct device *dev;
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void __iomem *regbase;
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struct clk *spi_clk;
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@ -367,7 +367,7 @@ static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
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hw_setup_bits_per_word(spi, spi->bits_per_word);
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hw_setup_clock_mode(spi, SPI_MODE_0);
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/* Enable master mode and clear error flags */
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/* Enable host mode and clear error flags */
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lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
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LTQ_SPI_WHBSTATE_CLR_ERRORS,
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LTQ_SPI_WHBSTATE);
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@ -387,8 +387,8 @@ static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
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static int lantiq_ssc_setup(struct spi_device *spidev)
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{
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struct spi_master *master = spidev->master;
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struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
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struct spi_controller *host = spidev->controller;
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struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
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unsigned int cs = spi_get_chipselect(spidev, 0);
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u32 gpocon;
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@ -416,10 +416,10 @@ static int lantiq_ssc_setup(struct spi_device *spidev)
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return 0;
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}
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static int lantiq_ssc_prepare_message(struct spi_master *master,
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static int lantiq_ssc_prepare_message(struct spi_controller *host,
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struct spi_message *message)
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{
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struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
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struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
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hw_enter_config_mode(spi);
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hw_setup_clock_mode(spi, message->spi->mode);
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@ -461,10 +461,10 @@ static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
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lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
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}
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static int lantiq_ssc_unprepare_message(struct spi_master *master,
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static int lantiq_ssc_unprepare_message(struct spi_controller *host,
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struct spi_message *message)
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{
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struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
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struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
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flush_workqueue(spi->wq);
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@ -693,8 +693,8 @@ static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
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lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
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/* set bad status so it can be retried */
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if (spi->master->cur_msg)
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spi->master->cur_msg->status = -EIO;
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if (spi->host->cur_msg)
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spi->host->cur_msg->status = -EIO;
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queue_work(spi->wq, &spi->work);
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spin_unlock(&spi->lock);
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@ -772,22 +772,22 @@ static void lantiq_ssc_bussy_work(struct work_struct *work)
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u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
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if (!(stat & LTQ_SPI_STAT_BSY)) {
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spi_finalize_current_transfer(spi->master);
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spi_finalize_current_transfer(spi->host);
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return;
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}
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cond_resched();
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} while (!time_after_eq(jiffies, end));
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if (spi->master->cur_msg)
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spi->master->cur_msg->status = -EIO;
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spi_finalize_current_transfer(spi->master);
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if (spi->host->cur_msg)
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spi->host->cur_msg->status = -EIO;
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spi_finalize_current_transfer(spi->host);
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}
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static void lantiq_ssc_handle_err(struct spi_master *master,
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static void lantiq_ssc_handle_err(struct spi_controller *host,
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struct spi_message *message)
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{
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struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
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struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
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/* flush FIFOs on timeout */
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rx_fifo_flush(spi);
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@ -796,7 +796,7 @@ static void lantiq_ssc_handle_err(struct spi_master *master,
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static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
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{
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struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
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struct lantiq_ssc_spi *spi = spi_controller_get_devdata(spidev->controller);
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unsigned int cs = spi_get_chipselect(spidev, 0);
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u32 fgpo;
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@ -808,11 +808,11 @@ static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
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lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
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}
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static int lantiq_ssc_transfer_one(struct spi_master *master,
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static int lantiq_ssc_transfer_one(struct spi_controller *host,
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struct spi_device *spidev,
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struct spi_transfer *t)
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{
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struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
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struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
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hw_setup_transfer(spi, spidev, t);
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@ -904,7 +904,7 @@ MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
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static int lantiq_ssc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct spi_controller *host;
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struct lantiq_ssc_spi *spi;
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const struct lantiq_ssc_hwcfg *hwcfg;
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u32 id, supports_dma, revision;
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@ -913,33 +913,33 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
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hwcfg = of_device_get_match_data(dev);
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master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
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if (!master)
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host = spi_alloc_host(dev, sizeof(struct lantiq_ssc_spi));
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if (!host)
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return -ENOMEM;
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spi = spi_master_get_devdata(master);
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spi->master = master;
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spi = spi_controller_get_devdata(host);
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spi->host = host;
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spi->dev = dev;
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spi->hwcfg = hwcfg;
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platform_set_drvdata(pdev, spi);
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spi->regbase = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(spi->regbase)) {
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err = PTR_ERR(spi->regbase);
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goto err_master_put;
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goto err_host_put;
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}
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err = hwcfg->cfg_irq(pdev, spi);
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if (err)
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goto err_master_put;
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goto err_host_put;
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spi->spi_clk = devm_clk_get(dev, "gate");
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if (IS_ERR(spi->spi_clk)) {
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err = PTR_ERR(spi->spi_clk);
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goto err_master_put;
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goto err_host_put;
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}
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err = clk_prepare_enable(spi->spi_clk);
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if (err)
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goto err_master_put;
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goto err_host_put;
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/*
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* Use the old clk_get_fpi() function on Lantiq platform, till it
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@ -965,19 +965,19 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
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spi->bits_per_word = 8;
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spi->speed_hz = 0;
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master->dev.of_node = pdev->dev.of_node;
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master->num_chipselect = num_cs;
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master->use_gpio_descriptors = true;
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master->setup = lantiq_ssc_setup;
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master->set_cs = lantiq_ssc_set_cs;
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master->handle_err = lantiq_ssc_handle_err;
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master->prepare_message = lantiq_ssc_prepare_message;
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master->unprepare_message = lantiq_ssc_unprepare_message;
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master->transfer_one = lantiq_ssc_transfer_one;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
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SPI_LOOP;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
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SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
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host->dev.of_node = pdev->dev.of_node;
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host->num_chipselect = num_cs;
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host->use_gpio_descriptors = true;
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host->setup = lantiq_ssc_setup;
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host->set_cs = lantiq_ssc_set_cs;
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host->handle_err = lantiq_ssc_handle_err;
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host->prepare_message = lantiq_ssc_prepare_message;
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host->unprepare_message = lantiq_ssc_unprepare_message;
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host->transfer_one = lantiq_ssc_transfer_one;
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host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
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SPI_LOOP;
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host->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
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SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
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spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM);
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if (!spi->wq) {
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@ -998,9 +998,9 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
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"Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
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revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
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err = devm_spi_register_master(dev, master);
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err = devm_spi_register_controller(dev, host);
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if (err) {
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dev_err(dev, "failed to register spi_master\n");
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dev_err(dev, "failed to register spi host\n");
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goto err_wq_destroy;
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}
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@ -1012,8 +1012,8 @@ err_clk_put:
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clk_put(spi->fpi_clk);
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err_clk_disable:
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clk_disable_unprepare(spi->spi_clk);
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err_master_put:
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spi_master_put(master);
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err_host_put:
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spi_controller_put(host);
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return err;
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}
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