Patches to add necessary SoC related clockdomain and interconnect
data to make dm816x boot with basic devices. This finally gets dm816x into a usable shape for further work to happen after a few years of stalled effort of making this SoC to work with the mainline kernel. As most of the devices are similar to the other omap variants, we get at least serial, MMC, Ethernet, I2C, EDMA, pinctrl, SPI and GPMC working for these SoCs with the related device tree changes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUxn4KAAoJEBvUPslcq6VzV9sP/2MHuTxTTVKyApk6jSNjJIqE 02I08N7eMc/b46Ct3X4zzIne+k0k1p/gBUx1o4oWyq/L3O21QpMHMEV4wDknF9PO oUsyFB5psv6SScH6zA20CjWHJ3DSmbUEHeccy5TFeUFIjpfnSnzOfipE/x+A2q8F nccZ+oEDh2BA7EXE1WYu5+rxJJo6YB8WNKy8XTDxoeBaOapblDMGqPL2AlBdwaoH 2P6gd0V2HWHb99ajp5edyvXJeMQ1jF3ztygoePuYyCNm5EgeZukeAECuh5i3vqL+ a2P4snRJwJAp2y45DWKJaUW89H25mQ9ZF9N4ZmgUOrkv6IoWmC+qtL9iQxlBgiZa 3pA31jkQCUbwxTYSbthqnuoJynGw9joxiR0FSJyIzYrqQPQC6byrvNr6Moue4GFy 8D5gjwYBrd9J7h6fetjnRlTcnxBdtXablut1RiglS7SorNfHh4Ty/BGNH/QLvQkS /Z1krJ5zVlSt4KRFF4Fx3nIEu4/t3N3fiLRY3IDoelKNc8ghYGmZHT7LnQ5OKyAW 2leBIhjzgJUkukXYgQiQfgM8LlOnLDjcUa3u++C5dJvu2tw7dUeie+kjkwNg4k79 +cxdQpP6y3n6O5hWryoC3Odj4EvbTSX9izNNnaGKtFTl3drOe91ZX1gksFUh0ueJ RBTfzA6MqAscqk7CQ9ch =tGOy -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.20/dm816x-data' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc Merge "omap changes to make dm816x usable" from Tony Lindgren: Patches to add necessary SoC related clockdomain and interconnect data to make dm816x boot with basic devices. This finally gets dm816x into a usable shape for further work to happen after a few years of stalled effort of making this SoC to work with the mainline kernel. As most of the devices are similar to the other omap variants, we get at least serial, MMC, Ethernet, I2C, EDMA, pinctrl, SPI and GPMC working for these SoCs with the related device tree changes. * tag 'omap-for-v3.20/dm816x-data' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Add dm816x hwmod support ARM: OMAP2+: Add clock domain support for dm816x ARM: OMAP2+: Add board-generic.c entry for ti81xx ARM: OMAP2+: Disable omap3 PM init for ti81xx ARM: OMAP2+: Fix reboot for 81xx ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init ARM: OMAP2+: Fix ti81xx class type ARM: OMAP2+: Fix ti81xx devtype ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Коммит
ed1bd46bee
|
@ -58,6 +58,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
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# Restart code (OMAP4/5 currently in omap4-common.c)
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obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
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obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
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obj-$(CONFIG_SOC_TI81XX) += ti81xx-restart.o
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obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
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obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o
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obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
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@ -120,6 +121,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
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obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
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obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
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am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
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obj-$(CONFIG_SOC_TI81XX) += $(am33xx-43xx-prcm-common)
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obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
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obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
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$(am33xx-43xx-prcm-common)
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@ -170,6 +172,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
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obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
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obj-$(CONFIG_SOC_TI81XX) += $(clockdomain-common)
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obj-$(CONFIG_SOC_TI81XX) += clockdomains81xx_data.o
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obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
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obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
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obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
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@ -223,6 +227,7 @@ obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o
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obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o
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obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o
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obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o
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obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
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obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
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obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
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@ -144,6 +144,42 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
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MACHINE_END
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#endif
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#ifdef CONFIG_SOC_TI81XX
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static const char *const ti814x_boards_compat[] __initconst = {
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"ti,dm8148",
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"ti,dm814",
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NULL,
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};
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DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)")
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.reserve = omap_reserve,
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.map_io = ti81xx_map_io,
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.init_early = ti814x_init_early,
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.init_machine = omap_generic_init,
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.init_late = ti81xx_init_late,
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.init_time = omap3_gptimer_timer_init,
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.dt_compat = ti814x_boards_compat,
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.restart = ti81xx_restart,
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MACHINE_END
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static const char *const ti816x_boards_compat[] __initconst = {
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"ti,dm8168",
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"ti,dm816",
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NULL,
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};
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DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)")
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.reserve = omap_reserve,
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.map_io = ti81xx_map_io,
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.init_early = ti816x_init_early,
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.init_machine = omap_generic_init,
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.init_late = ti81xx_init_late,
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.init_time = omap3_gptimer_timer_init,
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.dt_compat = ti816x_boards_compat,
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.restart = ti81xx_restart,
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MACHINE_END
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#endif
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#ifdef CONFIG_SOC_AM33XX
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static const char *const am33xx_boards_compat[] __initconst = {
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"ti,am33xx",
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@ -620,6 +620,9 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
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for (i = 0; i < num_clocks; i++) {
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init_clk = clk_get(NULL, clk_names[i]);
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if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
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clk_names[i]))
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continue;
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clk_prepare_enable(init_clk);
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}
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}
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@ -216,6 +216,7 @@ extern void __init omap242x_clockdomains_init(void);
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extern void __init omap243x_clockdomains_init(void);
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extern void __init omap3xxx_clockdomains_init(void);
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extern void __init am33xx_clockdomains_init(void);
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extern void __init ti81xx_clockdomains_init(void);
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extern void __init omap44xx_clockdomains_init(void);
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extern void __init omap54xx_clockdomains_init(void);
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extern void __init dra7xx_clockdomains_init(void);
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@ -0,0 +1,194 @@
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/*
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* TI81XX Clock Domain data.
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*
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* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
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* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm81xx.h"
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/*
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* Note that 814x seems to have HWSUP_SWSUP for many clockdomains
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* while 816x does not. According to the TRM, 816x only has HWSUP
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* for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
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* seems to have the related ifdef the wrong way around claiming
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* 816x supports HWSUP while 814x does not. For now, we only set
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* HWSUP for ALWON_L3_FAST as that seems to be supported for both
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* dm814x and dm816x.
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*/
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/* Common for 81xx */
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static struct clockdomain alwon_l3_slow_81xx_clkdm = {
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.name = "alwon_l3s_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain alwon_l3_med_81xx_clkdm = {
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.name = "alwon_l3_med_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain alwon_l3_fast_81xx_clkdm = {
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.name = "alwon_l3_fast_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain alwon_ethernet_81xx_clkdm = {
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.name = "alwon_ethernet_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ETHERNET_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mmu_81xx_clkdm = {
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.name = "mmu_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_MMU_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mmu_cfg_81xx_clkdm = {
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.name = "mmu_cfg_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_MMUCFG_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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/* 816x only */
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static struct clockdomain alwon_mpu_816x_clkdm = {
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.name = "alwon_mpu_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain active_gem_816x_clkdm = {
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.name = "active_gem_clkdm",
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.pwrdm = { .name = "active_pwrdm" },
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.cm_inst = TI816X_CM_ACTIVE_MOD,
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.clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd0_816x_clkdm = {
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.name = "ivahd0_clkdm",
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.pwrdm = { .name = "ivahd0_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD0_MOD,
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.clkdm_offs = TI816X_CM_IVAHD0_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd1_816x_clkdm = {
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.name = "ivahd1_clkdm",
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.pwrdm = { .name = "ivahd1_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD1_MOD,
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.clkdm_offs = TI816X_CM_IVAHD1_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd2_816x_clkdm = {
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.name = "ivahd2_clkdm",
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.pwrdm = { .name = "ivahd2_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD2_MOD,
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.clkdm_offs = TI816X_CM_IVAHD2_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain sgx_816x_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.cm_inst = TI816X_CM_SGX_MOD,
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.clkdm_offs = TI816X_CM_SGX_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_l3_med_816x_clkdm = {
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.name = "default_l3_med_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
|
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.cm_inst = TI816X_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
|
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.flags = CLKDM_CAN_SWSUP,
|
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};
|
||||
|
||||
static struct clockdomain default_ducati_816x_clkdm = {
|
||||
.name = "default_ducati_clkdm",
|
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.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
|
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.flags = CLKDM_CAN_SWSUP,
|
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};
|
||||
|
||||
static struct clockdomain default_pci_816x_clkdm = {
|
||||
.name = "default_pci_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
|
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.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain default_l3_slow_816x_clkdm = {
|
||||
.name = "default_l3_slow_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_ti81xx[] __initdata = {
|
||||
&alwon_mpu_816x_clkdm,
|
||||
&alwon_l3_slow_81xx_clkdm,
|
||||
&alwon_l3_med_81xx_clkdm,
|
||||
&alwon_l3_fast_81xx_clkdm,
|
||||
&alwon_ethernet_81xx_clkdm,
|
||||
&mmu_81xx_clkdm,
|
||||
&mmu_cfg_81xx_clkdm,
|
||||
&active_gem_816x_clkdm,
|
||||
&ivahd0_816x_clkdm,
|
||||
&ivahd1_816x_clkdm,
|
||||
&ivahd2_816x_clkdm,
|
||||
&sgx_816x_clkdm,
|
||||
&default_l3_med_816x_clkdm,
|
||||
&default_ducati_816x_clkdm,
|
||||
&default_pci_816x_clkdm,
|
||||
&default_l3_slow_816x_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init ti81xx_clockdomains_init(void)
|
||||
{
|
||||
clkdm_register_platform_funcs(&am33xx_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_ti81xx);
|
||||
clkdm_complete_init();
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Clock domain register offsets for TI81XX.
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
|
||||
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
|
||||
|
||||
/* TI81XX common CM module offsets */
|
||||
#define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
|
||||
|
||||
/* TI816X CM module offsets */
|
||||
#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */
|
||||
#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */
|
||||
#define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
|
||||
#define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
|
||||
#define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
|
||||
#define TI816X_CM_SGX_MOD 0x0900 /* 256B */
|
||||
|
||||
/* ALWON */
|
||||
#define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
|
||||
#define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
|
||||
#define TI81XX_CM_ETHERNET_CLKDM 0x0004
|
||||
#define TI81XX_CM_MMU_CLKDM 0x000C
|
||||
#define TI81XX_CM_MMUCFG_CLKDM 0x0010
|
||||
#define TI81XX_CM_ALWON_MPU_CLKDM 0x001C
|
||||
#define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030
|
||||
|
||||
/* ACTIVE */
|
||||
#define TI816X_CM_ACTIVE_GEM_CLKDM 0x0000
|
||||
|
||||
/* IVAHD0 */
|
||||
#define TI816X_CM_IVAHD0_CLKDM 0x0000
|
||||
|
||||
/* IVAHD1 */
|
||||
#define TI816X_CM_IVAHD1_CLKDM 0x0000
|
||||
|
||||
/* IVAHD2 */
|
||||
#define TI816X_CM_IVAHD2_CLKDM 0x0000
|
||||
|
||||
/* SGX */
|
||||
#define TI816X_CM_SGX_CLKDM 0x0000
|
||||
|
||||
/* DEFAULT */
|
||||
#define TI816X_CM_DEFAULT_L3_MED_CLKDM 0x0004
|
||||
#define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010
|
||||
#define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
|
||||
#define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018
|
||||
|
||||
#endif
|
|
@ -110,7 +110,8 @@ void omap3630_init_early(void);
|
|||
void omap3_init_early(void); /* Do not use this one */
|
||||
void am33xx_init_early(void);
|
||||
void am35xx_init_early(void);
|
||||
void ti81xx_init_early(void);
|
||||
void ti814x_init_early(void);
|
||||
void ti816x_init_early(void);
|
||||
void am33xx_init_early(void);
|
||||
void am43xx_init_early(void);
|
||||
void am43xx_init_late(void);
|
||||
|
@ -163,6 +164,14 @@ static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_TI81XX
|
||||
void ti81xx_restart(enum reboot_mode mode, const char *cmd);
|
||||
#else
|
||||
static inline void ti81xx_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
||||
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
|
||||
void omap44xx_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
|
|
@ -53,6 +53,7 @@
|
|||
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
|
||||
|
||||
/* TI81XX spefic control submodules */
|
||||
#define TI81XX_CONTROL_DEVBOOT 0x040
|
||||
#define TI81XX_CONTROL_DEVCONF 0x600
|
||||
|
||||
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
|
||||
|
@ -246,6 +247,9 @@
|
|||
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
|
||||
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
|
||||
|
||||
/* TI81XX CONTROL_DEVBOOT register offsets */
|
||||
#define TI81XX_CONTROL_STATUS (TI81XX_CONTROL_DEVBOOT + 0x000)
|
||||
|
||||
/* TI81XX CONTROL_DEVCONF register offsets */
|
||||
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
|
||||
|
||||
|
|
|
@ -56,6 +56,8 @@ int omap_type(void)
|
|||
|
||||
if (cpu_is_omap24xx()) {
|
||||
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
|
||||
} else if (cpu_is_ti81xx()) {
|
||||
val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
|
||||
} else if (soc_is_am33xx() || soc_is_am43xx()) {
|
||||
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
|
|
|
@ -492,27 +492,6 @@ void __init am35xx_init_early(void)
|
|||
omap_clk_soc_init = am35xx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init ti81xx_init_early(void)
|
||||
{
|
||||
omap2_set_globals_tap(OMAP343X_CLASS,
|
||||
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
|
||||
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
|
||||
NULL);
|
||||
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
|
||||
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
|
||||
omap3xxx_check_revision();
|
||||
ti81xx_check_features();
|
||||
omap3xxx_voltagedomains_init();
|
||||
omap3xxx_powerdomains_init();
|
||||
omap3xxx_clockdomains_init();
|
||||
omap3xxx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = ti81xx_dt_clk_init;
|
||||
else
|
||||
omap_clk_soc_init = omap3xxx_clk_init;
|
||||
}
|
||||
|
||||
void __init omap3_init_late(void)
|
||||
{
|
||||
omap_common_late_init();
|
||||
|
@ -551,11 +530,54 @@ void __init am35xx_init_late(void)
|
|||
void __init ti81xx_init_late(void)
|
||||
{
|
||||
omap_common_late_init();
|
||||
omap3_pm_init();
|
||||
omap2_clk_enable_autoidle_all();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_TI81XX
|
||||
void __init ti814x_init_early(void)
|
||||
{
|
||||
omap2_set_globals_tap(TI814X_CLASS,
|
||||
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
|
||||
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
|
||||
NULL);
|
||||
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
|
||||
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
|
||||
omap3xxx_check_revision();
|
||||
ti81xx_check_features();
|
||||
am33xx_prm_init();
|
||||
am33xx_cm_init();
|
||||
omap3xxx_voltagedomains_init();
|
||||
omap3xxx_powerdomains_init();
|
||||
ti81xx_clockdomains_init();
|
||||
ti81xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = ti81xx_dt_clk_init;
|
||||
}
|
||||
|
||||
void __init ti816x_init_early(void)
|
||||
{
|
||||
omap2_set_globals_tap(TI816X_CLASS,
|
||||
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
|
||||
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
|
||||
NULL);
|
||||
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
|
||||
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
|
||||
omap3xxx_check_revision();
|
||||
ti81xx_check_features();
|
||||
am33xx_prm_init();
|
||||
am33xx_cm_init();
|
||||
omap3xxx_voltagedomains_init();
|
||||
omap3xxx_powerdomains_init();
|
||||
ti81xx_clockdomains_init();
|
||||
ti81xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
if (of_have_populated_dt())
|
||||
omap_clk_soc_init = ti81xx_dt_clk_init;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
void __init am33xx_init_early(void)
|
||||
{
|
||||
|
|
|
@ -4142,7 +4142,7 @@ void __init omap_hwmod_init(void)
|
|||
soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
|
||||
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
|
||||
soc_ops.init_clkdm = _init_clkdm;
|
||||
} else if (soc_is_am33xx()) {
|
||||
} else if (cpu_is_ti816x() || soc_is_am33xx()) {
|
||||
soc_ops.enable_module = _omap4_enable_module;
|
||||
soc_ops.disable_module = _omap4_disable_module;
|
||||
soc_ops.wait_target_ready = _omap4_wait_target_ready;
|
||||
|
|
|
@ -763,6 +763,7 @@ extern int omap3xxx_hwmod_init(void);
|
|||
extern int omap44xx_hwmod_init(void);
|
||||
extern int omap54xx_hwmod_init(void);
|
||||
extern int am33xx_hwmod_init(void);
|
||||
extern int ti81xx_hwmod_init(void);
|
||||
extern int dra7xx_hwmod_init(void);
|
||||
int am43xx_hwmod_init(void);
|
||||
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -464,7 +464,7 @@ void __init omap3xxx_powerdomains_init(void)
|
|||
{
|
||||
unsigned int rev;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
|
||||
return;
|
||||
|
||||
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
|
||||
|
|
|
@ -571,6 +571,10 @@ static const struct of_device_id omap_prcm_dt_match_table[] = {
|
|||
{ .compatible = "ti,am3-scrm" },
|
||||
{ .compatible = "ti,am4-prcm" },
|
||||
{ .compatible = "ti,am4-scrm" },
|
||||
{ .compatible = "ti,dm814-prcm" },
|
||||
{ .compatible = "ti,dm814-scrm" },
|
||||
{ .compatible = "ti,dm816-prcm" },
|
||||
{ .compatible = "ti,dm816-scrm" },
|
||||
{ .compatible = "ti,omap2-prcm" },
|
||||
{ .compatible = "ti,omap2-scrm" },
|
||||
{ .compatible = "ti,omap3-prm" },
|
||||
|
|
|
@ -423,13 +423,13 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
|
||||
#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
|
||||
|
||||
#define TI816X_CLASS 0x81600034
|
||||
#define TI816X_CLASS 0x81600081
|
||||
#define TI8168_REV_ES1_0 TI816X_CLASS
|
||||
#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
|
||||
#define TI8168_REV_ES2_0 (TI816X_CLASS | (0x2 << 8))
|
||||
#define TI8168_REV_ES2_1 (TI816X_CLASS | (0x3 << 8))
|
||||
|
||||
#define TI814X_CLASS 0x81400034
|
||||
#define TI814X_CLASS 0x81400081
|
||||
#define TI8148_REV_ES1_0 TI814X_CLASS
|
||||
#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
|
||||
#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
|
||||
|
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include "iomap.h"
|
||||
#include "common.h"
|
||||
#include "control.h"
|
||||
#include "prm3xxx.h"
|
||||
|
||||
#define TI81XX_PRM_DEVICE_RSTCTRL 0x00a0
|
||||
#define TI81XX_GLOBAL_RST_COLD BIT(1)
|
||||
|
||||
/**
|
||||
* ti81xx_restart - trigger a software restart of the SoC
|
||||
* @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
|
||||
* @cmd: passed from the userspace program rebooting the system (if provided)
|
||||
*
|
||||
* Resets the SoC. For @cmd, see the 'reboot' syscall in
|
||||
* kernel/sys.c. No return value.
|
||||
*
|
||||
* NOTE: Warm reset does not seem to work, may require resetting
|
||||
* clocks to bypass mode.
|
||||
*/
|
||||
void ti81xx_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
omap2_prm_set_mod_reg_bits(TI81XX_GLOBAL_RST_COLD, 0,
|
||||
TI81XX_PRM_DEVICE_RSTCTRL);
|
||||
while (1);
|
||||
}
|
|
@ -146,6 +146,8 @@ static const struct of_device_id omap_timer_match[] __initconst = {
|
|||
{ .compatible = "ti,omap3430-timer", },
|
||||
{ .compatible = "ti,omap4430-timer", },
|
||||
{ .compatible = "ti,omap5430-timer", },
|
||||
{ .compatible = "ti,dm814-timer", },
|
||||
{ .compatible = "ti,dm816-timer", },
|
||||
{ .compatible = "ti,am335x-timer", },
|
||||
{ .compatible = "ti,am335x-timer-1ms", },
|
||||
{ }
|
||||
|
|
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