coresight-etb: add CoreSight ETB driver
This driver manages CoreSight ETB (Embedded Trace Buffer) which acts as a circular buffer sink collecting generated trace data. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Pratik Patel
Greg Kroah-Hartman
Родитель
dc161b9f01
Коммит
fdfc0d8a06
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@ -1368,5 +1368,13 @@ config CORESIGHT_SINK_TPIU
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for bridging the gap between the on-chip coresight components and a trace
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port collection engine, typically connected to an external host for use
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case capturing more traces than the on-board coresight memory can handle.
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config CORESIGHT_SINK_ETBV10
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bool "Coresight ETBv1.0 driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Embedded Trace Buffer version 1.0 driver
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that complies with the generic implementation of the component without
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special enhancement or added features.
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endif
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endmenu
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@ -5,3 +5,4 @@ obj-$(CONFIG_CORESIGHT) += coresight.o
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obj-$(CONFIG_OF) += of_coresight.o
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obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
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obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
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obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
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@ -0,0 +1,537 @@
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/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/seq_file.h>
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#include <linux/coresight.h>
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#include <linux/amba/bus.h>
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#include "coresight-priv.h"
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#define ETB_RAM_DEPTH_REG 0x004
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#define ETB_STATUS_REG 0x00c
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#define ETB_RAM_READ_DATA_REG 0x010
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#define ETB_RAM_READ_POINTER 0x014
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#define ETB_RAM_WRITE_POINTER 0x018
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#define ETB_TRG 0x01c
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#define ETB_CTL_REG 0x020
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#define ETB_RWD_REG 0x024
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#define ETB_FFSR 0x300
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#define ETB_FFCR 0x304
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#define ETB_ITMISCOP0 0xee0
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#define ETB_ITTRFLINACK 0xee4
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#define ETB_ITTRFLIN 0xee8
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#define ETB_ITATBDATA0 0xeeC
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#define ETB_ITATBCTR2 0xef0
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#define ETB_ITATBCTR1 0xef4
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#define ETB_ITATBCTR0 0xef8
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/* register description */
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/* STS - 0x00C */
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#define ETB_STATUS_RAM_FULL BIT(0)
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/* CTL - 0x020 */
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#define ETB_CTL_CAPT_EN BIT(0)
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/* FFCR - 0x304 */
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#define ETB_FFCR_EN_FTC BIT(0)
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#define ETB_FFCR_FON_MAN BIT(6)
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#define ETB_FFCR_STOP_FI BIT(12)
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#define ETB_FFCR_STOP_TRIGGER BIT(13)
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#define ETB_FFCR_BIT 6
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#define ETB_FFSR_BIT 1
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#define ETB_FRAME_SIZE_WORDS 4
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/**
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* struct etb_drvdata - specifics associated to an ETB component
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* @base: memory mapped base address for this component.
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* @dev: the device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @miscdev: specifics to handle "/dev/xyz.etb" entry.
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* @clk: the clock this component is associated to.
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* @spinlock: only one at a time pls.
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* @in_use: synchronise user space access to etb buffer.
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* @buf: area of memory where ETB buffer content gets sent.
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* @buffer_depth: size of @buf.
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* @enable: this ETB is being used.
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* @trigger_cntr: amount of words to store after a trigger.
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*/
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struct etb_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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struct miscdevice miscdev;
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struct clk *clk;
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spinlock_t spinlock;
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atomic_t in_use;
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u8 *buf;
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u32 buffer_depth;
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bool enable;
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u32 trigger_cntr;
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};
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static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
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{
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int ret;
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u32 depth = 0;
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ret = clk_prepare_enable(drvdata->clk);
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if (ret)
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return ret;
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/* RO registers don't need locking */
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depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
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clk_disable_unprepare(drvdata->clk);
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return depth;
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}
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static void etb_enable_hw(struct etb_drvdata *drvdata)
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{
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int i;
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u32 depth;
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CS_UNLOCK(drvdata->base);
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depth = drvdata->buffer_depth;
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/* reset write RAM pointer address */
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writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
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/* clear entire RAM buffer */
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for (i = 0; i < depth; i++)
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writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
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/* reset write RAM pointer address */
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writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
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/* reset read RAM pointer address */
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writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
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writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
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writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
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drvdata->base + ETB_FFCR);
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/* ETB trace capture enable */
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writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
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CS_LOCK(drvdata->base);
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}
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static int etb_enable(struct coresight_device *csdev)
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{
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struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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int ret;
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unsigned long flags;
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ret = clk_prepare_enable(drvdata->clk);
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if (ret)
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return ret;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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etb_enable_hw(drvdata);
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drvdata->enable = true;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "ETB enabled\n");
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return 0;
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}
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static void etb_disable_hw(struct etb_drvdata *drvdata)
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{
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u32 ffcr;
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CS_UNLOCK(drvdata->base);
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ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
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/* stop formatter when a stop has completed */
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ffcr |= ETB_FFCR_STOP_FI;
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writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
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/* manually generate a flush of the system */
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ffcr |= ETB_FFCR_FON_MAN;
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writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
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if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
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dev_err(drvdata->dev,
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"timeout observed when probing at offset %#x\n",
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ETB_FFCR);
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}
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/* disable trace capture */
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writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
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if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
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dev_err(drvdata->dev,
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"timeout observed when probing at offset %#x\n",
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ETB_FFCR);
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}
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CS_LOCK(drvdata->base);
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}
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static void etb_dump_hw(struct etb_drvdata *drvdata)
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{
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int i;
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u8 *buf_ptr;
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u32 read_data, depth;
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u32 read_ptr, write_ptr;
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u32 frame_off, frame_endoff;
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CS_UNLOCK(drvdata->base);
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read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
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write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
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frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
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frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
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if (frame_off) {
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dev_err(drvdata->dev,
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"write_ptr: %lu not aligned to formatter frame size\n",
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(unsigned long)write_ptr);
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dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
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(unsigned long)frame_off, (unsigned long)frame_endoff);
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write_ptr += frame_endoff;
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}
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if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
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& ETB_STATUS_RAM_FULL) == 0)
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writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
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else
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writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
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depth = drvdata->buffer_depth;
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buf_ptr = drvdata->buf;
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for (i = 0; i < depth; i++) {
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read_data = readl_relaxed(drvdata->base +
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ETB_RAM_READ_DATA_REG);
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*buf_ptr++ = read_data >> 0;
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*buf_ptr++ = read_data >> 8;
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*buf_ptr++ = read_data >> 16;
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*buf_ptr++ = read_data >> 24;
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}
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if (frame_off) {
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buf_ptr -= (frame_endoff * 4);
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for (i = 0; i < frame_endoff; i++) {
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*buf_ptr++ = 0x0;
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*buf_ptr++ = 0x0;
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*buf_ptr++ = 0x0;
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*buf_ptr++ = 0x0;
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}
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}
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writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
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CS_LOCK(drvdata->base);
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}
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static void etb_disable(struct coresight_device *csdev)
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{
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struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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unsigned long flags;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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etb_disable_hw(drvdata);
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etb_dump_hw(drvdata);
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drvdata->enable = false;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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clk_disable_unprepare(drvdata->clk);
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dev_info(drvdata->dev, "ETB disabled\n");
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}
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static const struct coresight_ops_sink etb_sink_ops = {
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.enable = etb_enable,
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.disable = etb_disable,
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};
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static const struct coresight_ops etb_cs_ops = {
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.sink_ops = &etb_sink_ops,
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};
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static void etb_dump(struct etb_drvdata *drvdata)
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{
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unsigned long flags;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->enable) {
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etb_disable_hw(drvdata);
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etb_dump_hw(drvdata);
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etb_enable_hw(drvdata);
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}
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "ETB dumped\n");
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}
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static int etb_open(struct inode *inode, struct file *file)
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{
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struct etb_drvdata *drvdata = container_of(file->private_data,
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struct etb_drvdata, miscdev);
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if (atomic_cmpxchg(&drvdata->in_use, 0, 1))
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return -EBUSY;
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dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
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return 0;
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}
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static ssize_t etb_read(struct file *file, char __user *data,
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size_t len, loff_t *ppos)
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{
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u32 depth;
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struct etb_drvdata *drvdata = container_of(file->private_data,
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struct etb_drvdata, miscdev);
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etb_dump(drvdata);
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depth = drvdata->buffer_depth;
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if (*ppos + len > depth * 4)
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len = depth * 4 - *ppos;
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if (copy_to_user(data, drvdata->buf + *ppos, len)) {
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dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
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return -EFAULT;
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}
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*ppos += len;
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dev_dbg(drvdata->dev, "%s: %d bytes copied, %d bytes left\n",
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__func__, len, (int) (depth * 4 - *ppos));
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return len;
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}
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static int etb_release(struct inode *inode, struct file *file)
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{
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struct etb_drvdata *drvdata = container_of(file->private_data,
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struct etb_drvdata, miscdev);
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atomic_set(&drvdata->in_use, 0);
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dev_dbg(drvdata->dev, "%s: released\n", __func__);
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return 0;
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}
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static const struct file_operations etb_fops = {
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.owner = THIS_MODULE,
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.open = etb_open,
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.read = etb_read,
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.release = etb_release,
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.llseek = no_llseek,
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};
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static ssize_t status_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int ret;
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unsigned long flags;
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u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
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u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
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struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
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ret = clk_prepare_enable(drvdata->clk);
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if (ret)
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goto out;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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CS_UNLOCK(drvdata->base);
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etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
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etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG);
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etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
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etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
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etb_trg = readl_relaxed(drvdata->base + ETB_TRG);
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etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG);
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etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR);
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etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
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CS_LOCK(drvdata->base);
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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clk_disable_unprepare(drvdata->clk);
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return sprintf(buf,
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"Depth:\t\t0x%x\n"
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"Status:\t\t0x%x\n"
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"RAM read ptr:\t0x%x\n"
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"RAM wrt ptr:\t0x%x\n"
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"Trigger cnt:\t0x%x\n"
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"Control:\t0x%x\n"
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"Flush status:\t0x%x\n"
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"Flush ctrl:\t0x%x\n",
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etb_rdr, etb_sr, etb_rrp, etb_rwp,
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etb_trg, etb_cr, etb_ffsr, etb_ffcr);
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out:
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return -EINVAL;
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}
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static DEVICE_ATTR_RO(status);
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static ssize_t trigger_cntr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
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unsigned long val = drvdata->trigger_cntr;
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return sprintf(buf, "%#lx\n", val);
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}
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static ssize_t trigger_cntr_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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int ret;
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unsigned long val;
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struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
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ret = kstrtoul(buf, 16, &val);
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if (ret)
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return ret;
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drvdata->trigger_cntr = val;
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return size;
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}
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static DEVICE_ATTR_RW(trigger_cntr);
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static struct attribute *coresight_etb_attrs[] = {
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&dev_attr_trigger_cntr.attr,
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&dev_attr_status.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(coresight_etb);
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static int etb_probe(struct amba_device *adev, const struct amba_id *id)
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{
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int ret;
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void __iomem *base;
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struct device *dev = &adev->dev;
|
||||
struct coresight_platform_data *pdata = NULL;
|
||||
struct etb_drvdata *drvdata;
|
||||
struct resource *res = &adev->res;
|
||||
struct coresight_desc *desc;
|
||||
struct device_node *np = adev->dev.of_node;
|
||||
|
||||
if (np) {
|
||||
pdata = of_get_coresight_platform_data(dev, np);
|
||||
if (IS_ERR(pdata))
|
||||
return PTR_ERR(pdata);
|
||||
adev->dev.platform_data = pdata;
|
||||
}
|
||||
|
||||
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata->dev = &adev->dev;
|
||||
dev_set_drvdata(dev, drvdata);
|
||||
|
||||
/* validity for the resource is already checked by the AMBA core */
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
drvdata->base = base;
|
||||
|
||||
spin_lock_init(&drvdata->spinlock);
|
||||
|
||||
drvdata->clk = adev->pclk;
|
||||
ret = clk_prepare_enable(drvdata->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
|
||||
clk_disable_unprepare(drvdata->clk);
|
||||
|
||||
if (drvdata->buffer_depth < 0)
|
||||
return -EINVAL;
|
||||
|
||||
drvdata->buf = devm_kzalloc(dev,
|
||||
drvdata->buffer_depth * 4, GFP_KERNEL);
|
||||
if (!drvdata->buf)
|
||||
return -ENOMEM;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
desc->type = CORESIGHT_DEV_TYPE_SINK;
|
||||
desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
|
||||
desc->ops = &etb_cs_ops;
|
||||
desc->pdata = pdata;
|
||||
desc->dev = dev;
|
||||
desc->groups = coresight_etb_groups;
|
||||
drvdata->csdev = coresight_register(desc);
|
||||
if (IS_ERR(drvdata->csdev))
|
||||
return PTR_ERR(drvdata->csdev);
|
||||
|
||||
drvdata->miscdev.name = pdata->name;
|
||||
drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
|
||||
drvdata->miscdev.fops = &etb_fops;
|
||||
ret = misc_register(&drvdata->miscdev);
|
||||
if (ret)
|
||||
goto err_misc_register;
|
||||
|
||||
dev_info(dev, "ETB initialized\n");
|
||||
return 0;
|
||||
|
||||
err_misc_register:
|
||||
coresight_unregister(drvdata->csdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int etb_remove(struct amba_device *adev)
|
||||
{
|
||||
struct etb_drvdata *drvdata = amba_get_drvdata(adev);
|
||||
|
||||
misc_deregister(&drvdata->miscdev);
|
||||
coresight_unregister(drvdata->csdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct amba_id etb_ids[] = {
|
||||
{
|
||||
.id = 0x0003b907,
|
||||
.mask = 0x0003ffff,
|
||||
},
|
||||
{ 0, 0},
|
||||
};
|
||||
|
||||
static struct amba_driver etb_driver = {
|
||||
.drv = {
|
||||
.name = "coresight-etb10",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = etb_probe,
|
||||
.remove = etb_remove,
|
||||
.id_table = etb_ids,
|
||||
};
|
||||
|
||||
static int __init etb_init(void)
|
||||
{
|
||||
return amba_driver_register(&etb_driver);
|
||||
}
|
||||
module_init(etb_init);
|
||||
|
||||
static void __exit etb_exit(void)
|
||||
{
|
||||
amba_driver_unregister(&etb_driver);
|
||||
}
|
||||
module_exit(etb_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver");
|
||||
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