Граф коммитов

9339 Коммитов

Автор SHA1 Сообщение Дата
Frieder Schrempf 30648e9f86 arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
We will move the FSL QSPI driver to the SPI framework soon. To
prepare and to make sure the full buswidth is used (as it is with
the current driver), let's add the right properties.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-16 16:24:01 +08:00
Frieder Schrempf a0578d2419 arm64: dts: Remove unused properties from FSL QSPI driver nodes
The properties 'num-cs' and 'bus-num' were never read by the driver
and can be removed.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-16 16:24:01 +08:00
Logan Gunthorpe d1402fc708 mm: introduce common STRUCT_PAGE_MAX_SHIFT define
This define is used by arm64 to calculate the size of the vmemmap
region.  It is defined as the log2 of the upper bound on the size of a
struct page.

We move it into mm_types.h so it can be defined properly instead of set
and checked with a build bug.  This also allows us to use the same
define for riscv.

Link: http://lkml.kernel.org/r/20181107205433.3875-2-logang@deltatee.com
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Andrew Morton <akpm@linux-foundation.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Christoph Hellwig <hch@lst.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-12-14 15:05:45 -08:00
Linus Torvalds eb6cf9f8cb - Invalidate the caches before clearing the DMA buffer via the
non-cacheable alias in the FORCE_CONTIGUOUS case
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fix from Catalin Marinas:
 "Invalidate the caches before clearing the DMA buffer via the
  non-cacheable alias in the FORCE_CONTIGUOUS case"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: dma-mapping: Fix FORCE_CONTIGUOUS buffer clearing
2018-12-14 09:36:41 -08:00
Miles Chen 12f799c8c7 arm64: kaslr: print PHYS_OFFSET in dump_kernel_offset()
When debug with kaslr, it is sometimes necessary to have PHYS_OFFSET to
perform linear virtual address to physical address translation.
Sometimes we're debugging with only few information such as a kernel log
and a symbol file, print PHYS_OFFSET in dump_kernel_offset() for that case.

Tested by:
echo c > /proc/sysrq-trigger
[   11.996161] SMP: stopping secondary CPUs
[   11.996732] Kernel Offset: 0x2522200000 from 0xffffff8008000000
[   11.996881] PHYS_OFFSET: 0xffffffeb40000000

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-14 09:33:49 +00:00
Vignesh R 5da94b5047 arm64: dts: ti: k3-am654: Enable main domain McSPI0
Enable McSPI0 of main domain and add DT node for the SPI NOR flash
connected to CS0.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:11 +02:00
Vignesh R 2cd7d393f4 arm64: dts: ti: k3-am654: Add McSPI DT nodes
There are 3 instances of McSPI in MCU domain and 4 instances in Main domain.
Add DT nodes for all McSPI instances present on AM654 SoC.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:11 +02:00
Vignesh R c484fc9572 arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes
Populate power-domain property for UART nodes, this is required for
Linux to enable UART clocks via PM calls. Without this UART instances
not initialized by bootloader (like main_uart1) fails to work in Linux.
Also, drop current-speed property from main_uart1 and main_uart2 nodes
as these UARTs are not initialized before Linux boots up and current
speed is unknown.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:10 +02:00
Vignesh R e577d79424 arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
Enable ECAP PWM which is used for LCD backlight.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:10 +02:00
Vignesh R 07c663b0ee arm64: dts: ti: k3-am65-main: Add ECAP PWM node
Add DT entry for ECAP0 PWM node present in main domain

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:10 +02:00
Vignesh R 19a1768fc3 arm64: dts: ti: k3-am654-base-board: Add I2C nodes
Add DT entries for I2C instances present in AM654 SoC.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:10 +02:00
Vignesh R 3f94859fd7 arm64: dts: ti: am654-base-board: Add pinmux for main uart0
Add pinmux for main uart0 that is serves as console on AM654 EVM

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14 09:57:10 +02:00
Tero Kristo 1d79b4375f arm64: dts: ti: k3-am65: Add pinctrl regions
Add pinctrl regions for the main and wkup mmr.

The range for main pinctrl region contains a gap
at offset 0x2e4, and because of this, the pinctrl
range is split into two sections.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2018-12-14 09:56:48 +02:00
Kamil Konieczny 72d7e948fe arm64: dts: exynos: Add IMEM clock controller to Exynos5433
Add node for IMEM clock controller, necessary for Security SubSystem
(SSS) on Exynos5433.

Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2018-12-13 22:07:36 +01:00
Christoph Hellwig 356da6d0cd dma-mapping: bypass indirect calls for dma-direct
Avoid expensive indirect calls in the fast path DMA mapping
operations by directly calling the dma_direct_* ops if we are using
the directly mapped DMA operations.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
2018-12-13 21:06:18 +01:00
Christoph Hellwig 55897af630 dma-direct: merge swiotlb_dma_ops into the dma_direct code
While the dma-direct code is (relatively) clean and simple we actually
have to use the swiotlb ops for the mapping on many architectures due
to devices with addressing limits.  Instead of keeping two
implementations around this commit allows the dma-direct
implementation to call the swiotlb bounce buffering functions and
thus share the guts of the mapping implementation.  This also
simplified the dma-mapping setup on a few architectures where we
don't have to differenciate which implementation to use.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
2018-12-13 21:06:17 +01:00
Robin Murphy 90ac706e98 dma-mapping: factor out dummy DMA ops
The dummy DMA ops are currently used by arm64 for any device which has
an invalid ACPI description and is thus barred from using DMA due to not
knowing whether is is cache-coherent or not. Factor these out into
general dma-mapping code so that they can be referenced from other
common code paths. In the process, we can prune all the optional
callbacks which just do the same thing as the default behaviour, and
fill in .map_resource for completeness.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
[hch: moved to a separate source file]
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
2018-12-13 21:06:12 +01:00
Christoph Hellwig 3731c3d477 dma-mapping: always build the direct mapping code
All architectures except for sparc64 use the dma-direct code in some
form, and even for sparc64 we had the discussion of a direct mapping
mode a while ago.  In preparation for directly calling the direct
mapping code don't bother having it optionally but always build the
code in.  This is a minor hardship for some powerpc and arm configs
that don't pull it in yet (although they should in a relase ot two),
and sparc64 which currently doesn't need it at all, but it will
reduce the ifdef mess we'd otherwise need significantly.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
2018-12-13 21:06:11 +01:00
Rob Herring acc2038738 Merge branch 'yaml-bindings-for-v4.21' into dt/next 2018-12-13 11:20:36 -06:00
Will Deacon 97bebc5fac arm64: sysreg: Use _BITUL() when defining register bits
Using shifts directly is error-prone and can cause inadvertent sign
extensions or build problems with older versions of binutils.

Consistent use of the _BITUL() macro makes these problems disappear.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:47 +00:00
Will Deacon 1e013d0612 arm64: cpufeature: Rework ptr auth hwcaps using multi_entry_cap_matches
Open-coding the pointer-auth HWCAPs is a mess and can be avoided by
reusing the multi-cap logic from the CPU errata framework.

Move the multi_entry_cap_matches code to cpufeature.h and reuse it for
the pointer auth HWCAPs.

Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:47 +00:00
Will Deacon a56005d321 arm64: cpufeature: Reduce number of pointer auth CPU caps from 6 to 4
We can easily avoid defining the two meta-capabilities for the address
and generic keys, so remove them and instead just check both of the
architected and impdef capabilities when determining the level of system
support.

Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:47 +00:00
Will Deacon 84931327a8 arm64: ptr auth: Move per-thread keys from thread_info to thread_struct
We don't need to get at the per-thread keys from assembly at all, so
they can live alongside the rest of the per-thread register state in
thread_struct instead of thread_info.

This will also allow straighforward whitelisting of the keys for
hardened usercopy should we expose them via a ptrace request later on.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:47 +00:00
Mark Rutland 04ca3204fa arm64: enable pointer authentication
Now that all the necessary bits are in place for userspace, add the
necessary Kconfig logic to allow this to be enabled.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Kristina Martsenko ba83088565 arm64: add prctl control for resetting ptrauth keys
Add an arm64-specific prctl to allow a thread to reinitialize its
pointer authentication keys to random values. This can be useful when
exec() is not used for starting new processes, to ensure that different
processes still have different keys.

Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland ccc4381082 arm64: perf: strip PAC when unwinding userspace
When the kernel is unwinding userspace callchains, we can't expect that
the userspace consumer of these callchains has the data necessary to
strip the PAC from the stored LR.

This patch has the kernel strip the PAC from user stackframes when the
in-kernel unwinder is used. This only affects the LR value, and not the
FP.

This only affects the in-kernel unwinder. When userspace performs
unwinding, it is up to userspace to strip PACs as necessary (which can
be determined from DWARF information).

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland ec6e822d1a arm64: expose user PAC bit positions via ptrace
When pointer authentication is in use, data/instruction pointers have a
number of PAC bits inserted into them. The number and position of these
bits depends on the configured TCR_ELx.TxSZ and whether tagging is
enabled. ARMv8.3 allows tagging to differ for instruction and data
pointers.

For userspace debuggers to unwind the stack and/or to follow pointer
chains, they need to be able to remove the PAC bits before attempting to
use a pointer.

This patch adds a new structure with masks describing the location of
the PAC bits in userspace instruction and data pointers (i.e. those
addressable via TTBR0), which userspace can query via PTRACE_GETREGSET.
By clearing these bits from pointers (and replacing them with the value
of bit 55), userspace can acquire the PAC-less versions.

This new regset is exposed when the kernel is built with (user) pointer
authentication support, and the address authentication feature is
enabled. Otherwise, the regset is hidden.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[will: Fix to use vabits_user instead of VA_BITS and rename macro]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland 7503197562 arm64: add basic pointer authentication support
This patch adds basic support for pointer authentication, allowing
userspace to make use of APIAKey, APIBKey, APDAKey, APDBKey, and
APGAKey. The kernel maintains key values for each process (shared by all
threads within), which are initialised to random values at exec() time.

The ID_AA64ISAR1_EL1.{APA,API,GPA,GPI} fields are exposed to userspace,
to describe that pointer authentication instructions are available and
that the kernel is managing the keys. Two new hwcaps are added for the
same reason: PACA (for address authentication) and PACG (for generic
authentication).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Tested-by: Adam Wallis <awallis@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[will: Fix sizeof() usage and unroll address key initialisation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland 6984eb47d5 arm64/cpufeature: detect pointer authentication
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.

From ARMv8.3 onwards, ID_AA64ISAR1 is no longer entirely RES0, and now
has four fields describing the presence of pointer authentication
functionality:

* APA - address authentication present, using an architected algorithm
* API - address authentication present, using an IMP DEF algorithm
* GPA - generic authentication present, using an architected algorithm
* GPI - generic authentication present, using an IMP DEF algorithm

This patch checks for both address and generic authentication,
separately. It is assumed that if all CPUs support an IMP DEF algorithm,
the same algorithm is used across all CPUs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland b3669b1e1c arm64: Don't trap host pointer auth use to EL2
To allow EL0 (and/or EL1) to use pointer authentication functionality,
we must ensure that pointer authentication instructions and accesses to
pointer authentication keys are not trapped to EL2.

This patch ensures that HCR_EL2 is configured appropriately when the
kernel is booted at EL2. For non-VHE kernels we set HCR_EL2.{API,APK},
ensuring that EL1 can access keys and permit EL0 use of instructions.
For VHE kernels host EL0 (TGE && E2H) is unaffected by these settings,
and it doesn't matter how we configure HCR_EL2.{API,APK}, so we don't
bother setting them.

This does not enable support for KVM guests, since KVM manages HCR_EL2
itself when running VMs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland a1ee8abb95 arm64/kvm: hide ptrauth from guests
In subsequent patches we're going to expose ptrauth to the host kernel
and userspace, but things are a bit trickier for guest kernels. For the
time being, let's hide ptrauth from KVM guests.

Regardless of how well-behaved the guest kernel is, guest userspace
could attempt to use ptrauth instructions, triggering a trap to EL2,
resulting in noise from kvm_handle_unknown_ec(). So let's write up a
handler for the PAC trap, which silently injects an UNDEF into the
guest, as if the feature were really missing.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:46 +00:00
Mark Rutland 4eaed6aa2c arm64/kvm: consistently handle host HCR_EL2 flags
In KVM we define the configuration of HCR_EL2 for a VHE HOST in
HCR_HOST_VHE_FLAGS, but we don't have a similar definition for the
non-VHE host flags, and open-code HCR_RW. Further, in head.S we
open-code the flags for VHE and non-VHE configurations.

In future, we're going to want to configure more flags for the host, so
lets add a HCR_HOST_NVHE_FLAGS defintion, and consistently use both
HCR_HOST_VHE_FLAGS and HCR_HOST_NVHE_FLAGS in the kvm code and head.S.

We now use mov_q to generate the HCR_EL2 value, as we use when
configuring other registers in head.S.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:45 +00:00
Mark Rutland aa6eece8ec arm64: add pointer authentication register bits
The ARMv8.3 pointer authentication extension adds:

* New fields in ID_AA64ISAR1 to report the presence of pointer
  authentication functionality.

* New control bits in SCTLR_ELx to enable this functionality.

* New system registers to hold the keys necessary for this
  functionality.

* A new ESR_ELx.EC code used when the new instructions are affected by
  configurable traps

This patch adds the relevant definitions to <asm/sysreg.h> and
<asm/esr.h> for these, to be used by subsequent patches.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:45 +00:00
Kristina Martsenko 1556065735 arm64: add comments about EC exception levels
To make it clear which exceptions can't be taken to EL1 or EL2, add
comments next to the ESR_ELx_EC_* macro definitions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 16:42:45 +00:00
Will Deacon 26a25c841d arm64: perf: Treat EXCLUDE_EL* bit definitions as unsigned
Although the upper 32 bits of the PMEVTYPER<n>_EL0 registers are RES0,
we should treat the EXCLUDE_EL* bit definitions as unsigned so that we
avoid accidentally sign-extending the privilege filtering bit (bit 31)
into the upper half of the register.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 15:34:44 +00:00
Will Deacon 2a355ec257 arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.

We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13 14:14:21 +00:00
Laurent Pinchart 6f61a2c8f1 arm64: dts: renesas: draak: Fix CVBS input
A typo in the adv7180 DT node prevents successful probing of the VIN.
Fix it.

Fixes: 6a0942c20f ("arm64: dts: renesas: draak: Describe CVBS input")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-13 13:47:30 +01:00
Ard Biesheuvel 2fe55987b2 crypto: arm64/chacha - use combined SIMD/ALU routine for more speed
To some degree, most known AArch64 micro-architectures appear to be
able to issue ALU instructions in parellel to SIMD instructions
without affecting the SIMD throughput. This means we can use the ALU
to process a fifth ChaCha block while the SIMD is processing four
blocks in parallel.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13 18:24:55 +08:00
Ard Biesheuvel f2ca1cbd0f crypto: arm64/chacha - optimize for arbitrary length inputs
Update the 4-way NEON ChaCha routine so it can handle input of any
length >64 bytes in its entirety, rather than having to call into
the 1-way routine and/or memcpy()s via temp buffers to handle the
tail of a ChaCha invocation that is not a multiple of 256 bytes.

On inputs that are a multiple of 256 bytes (and thus in tcrypt
benchmarks), performance drops by around 1% on Cortex-A57, while
performance for inputs drawn randomly from the range [64, 1024)
increases by around 30%.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13 18:24:40 +08:00
Eric Biggers 19c11c97c3 crypto: arm64/chacha - add XChaCha12 support
Now that the ARM64 NEON implementation of ChaCha20 and XChaCha20 has
been refactored to support varying the number of rounds, add support for
XChaCha12.  This is identical to XChaCha20 except for the number of
rounds, which is 12 instead of 20.  This can be used by Adiantum.

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13 18:24:37 +08:00
Eric Biggers 95a34b779e crypto: arm64/chacha20 - refactor to allow varying number of rounds
In preparation for adding XChaCha12 support, rename/refactor the ARM64
NEON implementation of ChaCha20 to support different numbers of rounds.

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13 18:24:36 +08:00
Eric Biggers cc7cf991e9 crypto: arm64/chacha20 - add XChaCha20 support
Add an XChaCha20 implementation that is hooked up to the ARM64 NEON
implementation of ChaCha20.  This can be used by Adiantum.

A NEON implementation of single-block HChaCha20 is also added so that
XChaCha20 can use it rather than the generic implementation.  This
required refactoring the ChaCha20 permutation into its own function.

Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13 18:24:36 +08:00
Eric Biggers a00fa0c887 crypto: arm64/nhpoly1305 - add NEON-accelerated NHPoly1305
Add an ARM64 NEON implementation of NHPoly1305, an ε-almost-∆-universal
hash function used in the Adiantum encryption mode.  For now, only the
NH portion is actually NEON-accelerated; the Poly1305 part is less
performance-critical so is just implemented in C.

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> # big-endian
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13 18:24:35 +08:00
Marc Gonzalez d9678adbe7 arm64: defconfig: Enable FSL_MC_BUS and FSL_MC_DPIO
Commit e8342cc795 ("enable CAAM crypto engine on QorIQ DPAA2 SoCs")
enabled CRYPTO_DEV_FSL_DPAA2_CAAM, which depends on FSL_MC_DPIO,
which is not set. Enable FSL_MC_BUS, and build FSL_MC_DPIO and
CRYPTO_DEV_FSL_DPAA2_CAAM as modules.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[olof: refreshed due to churn]
Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 18:08:50 -08:00
Marc Gonzalez 3cf9e6d009 arm64: defconfig: Replace PINCTRL_MT7622 with PINCTRL_MTK_MOORE
Commit e78d57b2f8 ("pinctrl: mediatek: add pinctrl-moore that
implements the generic pinctrl dt-bindings") made PINCTRL_MT7622
depend on PINCTRL_MTK_MOORE, so it fell off in the refresh.
Add MTK_MOORE, which automatically enables MT7622.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[olof: refresh and minor commit message reword]
Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 18:05:10 -08:00
Marc Gonzalez 1f4fa50dd4 arm64: defconfig: Regenerate for v4.20
Run the platform defconfig through kbuild, and handle the trivial case
where options merely move around.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[olof: refreshed due to some recent churn]
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 17:56:54 -08:00
Olof Johansson b125eb0bf4 arm64: dts: Amlogic updates for v4.21, round2
Highlights:
 - fix IRQ trigger type
 - AXG: enable GPIO IRQs, PHY IRQ, watchdog
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Merge tag 'amlogic-dt64-2-redo' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

arm64: dts: Amlogic updates for v4.21, round2

Highlights:
- fix IRQ trigger type
- AXG: enable GPIO IRQs, PHY IRQ, watchdog

* tag 'amlogic-dt64-2-redo' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: meson: Fix IRQ trigger type for macirq
  arm64: dts: meson-axg: Enable GPIO interrupt controller
  arm64: dts: meson-axg: s400: Enable PHY interrupt
  arm64: dts: meson: add clock controller clock inputs
  dt-bindings: clk: meson: add main controller clock input
  dt-bindings: clk: meson: add ao controller clock inputs
  arm64: dts: meson-axg: remove alternate xtal
  arm64: dts: meson-axg: Enable watchdog on Meson AXG SoCs

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 17:50:39 -08:00
Olof Johansson 8e22bce990 rockpro64 regulator fixes that cause stability issues
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Merge tag 'v4.20-rockchip-dts64fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes

rockpro64 regulator fixes that cause stability issues

* tag 'v4.20-rockchip-dts64fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: fix rk3399-rockpro64 regulator gpios

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 14:21:26 -08:00
Olof Johansson 69c5f266d8 Allwinner H3/H5 changes for 4.21
Our usual pull request with the changes shared between the H3 and H5 SoCs.
 
 The major changes for this release are:
   - Addition of the video engine for the H5
   - H3 Camera support
   - New board: Emlid Neutis N5, Mapleboard MP130
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Merge tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner H3/H5 changes for 4.21

Our usual pull request with the changes shared between the H3 and H5 SoCs.

The major changes for this release are:
  - Addition of the video engine for the H5
  - H3 Camera support
  - New board: Emlid Neutis N5, Mapleboard MP130

* tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: h5: Add Video Engine node
  ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes
  arm64: dts: allwinner: h5: Add system-control node with SRAM C1
  ARM: dts: sun8i: h3: Fix the system-control register range
  ARM: dts: sun8i: Add the H3/H5 CSI controller
  ARM: dts: sun8i-h3: Add dts for the Mapleboard MP130
  arm64: dts: allwinner: new board - Emlid Neutis N5
  dt-bindings: vendor-prefix: new vendor - Emlid
  ARM: dts: sun8i-h3: add sy8106a to orange pi plus

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 13:59:58 -08:00
Olof Johansson 50ba37008f Renesas ARM Based SoC Updates for v4.21
* pm-rmobile driver
   - Move to drivers/soc/renesas/
   - Clean up struct rmobile_pm_domain
 * Renesas SoC Kconfig Symbols
   - Move symbols for ARM and SoCs to drivers/soc/renesas/
   - Hide ARCH_RZN1 to improve consistency
 * SH-Mobile AG5 (sh73a0) SoC: Remove obsolete inclusion of <asm/smp_twd.h>
 * Restrict TWD and SCU to Renesas ARM based SoCs where they are present
 * Enable GPIOLIB on Renesas arm64 based SoCs to allow GPIO driver selection
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Merge tag 'renesas-soc-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Renesas ARM Based SoC Updates for v4.21

* pm-rmobile driver
  - Move to drivers/soc/renesas/
  - Clean up struct rmobile_pm_domain
* Renesas SoC Kconfig Symbols
  - Move symbols for ARM and SoCs to drivers/soc/renesas/
  - Hide ARCH_RZN1 to improve consistency
* SH-Mobile AG5 (sh73a0) SoC: Remove obsolete inclusion of <asm/smp_twd.h>
* Restrict TWD and SCU to Renesas ARM based SoCs where they are present
* Enable GPIOLIB on Renesas arm64 based SoCs to allow GPIO driver selection

* tag 'renesas-soc-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/
  ARM: shmobile: R-Mobile: Clean up struct rmobile_pm_domain
  ARM: shmobile: Move SoC Kconfig symbols to drivers/soc/renesas/
  arm64: renesas: Move SoC Kconfig symbols to drivers/soc/renesas/
  ARM: shmobile: Hide ARCH_RZN1 to improve consistency
  ARM: shmobile: sh73a0: Remove obsolete inclusion of <asm/smp_twd.h>
  ARM: shmobile: Restrict TWD support to SoCs that have it
  ARM: shmobile: Restrict SCU support to SoCs that have it
  arm64: renesas: Enable GPIOLIB to allow GPIO driver selection

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 13:49:58 -08:00
Olof Johansson 7d1396177c Allwinner arm64 defconfig for 4.21
A bunch of patches to improve the coverage of Allwinner drivers in the
 arm64 defconfig, mostly targeted at adding display drivers support.
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Merge tag 'sunxi-config64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/defconfig

Allwinner arm64 defconfig for 4.21

A bunch of patches to improve the coverage of Allwinner drivers in the
arm64 defconfig, mostly targeted at adding display drivers support.

* tag 'sunxi-config64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: defconfig: Enable PWM_SUN4I
  arm64: defconfig: Enable DRM_SUN8I_DW_HDMI
  arm64: defconfig: Enable DRM_SUN8I_MIXER
  arm64: defconfig: Enable MFD_AXP20X_I2C

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 13:46:39 -08:00
Olof Johansson 5cc60b0497 Support for the onboard LEDs of the 2 96boards (ficus, rock960),
hdmi output for rockpro64, vpu node on rk3399 and adding the
 always on 32kHz clock on rk3399-Gru to get a more complete clock
 tree.
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Merge tag 'v4.21-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Support for the onboard LEDs of the 2 96boards (ficus, rock960),
hdmi output for rockpro64, vpu node on rk3399 and adding the
always on 32kHz clock on rk3399-Gru to get a more complete clock
tree.

* tag 'v4.21-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add on-board LED support on rk3399-rock960
  arm64: dts: rockchip: Add on-board LED support on rk3399-ficus
  arm64: dts: rockchip: enable hdmi output on rk3399-rockpro64
  arm64: dts: rockchip: add VPU device node for RK3399
  arm64: dts: rockchip: Add 32k clk on rk3399-gru

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 13:07:51 -08:00
Olof Johansson ba97d019fc UniPhier ARM SoC DT updates for v4.21
- Add bindings for all SoCs/boards of UniPhier platform
 
 - Move binding docs to socionext directory
 
 - Add all CPUs in cooling maps
 
 - Add MIO DMAC nodes
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Merge tag 'uniphier-dt-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt

UniPhier ARM SoC DT updates for v4.21

- Add bindings for all SoCs/boards of UniPhier platform

- Move binding docs to socionext directory

- Add all CPUs in cooling maps

- Add MIO DMAC nodes

* tag 'uniphier-dt-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  ARM: dts: uniphier: add MIO DMAC nodes
  arm64: dts: uniphier: Add all CPUs in cooling maps
  ARM: dts: uniphier: Add all CPUs in cooling maps
  dt-bindings: uniphier: move cache-uniphier.txt to vendor directory
  dt-bindings: uniphier: add bindings for UniPhier SoC family

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 13:01:24 -08:00
Olof Johansson dd980900e2 Freescale arm64 device tree update for 4.21:
- Add device tree for LS1028A SoC and NXP FRWY & QDS boards support
    based on this SoC.
  - Add device tree for LX2160A SoC and NXP QDS & RDB boards support
    based on this SoC.
  - Add qdma devices for LS1043A and LS1046A SoC.
  - Disable PCIe device by default in SoC device tree and let board level
    device tree to enable as needed.
  - Drop compatible string "snps,dw-pcie" from LayerScape PCIe devices to
    avoid incorrect matching.
  - Move fsl-mc device as a child node of soc node, and add missing
    dma-ranges property for LS1088A SoC.
  - Update LayerScape SoCs' cooling maps to include all devices affected
    by individual trip points.
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Merge tag 'imx-dt64-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Freescale arm64 device tree update for 4.21:
 - Add device tree for LS1028A SoC and NXP FRWY & QDS boards support
   based on this SoC.
 - Add device tree for LX2160A SoC and NXP QDS & RDB boards support
   based on this SoC.
 - Add qdma devices for LS1043A and LS1046A SoC.
 - Disable PCIe device by default in SoC device tree and let board level
   device tree to enable as needed.
 - Drop compatible string "snps,dw-pcie" from LayerScape PCIe devices to
   avoid incorrect matching.
 - Move fsl-mc device as a child node of soc node, and add missing
   dma-ranges property for LS1088A SoC.
 - Update LayerScape SoCs' cooling maps to include all devices affected
   by individual trip points.

* tag 'imx-dt64-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls1046a: add qdma device tree nodes
  arm64: dts: ls1043a: add qdma device tree nodes
  arm64: dts: ls1088a: Add missing dma-ranges property
  arm64: dts: ls1088a: Move fsl-mc node
  arm64: dts: fsl: Add all CPUs in cooling maps
  arm64: dts: Add support for NXP LS1028A SoC
  arm64: dts: layerscape: removed compatible string "snps,dw-pcie"
  arm64: dts: fsl: Add the status property disable PCIe
  arm64: dts: ls1012a: Add FRWY-LS1012A board support
  arm64: dts: add LX2160AQDS board support
  arm64: dts: add LX2160ARDB board support
  arm64: dts: add QorIQ LX2160A SoC support

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:59:14 -08:00
Olof Johansson 457a728d80 mt8173: add node for the command queue device
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Merge tag 'v4.20-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

mt8173: add node for the command queue device

* tag 'v4.20-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt8173: Add GCE node

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:53:47 -08:00
Olof Johansson 333524bcd3 Samsung DTS ARM64 changes for v4.21
1. Update DWC3 hardware modules to Exynos5433 specific variant.
 2. Update cooling maps to include all CPU devices in multiple DTS files.
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Merge tag 'samsung-dt64-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DTS ARM64 changes for v4.21

1. Update DWC3 hardware modules to Exynos5433 specific variant.
2. Update cooling maps to include all CPU devices in multiple DTS files.

* tag 'samsung-dt64-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Add all CPUs in cooling maps
  arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:53:05 -08:00
Olof Johansson d4dcfc7c93 mvebu dt64 for 4.21 (part 1)
- complete the description of the clearfog-gt-8k board (Armada 8040
    based board)
  - declare eMMC on espressobin (Armada 3720 based board) which still
    need to be enable by the bootloader as it is not present on all the
    board.
  - add a new version of the Macchiatobin (Armada 8040 based board): the
    Single Shot (without the 10G 3310 PHYs).
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Merge tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.21 (part 1)

 - complete the description of the clearfog-gt-8k board (Armada 8040
   based board)
 - declare eMMC on espressobin (Armada 3720 based board) which still
   need to be enable by the bootloader as it is not present on all the
   board.
 - add a new version of the Macchiatobin (Armada 8040 based board): the
   Single Shot (without the 10G 3310 PHYs).

* tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB
  arm64: dts: add support for Macchiatobin Single Shot board
  arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
  arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl definition
  arm64: dts: clearfog-gt-8k: enable mini-PCIe CON2 USB
  arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
  arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:51:46 -08:00
Olof Johansson e7828317a4 Qualcomm ARM64 Updates for v4.21 Part 2
* Switch to use dwc3-qcom glue driver on MSM8996
 * Fix issue with xo clk name on MSM8998
 * Add cooling maps on MSM8916
 * Add UART nodes on SDM845
 * Add camera subsystem support on MSM8996 and MSM8916
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Merge tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt

Qualcomm ARM64 Updates for v4.21 Part 2

* Switch to use dwc3-qcom glue driver on MSM8996
* Fix issue with xo clk name on MSM8998
* Add cooling maps on MSM8916
* Add UART nodes on SDM845
* Add camera subsystem support on MSM8996 and MSM8916

* tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  arm64: dts: msm8996: Use dwc3-qcom glue driver for USB
  arm64: dts: qcom: msm8998: Fixup clock to use xo_board
  arm64: dts: qcom: sdm845: Add UART nodes
  arm64: dts: qcom: msm8996: Add CAMSS support
  arm64: dts: qcom: msm8996: Add VFE SMMU node
  arm64: dts: qcom: Add pinctrls for camera sensors
  arm64: dts: qcom: Add Camera Control Interface pinctrls
  arm64: dts: qcom: msm8916: Add CAMSS support
  arm64: dts: qcom: msm8916: Add IOMMU sub-node for VFE context bank
  arm64: dts: msm8916: Add all CPUs in cooling maps

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:50:46 -08:00
Olof Johansson ee261c7e82 Allwinner arm64 DT changes for 4.21
Our usual set of arm64 DT changes, with the biggest additions being:
   - Support for the video decoding engine in the A64
   - Support for the audio codec in the A64
   - USB Support in the H6
   - HDMI Support in the H6
   - EMAC Support in the H6
   - New board: Orange Pi Lite2
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Merge tag 'sunxi-dt64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner arm64 DT changes for 4.21

Our usual set of arm64 DT changes, with the biggest additions being:
  - Support for the video decoding engine in the A64
  - Support for the audio codec in the A64
  - USB Support in the H6
  - HDMI Support in the H6
  - EMAC Support in the H6
  - New board: Orange Pi Lite2

* tag 'sunxi-dt64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (27 commits)
  arm64: dts: allwinner: a64: Fix up RTC device node and clock references
  arm64: dts: allwinner: a64: Add Video Engine node
  arm64: dts: allwinner: a64: Add support for the SRAM C1 section
  arm64: dts: allwinner: a64: pinebook: enable power supplies
  arm64: dts: allwinner: a64: sopine-baseboard: enable power supplies
  arm64: dts: allwinner: axp803: add AC and battery power supplies
  arm64: dts: allwinner: a64: bananapi-m64: Enable audio codec
  arm64: dts: allwinner: a64: enable sound on Pinebook
  arm64: dts: allwinner: a64: enable sound on Pine64 and SoPine
  arm64: dts: allwinner: a64: add nodes necessary for analog sound support
  arm64: dts: allwinner: h6: orangepi: Add device nodes for LEDs
  arm64: dts: allwinner: h6: orangepi: Enable USB 2.0 host and OTG ports
  arm64: dts: allwinner: h6: orangepi: Add board-wide 5V regulator
  arm64: dts: allwinner: h6: fix EMAC compatible string sequence
  arm64: dts: allwinner: a64: Add device node for Mali-400 GPU
  dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali
  arm64: dts: allwinner: h6: enable USB2 on Pine H64
  arm64: dts: allwinner: h6: add USB Vbus regulator for Pine H64
  arm64: dts: allwinner: h6: add USB2-related device nodes
  arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:50:00 -08:00
Olof Johansson 2c94db389b Allwinner DT changes for 4.21
This is a quite big pull request this time, with a huge number of changes
 (and patches) due to us fixing the vast majority of the DTC warnings our DT
 had.
 
 We also have a bunch of other good, more meaningful, changes:
   - Support for the new Allwinner T3 (rebranded R40) and f1c100s (armv5)
     SoCs
   - AXP803 PMIC AC Power supply support
   - Rework of the oscillators tree
   - Two new boards: the t3-cqa3t-bv3 and Lichee Pi Nano
 
 Plus a few enhancements here and there.
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Merge tag 'sunxi-dt-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner DT changes for 4.21

This is a quite big pull request this time, with a huge number of changes
(and patches) due to us fixing the vast majority of the DTC warnings our DT
had.

We also have a bunch of other good, more meaningful, changes:
  - Support for the new Allwinner T3 (rebranded R40) and f1c100s (armv5)
    SoCs
  - AXP803 PMIC AC Power supply support
  - Rework of the oscillators tree
  - Two new boards: the t3-cqa3t-bv3 and Lichee Pi Nano

Plus a few enhancements here and there.

* tag 'sunxi-dt-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (84 commits)
  ARM: dts: sunxi: Fix PMU compatible strings
  ARM: dts: sun8i: r40: Add RTC device node
  ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references
  ARM: dts: sun8i: a23/a33: Fix up RTC device node
  ARM: dts: sun8i: r40: Add clock accuracy for external oscillators
  ARM: dts: sunxi: h3/h5: Add clock accuracy for external oscillators
  ARM: dts: sun8i: a33: Drop audio codec oversampling rate to 128 fs
  ARM: dts: sun8i: h3: Remove unnecessary reserved memory node
  ARM: dts: sun8i: a33: Remove unnecessary reserved memory node
  ARM: dts: suniv: Add device tree for Lichee Pi Nano
  ARM: dts: suniv: add initial DTSI file for F1C100s
  ARM: dts: axp81x: add AC power supply subnode
  ARM: dts: sun8i: v3s: Remove skeleton and memory to avoid warnings
  ARM: dts: sun8i: v3s: Provide default muxing for relevant controllers
  ARM: dts: sun8i: v3s: Change pinctrl nodes to avoid warning
  ARM: dts: sun8i: v3s: Change LRADC node names to avoid warnings
  ARM: dts: sun8i: h3: Remove leading zeros from unit-addresses
  ARM: dts: sun8i: BPI-M2M: Remove i2c nodes
  ARM: dts: sun8i: a23/a33: Provide default muxing for relevant controllers
  ARM: dts: sunxi: reference: Move the muxing back to the common DTSI
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12 12:48:57 -08:00
Will Deacon b47f515bdc Merge branch 'for-next/perf' into aarch64/for-next/core
Merge in arm64 perf and PMU driver updates, including support for the
system/uncore PMU in the ThunderX2 platform.
2018-12-12 19:00:25 +00:00
Ard Biesheuvel 0a1213fa74 arm64: enable per-task stack canaries
This enables the use of per-task stack canary values if GCC has
support for emitting the stack canary reference relative to the
value of sp_el0, which holds the task struct pointer in the arm64
kernel.

The $(eval) extends KBUILD_CFLAGS at the moment the make rule is
applied, which means asm-offsets.o (which we rely on for the offset
value) is built without the arguments, and everything built afterwards
has the options set.

Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-12 18:45:31 +00:00
Robin Murphy 4ab2150615 arm64: Add memory hotplug support
Wire up the basic support for hot-adding memory. Since memory hotplug
is fairly tightly coupled to sparsemem, we tweak pfn_valid() to also
cross-check the presence of a section in the manner of the generic
implementation, before falling back to memblock to check for no-map
regions within a present section as before. By having arch_add_memory(()
create the linear mapping first, this then makes everything work in the
way that __add_section() expects.

We expect hotplug to be ACPI-driven, so the swapper_pg_dir updates
should be safe from races by virtue of the global device hotplug lock.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-12 14:43:43 +00:00
Will Deacon 6e4ede698d arm64: percpu: Fix LSE implementation of value-returning pcpu atomics
Commit 959bf2fd03 ("arm64: percpu: Rewrite per-cpu ops to allow use of
LSE atomics") introduced alternative code sequences for the arm64 percpu
atomics, so that the LSE instructions can be patched in at runtime if
they are supported by the CPU.

Unfortunately, when patching in the LSE sequence for a value-returning
pcpu atomic, the argument registers are the wrong way round. The
implementation of this_cpu_add_return() therefore ends up adding
uninitialised stack to the percpu variable and returning garbage.

As it turns out, there aren't very many users of the value-returning
percpu atomics in mainline and we only spotted this due to a failure in
the kprobes selftests. In this case, when attempting to single-step over
the out-of-line instruction slot, the debug monitors would not be
enabled because calling this_cpu_inc_return() on the kernel debug
monitor refcount would fail to detect the transition from 0. We would
consequently execute past the slot and take an undefined instruction
exception from the kernel, resulting in a BUG:

 | kernel BUG at arch/arm64/kernel/traps.c:421!
 | PREEMPT SMP
 | pc : do_undefinstr+0x268/0x278
 | lr : do_undefinstr+0x124/0x278
 | Process swapper/0 (pid: 1, stack limit = 0x(____ptrval____))
 | Call trace:
 |  do_undefinstr+0x268/0x278
 |  el1_undef+0x10/0x78
 |  0xffff00000803c004
 |  init_kprobes+0x150/0x180
 |  do_one_initcall+0x74/0x178
 |  kernel_init_freeable+0x188/0x224
 |  kernel_init+0x10/0x100
 |  ret_from_fork+0x10/0x1c

Fix the argument order to get the value-returning pcpu atomics working
correctly when implemented using the LSE instructions.

Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-12 14:43:35 +00:00
Mark Rutland c3296a1391 arm64: add <asm/asm-prototypes.h>
While we can export symbols from assembly files, CONFIG_MODVERIONS requires C
declarations of anyhting that's exported.

Let's account for this as other architectures do by placing these declarations
in <asm/asm-prototypes.h>, which kbuild will automatically use to generate
modversion information for assembly files.

Since we already define most prototypes in existing headers, we simply need to
include those headers in <asm/asm-prototypes.h>, and don't need to duplicate
these.

Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-12 14:10:18 +00:00
Will Deacon 9b31cf493f arm64: mm: Introduce MAX_USER_VA_BITS definition
With the introduction of 52-bit virtual addressing for userspace, we are
now in a position where the virtual addressing capability of userspace
may exceed that of the kernel. Consequently, the VA_BITS definition
cannot be used blindly, since it reflects only the size of kernel
virtual addresses.

This patch introduces MAX_USER_VA_BITS which is either VA_BITS or 52
depending on whether 52-bit virtual addressing has been configured at
build time, removing a few places where the 52 is open-coded based on
explicit CONFIG_ guards.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-12 11:51:40 +00:00
Martin KaFai Lau 37ab566c17 bpf: arm64: Enable arm64 jit to provide bpf_line_info
This patch enables arm64's bpf_int_jit_compile() to provide
bpf_line_info by calling bpf_prog_fill_jited_linfo().

Signed-off-by: Martin KaFai Lau <kafai@fb.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2018-12-12 02:16:56 +01:00
Arnd Bergmann 4d08d20f1c arm64: fix ARM64_USER_VA_BITS_52 builds
In some randconfig builds, the new CONFIG_ARM64_USER_VA_BITS_52
triggered a build failure:

arch/arm64/mm/proc.S:287: Error: immediate out of range

As it turns out, we were incorrectly setting PGTABLE_LEVELS here,
lacking any other default value.
This fixes the calculation of CONFIG_PGTABLE_LEVELS to consider
all combinations again.

Fixes: 68d23da437 ("arm64: Kconfig: Re-jig CONFIG options for 52-bit VA")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-11 20:07:12 +00:00
Will Deacon 7faa313f05 arm64: preempt: Fix big-endian when checking preempt count in assembly
Commit 3962446922 ("arm64: preempt: Provide our own implementation of
asm/preempt.h") extended the preempt count field in struct thread_info
to 64 bits, so that it consists of a 32-bit count plus a 32-bit flag
indicating whether or not the current task needs rescheduling.

Whilst the asm-offsets definition of TSK_TI_PREEMPT was updated to point
to this new field, the assembly usage was left untouched meaning that a
32-bit load from TSK_TI_PREEMPT on a big-endian machine actually returns
the reschedule flag instead of the count.

Whilst we could fix this by pointing TSK_TI_PREEMPT at the count field,
we're actually better off reworking the two assembly users so that they
operate on the whole 64-bit value in favour of inspecting the thread
flags separately in order to determine whether a reschedule is needed.

Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reported-by: "kernelci.org bot" <bot@kernelci.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-11 20:07:03 +00:00
Manivannan Sadhasivam 953d9f3903 arm64: dts: rockchip: Add on-board LED support on rk3399-rock960
Add on-board LED support for Rock960 board based on the following
standard used by rest of the 96Boards:

green:user1  default-trigger: heartbeat
green:user2  default-trigger: mmc0/disk-activity(onboard-storage)
green:user3  default-trigger: mmc1 (SD-card)
green:user4  default-trigger: none, panic-indicator
yellow:wlan  default-trigger: phy0tx
blue:bt      default-trigger: hci0-power

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-12-11 20:09:38 +01:00
Manivannan Sadhasivam ba0abee70a arm64: dts: rockchip: Add on-board LED support on rk3399-ficus
Add on-board LED support for Ficus board based on the following
standard used by other 96Boards:

red:user1  default-trigger: heartbeat
red:user2  default-trigger: mmc0/disk-activity (onboard-storage)
red:user3  default-trigger: mmc1 (SD-card)
red:user4  default-trigger: none, panic-indicator
red:wlan   default-trigger: phy0tx
red:bt     default-trigger: hci0-power

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-12-11 20:09:15 +01:00
Olof Johansson 91eac9139e arm64: tegra: Device tree change for v4.21-rc1
These changes add a bunch of features for Tegra194 and Tegra186, such as
 wake events, on-die RTC, temperature sensors, HDA for audio over HDMI
 and fan support on Jetson Xavier to allow cooling of the device.
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Merge tag 'tegra-for-4.21-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

arm64: tegra: Device tree change for v4.21-rc1

These changes add a bunch of features for Tegra194 and Tegra186, such as
wake events, on-die RTC, temperature sensors, HDA for audio over HDMI
and fan support on Jetson Xavier to allow cooling of the device.

* tag 'tegra-for-4.21-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (29 commits)
  arm64: tegra: Set reg property for display-hub on Tegra194
  arm64: tegra: Set reg property for display-hub on Tegra186
  arm64: dts: tegra186: Enable IOMMU for SDHCI
  arm64: tegra: Enable HDA controller on Jetson TX1
  arm64: tegra: Add CEC controller on Tegra194
  arm64: tegra: Enable HDA on Jetson Xavier
  arm64: tegra: Add HDA controller on Tegra194
  arm64: tegra: Add CEC controller on Tegra186
  arm64: tegra: Enable HDA on Jetson TX2
  arm64: tegra: Add HDA controller on Tegra186
  arm64: tegra: Add temperature sensor on P2888
  arm64: tegra: Add gpio-keys on Jetson Xavier
  arm64: tegra: Add AON GPIO controller on Tegra194
  arm64: tegra: p2888: Enable on-die RTC
  arm64: tegra: Add RTC support on Tegra194
  arm64: tegra: Enable PMC wake events on Tegra194
  arm64: tegra: p3310: Enable on-die RTC
  arm64: tegra: Add RTC support on Tegra186
  arm64: tegra: Enable PMC wake events on Tegra186
  arm64: tegra: Fix power key interrupt type on Jetson TX2
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-11 08:10:09 -08:00
Olof Johansson e2bc560635 Second Round of Renesas ARM64 Based SoC DT Updates for v4.21
* R-Car D3 (r8a77995) SoC based Draak board
   - Add the backlight device for the LVDS1 output
 
 * R-Car H3 (r8a7795) ES1.0 SoC
   - Add missing power domains to IPMMU nodes
 
 * R-Car M3-N (r8a77965) SoC
   - Remove non-existent IPMMU-IR
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Merge tag 'renesas-arm64-dt2-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM64 Based SoC DT Updates for v4.21

* R-Car D3 (r8a77995) SoC based Draak board
  - Add the backlight device for the LVDS1 output

* R-Car H3 (r8a7795) ES1.0 SoC
  - Add missing power domains to IPMMU nodes

* R-Car M3-N (r8a77965) SoC
  - Remove non-existent IPMMU-IR

* tag 'renesas-arm64-dt2-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: renesas: r8a77995: draak: Add backlight
  arm64: dts: renesas: r8a7795-es1: Add missing power domains to IPMMU nodes
  arm64: dts: renesas: r8a77965: Remove non-existent IPMMU-IR

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-11 08:01:55 -08:00
Robin Murphy 3238c359ac arm64: dma-mapping: Fix FORCE_CONTIGUOUS buffer clearing
We need to invalidate the caches *before* clearing the buffer via the
non-cacheable alias, else in the worst case __dma_flush_area() may
write back dirty lines over the top of our nice new zeros.

Fixes: dd65a941f6 ("arm64: dma-mapping: clear buffers allocated with FORCE_CONTIGUOUS flag")
Cc: <stable@vger.kernel.org> # 4.18.x-
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-12-11 11:55:32 +00:00
Arnd Bergmann 732291c4fa arm64: kexec_file: include linux/vmalloc.h
This is needed for compilation in some configurations that don't
include it implicitly:

arch/arm64/kernel/machine_kexec_file.c: In function 'arch_kimage_file_post_load_cleanup':
arch/arm64/kernel/machine_kexec_file.c:37:2: error: implicit declaration of function 'vfree'; did you mean 'kvfree'? [-Werror=implicit-function-declaration]

Fixes: 52b2a8af74 ("arm64: kexec_file: load initrd and device-tree")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-11 10:37:38 +00:00
David S. Miller addb067983 Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next
Daniel Borkmann says:

====================
pull-request: bpf-next 2018-12-11

The following pull-request contains BPF updates for your *net-next* tree.

It has three minor merge conflicts, resolutions:

1) tools/testing/selftests/bpf/test_verifier.c

 Take first chunk with alignment_prevented_execution.

2) net/core/filter.c

  [...]
  case bpf_ctx_range_ptr(struct __sk_buff, flow_keys):
  case bpf_ctx_range(struct __sk_buff, wire_len):
        return false;
  [...]

3) include/uapi/linux/bpf.h

  Take the second chunk for the two cases each.

The main changes are:

1) Add support for BPF line info via BTF and extend libbpf as well
   as bpftool's program dump to annotate output with BPF C code to
   facilitate debugging and introspection, from Martin.

2) Add support for BPF_ALU | BPF_ARSH | BPF_{K,X} in interpreter
   and all JIT backends, from Jiong.

3) Improve BPF test coverage on archs with no efficient unaligned
   access by adding an "any alignment" flag to the BPF program load
   to forcefully disable verifier alignment checks, from David.

4) Add a new bpf_prog_test_run_xattr() API to libbpf which allows for
   proper use of BPF_PROG_TEST_RUN with data_out, from Lorenz.

5) Extend tc BPF programs to use a new __sk_buff field called wire_len
   for more accurate accounting of packets going to wire, from Petar.

6) Improve bpftool to allow dumping the trace pipe from it and add
   several improvements in bash completion and map/prog dump,
   from Quentin.

7) Optimize arm64 BPF JIT to always emit movn/movk/movk sequence for
   kernel addresses and add a dedicated BPF JIT backend allocator,
   from Ard.

8) Add a BPF helper function for IR remotes to report mouse movements,
   from Sean.

9) Various cleanups in BPF prog dump e.g. to make UAPI bpf_prog_info
   member naming consistent with existing conventions, from Yonghong
   and Song.

10) Misc cleanups and improvements in allowing to pass interface name
    via cmdline for xdp1 BPF example, from Matteo.

11) Fix a potential segfault in BPF sample loader's kprobes handling,
    from Daniel T.

12) Fix SPDX license in libbpf's README.rst, from Andrey.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
2018-12-10 18:00:43 -08:00
Will Deacon 4a1daf29d3 arm64: mm: EXPORT vabits_user to modules
TASK_SIZE is defined using the vabits_user variable for 64-bit tasks,
so ensure that this variable is exported to modules to avoid the
following build breakage with allmodconfig:

 | ERROR: "vabits_user" [lib/test_user_copy.ko] undefined!
 | ERROR: "vabits_user" [drivers/misc/lkdtm/lkdtm.ko] undefined!
 | ERROR: "vabits_user" [drivers/infiniband/hw/mlx5/mlx5_ib.ko] undefined!

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 19:20:23 +00:00
Will Deacon d34664f63b Merge branch 'for-next/kexec' into aarch64/for-next/core
Merge in kexec_file_load() support from Akashi Takahiro.
2018-12-10 18:57:17 +00:00
Will Deacon bc84a2d106 Merge branch 'kvm/cortex-a76-erratum-1165522' into aarch64/for-next/core
Pull in KVM workaround for A76 erratum .

Conflicts:
	arch/arm64/include/asm/cpucaps.h
2018-12-10 18:53:52 +00:00
Suzuki K Poulose f357b3a7e1 arm64: smp: Handle errors reported by the firmware
The __cpu_up() routine ignores the errors reported by the firmware
for a CPU bringup operation and looks for the error status set by the
booting CPU. If the CPU never entered the kernel, we could end up
in assuming stale error status, which otherwise would have been
set/cleared appropriately by the booting CPU.

Reported-by: Steve Capper <steve.capper@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:18 +00:00
Will Deacon 66f16a2451 arm64: smp: Rework early feature mismatched detection
Rather than add additional variables to detect specific early feature
mismatches with secondary CPUs, we can instead dedicate the upper bits
of the CPU boot status word to flag specific mismatches.

This allows us to communicate both granule and VA-size mismatches back
to the primary CPU without the need for additional book-keeping.

Tested-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:18 +00:00
Will Deacon 68d23da437 arm64: Kconfig: Re-jig CONFIG options for 52-bit VA
Enabling 52-bit VAs for userspace is pretty confusing, since it requires
you to select "48-bit" virtual addressing in the Kconfig.

Rework the logic so that 52-bit user virtual addressing is advertised in
the "Virtual address space size" choice, along with some help text to
describe its interaction with Pointer Authentication. The EXPERT-only
option to force all user mappings to the 52-bit range is then made
available immediately below the VA size selection.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:18 +00:00
Steve Capper b9567720a1 arm64: mm: Allow forcing all userspace addresses to 52-bit
On arm64 52-bit VAs are provided to userspace when a hint is supplied to
mmap. This helps maintain compatibility with software that expects at
most 48-bit VAs to be returned.

In order to help identify software that has 48-bit VA assumptions, this
patch allows one to compile a kernel where 52-bit VAs are returned by
default on HW that supports it.

This feature is intended to be for development systems only.

Signed-off-by: Steve Capper <steve.capper@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:18 +00:00
Steve Capper 67e7fdfcc6 arm64: mm: introduce 52-bit userspace support
On arm64 there is optional support for a 52-bit virtual address space.
To exploit this one has to be running with a 64KB page size and be
running on hardware that supports this.

For an arm64 kernel supporting a 48 bit VA with a 64KB page size,
some changes are needed to support a 52-bit userspace:
 * TCR_EL1.T0SZ needs to be 12 instead of 16,
 * TASK_SIZE needs to reflect the new size.

This patch implements the above when the support for 52-bit VAs is
detected at early boot time.

On arm64 userspace addresses translation is controlled by TTBR0_EL1. As
well as userspace, TTBR0_EL1 controls:
 * The identity mapping,
 * EFI runtime code.

It is possible to run a kernel with an identity mapping that has a
larger VA size than userspace (and for this case __cpu_set_tcr_t0sz()
would set TCR_EL1.T0SZ as appropriate). However, when the conditions for
52-bit userspace are met; it is possible to keep TCR_EL1.T0SZ fixed at
12. Thus in this patch, the TCR_EL1.T0SZ size changing logic is
disabled.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:17 +00:00
Steve Capper a96a33b1ca arm64: mm: Prevent mismatched 52-bit VA support
For cases where there is a mismatch in ARMv8.2-LVA support between CPUs
we have to be careful in allowing secondary CPUs to boot if 52-bit
virtual addresses have already been enabled on the boot CPU.

This patch adds code to the secondary startup path. If the boot CPU has
enabled 52-bit VAs then ID_AA64MMFR2_EL1 is checked to see if the
secondary can also enable 52-bit support. If not, the secondary is
prevented from booting and an error message is displayed indicating why.

Technically this patch could be implemented using the cpufeature code
when considering 52-bit userspace support. However, we employ low level
checks here as the cpufeature code won't be able to run if we have
mismatched 52-bit kernel va support.

Signed-off-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:17 +00:00
Steve Capper e842dfb5a2 arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:

pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)

Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)

In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.

Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)

In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.

If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)

We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
 = (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F	// "lower" cancels out
 = 0x3C0

In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).

For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:17 +00:00
Steve Capper e5d9915745 arm64: mm: Define arch_get_mmap_end, arch_get_mmap_base
Now that we have DEFAULT_MAP_WINDOW defined, we can arch_get_mmap_end
and arch_get_mmap_base helpers to allow for high addresses in mmap.

Signed-off-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:17 +00:00
Steve Capper 363524d2b1 arm64: mm: Introduce DEFAULT_MAP_WINDOW
We wish to introduce a 52-bit virtual address space for userspace but
maintain compatibility with software that assumes the maximum VA space
size is 48 bit.

In order to achieve this, on 52-bit VA systems, we make mmap behave as
if it were running on a 48-bit VA system (unless userspace explicitly
requests a VA where addr[51:48] != 0).

On a system running a 52-bit userspace we need TASK_SIZE to represent
the 52-bit limit as it is used in various places to distinguish between
kernelspace and userspace addresses.

Thus we need a new limit for mmap, stack, ELF loader and EFI (which uses
TTBR0) to represent the non-extended VA space.

This patch introduces DEFAULT_MAP_WINDOW and DEFAULT_MAP_WINDOW_64 and
switches the appropriate logic to use that instead of TASK_SIZE.

Signed-off-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 18:42:17 +00:00
Qian Cai 6e8830674e arm64: kasan: Increase stack size for KASAN_EXTRA
If the kernel is configured with KASAN_EXTRA, the stack size is
increased significantly due to setting the GCC -fstack-reuse option to
"none" [1]. As a result, it can trigger a stack overrun quite often with
32k stack size compiled using GCC 8. For example, this reproducer

  https://github.com/linux-test-project/ltp/blob/master/testcases/kernel/syscalls/madvise/madvise06.c

can trigger a "corrupted stack end detected inside scheduler" very
reliably with CONFIG_SCHED_STACK_END_CHECK enabled. There are other
reports at:

  https://lore.kernel.org/lkml/1542144497.12945.29.camel@gmx.us/
  https://lore.kernel.org/lkml/721E7B42-2D55-4866-9C1A-3E8D64F33F9C@gmx.us/

There are just too many functions that could have a large stack with
KASAN_EXTRA due to large local variables that have been called over and
over again without being able to reuse the stacks. Some noticiable ones
are,

size
7536 shrink_inactive_list
7440 shrink_page_list
6560 fscache_stats_show
3920 jbd2_journal_commit_transaction
3216 try_to_unmap_one
3072 migrate_page_move_mapping
3584 migrate_misplaced_transhuge_page
3920 ip_vs_lblcr_schedule
4304 lpfc_nvme_info_show
3888 lpfc_debugfs_nvmestat_data.constprop

There are other 49 functions over 2k in size while compiling kernel with
"-Wframe-larger-than=" on this machine. Hence, it is too much work to
change Makefiles for each object to compile without
-fsanitize-address-use-after-scope individually.

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715#c23

Signed-off-by: Qian Cai <cai@lca.pw>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 17:53:12 +00:00
Steven Rostedt (VMware) e4c07bf986 arm64: ftrace: Set FTRACE_MAY_SLEEP before ftrace_modify_all_code()
It has been reported that ftrace_replace_code() which is called by
ftrace_modify_all_code() can cause a soft lockup warning for an
allmodconfig kernel. This is because all the debug options enabled
causes the loop in ftrace_replace_code() (which loops over all the
functions being enabled where there can be 10s of thousands), is too
slow, and never schedules out.

To solve this, setting FTRACE_MAY_SLEEP to the command passed into
ftrace_replace_code() will make it call cond_resched() in the loop,
which prevents the soft lockup warning from triggering.

Link: http://lkml.kernel.org/r/20181204192903.8193-1-anders.roxell@linaro.org
Link: http://lkml.kernel.org/r/20181205183304.000714627@goodmis.org

Acked-by: Will Deacon <will.deacon@arm.com>
Reported-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2018-12-10 12:22:45 -05:00
Linus Torvalds 1dffab5e98 ARM: SoC fixes
The usual batch; most of them are DT tweaks to fix misdescribed
 hardware. Beyond that:
 
  - A bugfix for MMP2 CPU detection, it's been there quite a while but
    makes sense to fix now anyway.
  - Some power management tweaks;
    + disabling of CPU idle power state on Marvell Armada 7K/8K (Macchiatobin et al)
    + Increase of minimum voltage on BananaPi M3
    + Tweak of power ramp time for DVFS on NXP/Freescale i.MX7SX
  - A couple of MAINTAINER updates; MMP has a new volunteer to look after
    it, and Mediatek adds a few keywords, IRC channel and wiki URL.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "The usual batch; most of them are DT tweaks to fix misdescribed
  hardware. Beyond that:

   - A bugfix for MMP2 CPU detection, it's been there quite a while but
     makes sense to fix now anyway.

   - Some power management tweaks:
      + disabling of CPU idle power state on Marvell Armada 7K/8K
        (Macchiatobin et al)
      + Increase of minimum voltage on BananaPi M3
      + Tweak of power ramp time for DVFS on NXP/Freescale i.MX7SX

   - A couple of MAINTAINER updates:
      + MMP has a new volunteer to look after it
      + Mediatek adds a few keywords, IRC channel and wiki URL"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: imx7d-nitrogen7: Fix the description of the Wifi clock
  ARM: imx: update the cpu power up timing setting on i.mx6sx
  Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K"
  ARM: dts: imx7d-pico: Describe the Wifi clock
  ARM: dts: realview: Fix some more duplicate regulator nodes
  MAINTAINERS: update entry for MMP platform
  ARM: mmp/mmp2: fix cpu_is_mmp2() on mmp2-dt
  MAINTAINERS: mediatek: Update SoC entry
  ARM: dts: bcm2837: Fix polarity of wifi reset GPIOs
  arm64: dts: mt7622: Drop the general purpose timer node
  arm64: dts: mt7622: fix no more console output on BPI-R64 board
  arm64: dts: mt7622: fix no more console output on rfb1
  ARM: dts: sun8i: a83t: bananapi-m3: increase vcc-pd voltage to 3.3V
2018-12-10 09:06:22 -08:00
Viresh Kumar 072ae88ad2 arm64: dts: uniphier: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-11 01:31:17 +09:00
Will Deacon 33309ecda0 arm64: Fix minor issues with the dcache_by_line_op macro
The dcache_by_line_op macro suffers from a couple of small problems:

First, the GAS directives that are currently being used rely on
assembler behavior that is not documented, and probably not guaranteed
to produce the correct behavior going forward. As a result, we end up
with some undefined symbols in cache.o:

$ nm arch/arm64/mm/cache.o
         ...
         U civac
         ...
         U cvac
         U cvap
         U cvau

This is due to the fact that the comparisons used to select the
operation type in the dcache_by_line_op macro are comparing symbols
not strings, and even though it seems that GAS is doing the right
thing here (undefined symbols by the same name are equal to each
other), it seems unwise to rely on this.

Second, when patching in a DC CVAP instruction on CPUs that support it,
the fallback path consists of a DC CVAU instruction which may be
affected by CPU errata that require ARM64_WORKAROUND_CLEAN_CACHE.

Solve these issues by unrolling the various maintenance routines and
using the conditional directives that are documented as operating on
strings. To avoid the complexity of nested alternatives, we move the
DC CVAP patching to __clean_dcache_area_pop, falling back to a branch
to __clean_dcache_area_poc if DCPOP is not supported by the CPU.

Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 15:03:51 +00:00
Marc Zyngier a457b0f7f5 arm64: Add configuration/documentation for Cortex-A76 erratum 1165522
Now that the infrastructure to handle erratum 1165522 is in place,
let's make it a selectable option and add the required documentation.

Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 12:21:06 +00:00
Marc Zyngier eb036ad2dd arm64: KVM: Handle ARM erratum 1165522 in TLB invalidation
In order to avoid TLB corruption whilst invalidating TLBs on CPUs
affected by erratum 1165522, we need to prevent S1 page tables
from being usable.

For this, we set the EL1 S1 MMU on, and also disable the page table
walker (by setting the TCR_EL1.EPD* bits to 1).

This ensures that once we switch to the EL1/EL0 translation regime,
speculated AT instructions won't be able to parse the page tables.

Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 12:20:42 +00:00
Marc Zyngier 1e4448c5dd arm64: KVM: Add synchronization on translation regime change for erratum 1165522
In order to ensure that slipping HCR_EL2.TGE is done at the right
time when switching translation regime, let insert the required ISBs
that will be patched in when erratum 1165522 is detected.

Take this opportunity to add the missing include of asm/alternative.h
which was getting there by pure luck.

Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:59:07 +00:00
Marc Zyngier 8b2cca9ade arm64: KVM: Force VHE for systems affected by erratum 1165522
In order to easily mitigate ARM erratum 1165522, we need to force
affected CPUs to run in VHE mode if using KVM.

Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:59:07 +00:00
Marc Zyngier 793d5d9213 arm64: Add TCR_EPD{0,1} definitions
We are soon going to play with TCR_EL1.EPD{0,1}, so let's add the
relevant definitions.

Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:59:06 +00:00
Marc Zyngier bfae1b98ef arm64: KVM: Install stage-2 translation before enabling traps
It is a bit odd that we only install stage-2 translation after having
cleared HCR_EL2.TGE, which means that there is a window during which
AT requests could fail as stage-2 is not configured yet.

Let's move stage-2 configuration before we clear TGE, making the
guest entry sequence clearer: we first configure all the guest stuff,
then only switch to the guest translation regime.

While we're at it, do the same thing for !VHE. It doesn't hurt,
and keeps things symmetric.

Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:58:48 +00:00
Marc Zyngier 33e5f4e509 KVM: arm64: Rework detection of SVE, !VHE systems
An SVE system is so far the only case where we mandate VHE. As we're
starting to grow this requirements, let's slightly rework the way we
deal with that situation, allowing for easy extension of this check.

Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:57:52 +00:00
Marc Zyngier c987876a80 arm64: KVM: Make VHE Stage-2 TLB invalidation operations non-interruptible
Contrary to the non-VHE version of the TLB invalidation helpers, the VHE
code  has interrupts enabled, meaning that we can take an interrupt in
the middle of such a sequence, and start running something else with
HCR_EL2.TGE cleared.

That's really not a good idea.

Take the heavy-handed option and disable interrupts in
__tlb_switch_to_guest_vhe, restoring them in __tlb_switch_to_host_vhe.
The latter also gain an ISB in order to make sure that TGE really has
taken effect.

Cc: stable@vger.kernel.org
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:54:37 +00:00
Mark Rutland 2a9cee5b7a arm64: remove arm64ksyms.c
Now that arm64ksyms.c has been reduced to a stub, let's remove it
entirely. New exports should be associated with their function
definition.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:12 +00:00
Mark Rutland dbd3196299 arm64: frace: use asm EXPORT_SYMBOL()
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.

As a step towards removing arm64ksyms.c, let's move the ftrace exports
to the assembly files the functions are defined in.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:12 +00:00
Mark Rutland ac0e8c72b0 arm64: string: use asm EXPORT_SYMBOL()
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.

As a step towards removing arm64ksyms.c, let's move the string routine
exports to the assembly files the functions are defined in. Routines
which should only be exported for !KASAN builds are exported using the
EXPORT_SYMBOL_NOKASAN() helper.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:12 +00:00
Mark Rutland 56c08ec516 arm64: uaccess: use asm EXPORT_SYMBOL()
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.

As a step towards removing arm64ksyms.c, let's move the uaccess exports
to the assembly files the functions are defined in.  As we have to
include <asm/assembler.h>, the existing includes are fixed to follow the
usual ordering conventions.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Mark Rutland 50fdecb292 arm64: page: use asm EXPORT_SYMBOL()
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.

As a step towards removing arm64ksyms.c, let's move the copy_page and
clear_page exports to the assembly files the functions are defined in.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Mark Rutland 23fe04c0c5 arm64: smccc: use asm EXPORT_SYMBOL()
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.

As a step towards removing arm64ksyms.c, let's move the SMCCC exports to
the assembly file the functions are defined in.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Mark Rutland abb77f3d96 arm64: tishift: use asm EXPORT_SYMBOL()
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.

As a step towards removing arm64ksyms.c, let's move the tishift exports
to the assembly file the functions are defined in.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Mark Rutland 386b3c7bda arm64: add EXPORT_SYMBOL_NOKASAN()
So that we can export symbols directly from assembly files, let's make
use of the generic <asm/export.h>. We have a few symbols that we'll want
to conditionally export for !KASAN kernel builds, so we add a helper for
that in <asm/assembler.h>.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Mark Rutland 03ef055fd3 arm64: move memstart_addr export inline
Since we define memstart_addr in a C file, we can have the export
immediately after the definition of the symbol, as we do elsewhere.

As a step towards removing arm64ksyms.c, move the export of
memstart_addr to init.c, where the symbol is defined.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Mark Rutland 2d7c89b02c arm64: remove bitop exports
Now that the arm64 bitops are inlines built atop of the regular atomics,
we don't need to export anything.

Remove the redundant exports.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-10 11:50:11 +00:00
Greg Kroah-Hartman c4aa8b2a8b Merge 4.20-rc6 into char-misc-next
This should resolve the hv driver merge conflict.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-12-10 09:22:34 +01:00
Olof Johansson 0603a9a846 mvebu fixes for 4.20
Adding CPU Idle state in the device tree for Armada 8040 seems to
 breaks boot on some board, so let's revert it waiting for a better
 solution.
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Merge tag 'mvebu-fixes-4.20-1' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for 4.20

Adding CPU Idle state in the device tree for Armada 8040 seems to
breaks boot on some board, so let's revert it waiting for a better
solution.

* tag 'mvebu-fixes-4.20-1' of git://git.infradead.org/linux-mvebu:
  Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K"

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-09 10:28:02 -08:00
Steven Rostedt (VMware) 421d1069cd arm64: function_graph: Remove use of FTRACE_NOTRACE_DEPTH
Functions in the set_graph_notrace no longer subtract FTRACE_NOTRACE_DEPTH
from curr_ret_stack, as that is now implemented via the trace_recursion
flags. Access to curr_ret_stack no longer needs to worry about checking for
this. curr_ret_stack is still initialized to -1, when there's not a shadow
stack allocated.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Joel Fernandes (Google) <joel@joelfernandes.org>
Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2018-12-08 20:53:38 -05:00
Linus Torvalds 570c9139c3 A few clk driver fixes this time:
- Introduce protected-clock DT binding to fix breakage on qcom sdm845-mtp
    boards where the qspi clks introduced this merge window cause the
    firmware on those boards to take down the system if we try to read
    the clk registers
 
  - Fix a couple off-by-one errors found by Dan Carpenter
 
  - Handle failure in zynq fixed factor clk driver to avoid using
    uninitialized data
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A few clk driver fixes this time:

   - Introduce protected-clock DT binding to fix breakage on qcom
     sdm845-mtp boards where the qspi clks introduced this merge window
     cause the firmware on those boards to take down the system if we
     try to read the clk registers

   - Fix a couple off-by-one errors found by Dan Carpenter

   - Handle failure in zynq fixed factor clk driver to avoid using
     uninitialized data"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: zynqmp: Off by one in zynqmp_is_valid_clock()
  clk: mmp: Off by one in mmp_clk_add()
  clk: mvebu: Off by one bugs in cp110_of_clk_get()
  arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks
  clk: qcom: Support 'protected-clocks' property
  dt-bindings: clk: Introduce 'protected-clocks' property
  clk: zynqmp: handle fixed factor param query error
2018-12-08 11:33:26 -08:00
Baruch Siach dfc1259a3f arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB
Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K
board.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-08 09:26:51 +01:00
Russell King b1f0bbe270 arm64: dts: add support for Macchiatobin Single Shot board
Add DT support for the Macchiatobin Single Shot board from SolidRun,
which is similar to the Double Shot board, but does not have the
10G 3310 PHYs - the two ethernet ports are instead connected directly
to the SFP+ cages.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-08 09:26:51 +01:00
Ding Tao 43ebc7c1b3 arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
The ESPRESSObin board has a emmc interface available on U11: declare it
and let the bootloader enable it if the emmc is present.

[gregory.clement@bootlin.com: disable the emmc by default]
Signed-off-by: Ding Tao <miyatsu@qq.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-08 09:25:10 +01:00
Peng Ma 58f5fa6837 arm64: dts: ls1046a: add qdma device tree nodes
add the qDMA device tree nodes for LS1046A devices.

Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:39 +08:00
Peng Ma 29813f669d arm64: dts: ls1043a: add qdma device tree nodes
add the qDMA device tree nodes for LS1043A devices.

Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:39 +08:00
Ioana Ciocoi Radulescu d9a71ef086 arm64: dts: ls1088a: Add missing dma-ranges property
LS1088A has a 48-bit address size so make sure that the
dma-ranges property reflects this.

Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:38 +08:00
Ioana Ciocoi Radulescu a2468676cc arm64: dts: ls1088a: Move fsl-mc node
The fsl-mc node should sit under the soc node, so move it to
its proper location.

Fixes: ac7c9ff741 ("arm64: dts: ls1088a: add fsl-mc hardware resource manager node")
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:38 +08:00
Viresh Kumar c9a1f24304 arm64: dts: fsl: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:38 +08:00
Bhaskar Upadhaya 8897f3255c arm64: dts: Add support for NXP LS1028A SoC
LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache

Features summary
 Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
  - Arranged as single clusters of two cores sharing a 1 MB L2 cache
  - Speed Up to 1.3 GHz
  - Support for cluster power-gating.
 Cache coherent interconnect (CCI-400)
  - Hardware-managed data coherency
  - Up to 400 MHz
 32-bit DDR4 SDRAM memory controller with ECC
 Two PCIe 3.0 controllers
 One serial ATA (SATA 3.0) controller
 Two high-speed USB 3.0 controllers with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1028A
  SoC family:

         - fsl-ls1028a.dtsi:
                 DTS-Include file for NXP LS1028A SoC.

         - fsl-ls1028a-qds.dts:
                 DTS file for NXP LS1028A QDS board.

         - fsl-ls1028a-rdb.dts:
                 DTS file for NXP LS1028A RDB board

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:38 +08:00
Hou Zhiqiang 1fa35bc09d arm64: dts: layerscape: removed compatible string "snps,dw-pcie"
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:38 +08:00
Bao Xiaowei aa2aa88847 arm64: dts: fsl: Add the status property disable PCIe
Add the status property disable the PCIe, the property will be enable
by bootloader.

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:37 +08:00
Pramod Kumar 26a06c6e29 arm64: dts: ls1012a: Add FRWY-LS1012A board support
LS1012A-FRWY is an ls1012a based SoC board.
Key features of this board are  Micro SD, USB 3.0,
upto 1GB DDR, UART

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:37 +08:00
Carlo Caione 8b3e6f8999 arm64: dts: meson: Fix IRQ trigger type for macirq
A long running stress test on a custom board shipping an AXG SoCs and a
Realtek RTL8211F PHY revealed that after a few hours the connection
speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time
the 'macirq' (eth0) IRQ would stop being triggered at all and as
consequence the GMAC IRQs never ACKed.

After a painful investigation the problem seemed to be due to a wrong
defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of
EDGE_RISING.

The change in the macirq IRQ type also solved another long standing
issue affecting this SoC/PHY where EEE was causing the network
connection to die after stressing it with iperf3 (even though much
sooner). It's now possible to remove the 'eee-broken-1000t' quirk as
well.

Fixes: feb3cbea09 ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage")
Fixes: 6d28d57751 ("ARM64: dts: meson-axg: fix ethernet stability issue")
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-07 13:48:58 -08:00
Carlo Caione cbddb02e37 arm64: dts: meson-axg: Enable GPIO interrupt controller
Enable the GPIO interrupt controller for the AXG SoCs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-07 13:47:59 -08:00
Carlo Caione de7c2fa5fc arm64: dts: meson-axg: s400: Enable PHY interrupt
Now that the GPIO controller has been enabled also on AXG we can hook up
the GPIO interrupt for the PHY.

Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-07 13:46:20 -08:00
Manu Gautam 1504b91c81 arm64: dts: msm8996: Use dwc3-qcom glue driver for USB
Move from dwc3-of-simple to dwc3-qcom glue driver to
support peripheral mode which requires qscratch wrapper
programming on VBUS event.

Fixes: a4333c3a6b ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Tested-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-07 14:10:56 -06:00
Andy Gross 818046ebe2 arm64: dts: qcom: msm8998: Fixup clock to use xo_board
This patch sets the msm8998 xo clock name back to xo_board.  Recent
clock tree changes fixed the clock tree and the change to the xo name
is causing issues where msm8998 boards do not boot properly.  Let's
change it back and leave the xo label on it.

Fixes: 634da3307b (arm64: dts: qcom: msm8998: correct xo clock name)
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
2018-12-07 14:10:48 -06:00
Will Deacon 4230509978 arm64: cmpxchg: Use "K" instead of "L" for ll/sc immediate constraint
The "L" AArch64 machine constraint, which we use for the "old" value in
an LL/SC cmpxchg(), generates an immediate that is suitable for a 64-bit
logical instruction. However, for cmpxchg() operations on types smaller
than 64 bits, this constraint can result in an invalid instruction which
is correctly rejected by GAS, such as EOR W1, W1, #0xffffffff.

Whilst we could special-case the constraint based on the cmpxchg size,
it's far easier to change the constraint to "K" and put up with using
a register for large 64-bit immediates. For out-of-line LL/SC atomics,
this is all moot anyway.

Reported-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-07 17:28:13 +00:00
Will Deacon 959bf2fd03 arm64: percpu: Rewrite per-cpu ops to allow use of LSE atomics
Our percpu code is a bit of an inconsistent mess:

  * It rolls its own xchg(), but reuses cmpxchg_local()
  * It uses various different flavours of preempt_{enable,disable}()
  * It returns values even for the non-returning RmW operations
  * It makes no use of LSE atomics outside of the cmpxchg() ops
  * There are individual macros for different sizes of access, but these
    are all funneled through a switch statement rather than dispatched
    directly to the relevant case

This patch rewrites the per-cpu operations to address these shortcomings.
Whilst the new code is a lot cleaner, the big advantage is that we can
use the non-returning ST- atomic instructions when we have LSE.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-07 17:28:06 +00:00
Will Deacon b4f9209bfc arm64: Avoid masking "old" for LSE cmpxchg() implementation
The CAS instructions implicitly access only the relevant bits of the "old"
argument, so there is no need for explicit masking via type-casting as
there is in the LL/SC implementation.

Move the casting into the LL/SC code and remove it altogether for the LSE
implementation.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-07 17:28:01 +00:00
Will Deacon 5ef3fe4cec arm64: Avoid redundant type conversions in xchg() and cmpxchg()
Our atomic instructions (either LSE atomics of LDXR/STXR sequences)
natively support byte, half-word, word and double-word memory accesses
so there is no need to mask the data register prior to being stored.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-07 17:27:55 +00:00
Will Deacon b4aecf7808 arm64: hibernate: Avoid sending cross-calling with interrupts disabled
Since commit 3b8c9f1cdf ("arm64: IPI each CPU after invalidating the
I-cache for kernel mappings"), a call to flush_icache_range() will use
an IPI to cross-call other online CPUs so that any stale instructions
are flushed from their pipelines. This triggers a WARN during the
hibernation resume path, where flush_icache_range() is called with
interrupts disabled and is therefore prone to deadlock:

  | Disabling non-boot CPUs ...
  | CPU1: shutdown
  | psci: CPU1 killed.
  | CPU2: shutdown
  | psci: CPU2 killed.
  | CPU3: shutdown
  | psci: CPU3 killed.
  | WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
  | Modules linked in:
  | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 

Since all secondary CPUs have been taken offline prior to invalidating
the I-cache, there's actually no need for an IPI and we can simply call
__flush_icache_range() instead.

Cc: <stable@vger.kernel.org>
Fixes: 3b8c9f1cdf ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings")
Reported-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Tested-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Tested-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-12-07 15:52:39 +00:00
James Morse 394135c1ff arm64: kexec_file: forbid kdump via kexec_file_load()
Now that kexec_walk_memblock() can do the crash-kernel placement itself
architectures that don't support kdump via kexe_file_load() need to
explicitly forbid it.

We don't support this on arm64 until the kernel can add the elfcorehdr
and usable-memory-range fields to the DT. Without these the crash-kernel
overwrites the previous kernel's memory during startup.

Add a check to refuse crash image loading.

Reviewed-by: Bhupesh Sharma <bhsharma@redhat.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-07 15:28:21 +00:00
Will Deacon 3962446922 arm64: preempt: Provide our own implementation of asm/preempt.h
The asm-generic/preempt.h implementation doesn't make use of the
PREEMPT_NEED_RESCHED flag, since this can interact badly with load/store
architectures which rely on the preempt_count word being unchanged across
an interrupt.

However, since we're a 64-bit architecture and the preempt count is
only 32 bits wide, we can simply pack it next to the resched flag and
load the whole thing in one go, so that a dec-and-test operation doesn't
need to load twice.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-07 12:35:53 +00:00
Thierry Reding 611a1c69f8 arm64: tegra: Set reg property for display-hub on Tegra194
Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-07 12:57:26 +01:00
Thierry Reding ffa1ad89dd arm64: tegra: Set reg property for display-hub on Tegra186
Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-07 12:57:14 +01:00
Chen-Yu Tsai 44ff3cafcd arm64: dts: allwinner: a64: Fix up RTC device node and clock references
The RTC module on the A64 was claimed to be the same as on the A31, when
in fact it is not. It is actually compatible to the H3's RTC. The A64's
RTC has some extra crypto-related registers which the H3's does not, but
the exact function of these is not clear.

This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-12-07 10:23:39 +08:00
Chen-Yu Tsai 507c6e89d6 ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references
The RTC module on the H3 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The H5's RTC has some extra crypto-related registers compared to
the H3. Their exact functions are not clear. Also the RTC-VIO regulator
has different settings.

This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-12-07 10:23:07 +08:00
Krishna Reddy 8589a649d5 arm64: dts: tegra186: Enable IOMMU for SDHCI
Enable IOMMU for all SDHCI controllers in Tegra186.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:08:35 +01:00
Thierry Reding caa7a8e3c3 arm64: tegra: Enable HDA controller on Jetson TX1
The HDA controller can be used for audio playback over HDMI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:06:09 +01:00
Thierry Reding badb80bed0 arm64: tegra: Add CEC controller on Tegra194
The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:05:59 +01:00
Thierry Reding 01e13ae3b5 arm64: tegra: Enable HDA on Jetson Xavier
Enable the HDA controller on Jetson Xavier so that it can be used for
audio playback over HDMI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:05:28 +01:00
Sameer Pujar 4878cc0c9f arm64: tegra: Add HDA controller on Tegra194
The HDA controller found on Tegra194 can be used for audio playback over
HDMI.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:04:26 +01:00
Thierry Reding 97cf683c12 arm64: tegra: Add CEC controller on Tegra186
The CEC controller found on Tegra186 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:02:20 +01:00
Thierry Reding 7c3adf1243 arm64: tegra: Enable HDA on Jetson TX2
Enable the HDA controller on Jetson TX2 so that it can be used for audio
playback over HDMI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06 19:02:10 +01:00