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Linus Torvalds dddd564dbb This time we've got one core change to introduce a bulk clk_get API,
some new clk drivers and updates for old ones. The diff is pretty
 spread out across a handful of different SoC clk drivers for Broadcom, TI,
 Qualcomm, Renesas, Rockchip, Samsung, and Allwinner, mostly due to the
 introduction of new drivers.
 
 Core:
  - New clk bulk get APIs
  - Clk divider APIs gained the ability to consider a different parent than
    the current one
 
 New Drivers:
  - Renesas r8a779{0,1,2,4} CPG/MSSR
  - TI Keystone SCI firmware controlled clks and OMAP4 clkctrl
  - Qualcomm IPQ8074 SoCs
  - Cortina Systems Gemini (SL3516/CS3516)
  - Rockchip rk3128 SoCs
  - Allwinner A83T clk control units
  - Broadcom Stingray SoCs
  - CPU clks for Mediatek MT8173/MT2701/MT7623 SoCs
 
 Removed Drivers:
  - Old non-DT version of the Realview clk driver
 
 Updates:
  - Renesas Kconfig/Makefile cleanups
  - Amlogic CEC EE clk support
  - Improved Armada 7K/8K cp110 clk support
  - Rockchip clk id exposing, critical clk markings
  - Samsung converted to clk_hw registration APIs
  - Fixes for Samsung exynos5420 audio clks
  - USB2 clks for Hisilicon hi3798cv200 SoC and video/camera clks for hi3660
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This time we've got one core change to introduce a bulk clk_get API,
  some new clk drivers and updates for old ones. The diff is pretty
  spread out across a handful of different SoC clk drivers for Broadcom,
  TI, Qualcomm, Renesas, Rockchip, Samsung, and Allwinner, mostly due to
  the introduction of new drivers.

  Core:
   - New clk bulk get APIs
   - Clk divider APIs gained the ability to consider a different parent
     than the current one

  New Drivers:
   - Renesas r8a779{0,1,2,4} CPG/MSSR
   - TI Keystone SCI firmware controlled clks and OMAP4 clkctrl
   - Qualcomm IPQ8074 SoCs
   - Cortina Systems Gemini (SL3516/CS3516)
   - Rockchip rk3128 SoCs
   - Allwinner A83T clk control units
   - Broadcom Stingray SoCs
   - CPU clks for Mediatek MT8173/MT2701/MT7623 SoCs

  Removed Drivers:
   - Old non-DT version of the Realview clk driver

  Updates:
   - Renesas Kconfig/Makefile cleanups
   - Amlogic CEC EE clk support
   - Improved Armada 7K/8K cp110 clk support
   - Rockchip clk id exposing, critical clk markings
   - Samsung converted to clk_hw registration APIs
   - Fixes for Samsung exynos5420 audio clks
   - USB2 clks for Hisilicon hi3798cv200 SoC and video/camera clks for
     hi3660"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (147 commits)
  clk: gemini: Read status before using the value
  clk: scpi: error when clock fails to register
  clk: at91: Add sama5d2 suspend/resume
  gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
  clk: keystone: TI_SCI_PROTOCOL is needed for clk driver
  clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL
  clk: uniphier: provide NAND controller clock rate
  clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
  clk: Add Gemini SoC clock controller
  clk: iproc: Remove __init marking on iproc_pll_clk_setup()
  clk: bcm: Add clocks for Stingray SOC
  dt-bindings: clk: Extend binding doc for Stingray SOC
  clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
  clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
  clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work
  clk: renesas: cpg-mssr: Use of_device_get_match_data() helper
  clk: hi6220: add acpu clock
  clk: zx296718: export I2S mux clocks
  clk: imx7d: create clocks behind rawnand clock gate
  clk: hi3660: Set PPLL2 to 2880M
  ...
2017-07-07 12:26:13 -07:00
Linus Walleij d8e349af86 reset: add DT bindings header for Gemini reset controller
This adds the DT binding macros used by the reset controller.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 17:24:58 -07:00
Chen-Yu Tsai 05359be117 clk: sunxi-ng: Add driver for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.

Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.

Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.

This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:16 +02:00
Icenowy Zheng ed74f8a8a6 dt-bindings: add binding for the Allwinner DE2 CCU
Allwinner "Display Engine 2.0" contains some clock controls in it.

In order to add them as clock drivers, we need a device tree binding.
Add the binding here.

Also add the device tree binding headers.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:12 +02:00
Richard Gong cae285ea12 dt-bindings: reset: Add reset manager offsets for Stratix10
There are several changes in reset manager offsets from Arria10 to
Stratix10. This patch is based on one from Arria10 and adds offset
updates for Stratix10

Signed-off-by: Richard Gong <richard.gong@intel.com>
2017-06-01 19:16:06 +02:00
Linus Walleij 128987916f reset: add DT bindings header for Gemini reset controller
This adds the DT binding macros used by the reset controller.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-24 10:46:12 +02:00
Linus Torvalds b5a53b61a2 Sort of on the quieter side this time, which is probably due more
to me not catching up as quickly on patch review than anything else.
 Overall it seems normal though, a few small changes to the core, mostly
 small non-critical fixes here and there as well as driver updates for new
 and existing hardware support. The biggest things are the TI clk driver
 rework to lay the groundwork for clkctrl support in the next merge window
 and the AmLogic audio/graphics clk support.
 
 Core:
  * clk_possible_parents debugfs file so we know which parents a clk
    could possibly have
  * Fix to make clk rate change notifiers stop on the first failure instead
    of continuing
 
 New Drivers:
  * Mediatek MT6797 SoCs
  * hi655x PMIC clks
  * AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
  * Allwinner H5 SoCs and PRCM hardware
 
 Updates:
  * Nvidia Tegra T210 cleanups and non-critical fixes
  * TI OMAP cleanups in preparation for clkctrl support
  * Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
  * ZTE zx296718 SoC VGA clks
  * Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
  * Support for IDT VersaClock 5P49V5935
  * Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Sort of on the quieter side this time, which is probably due more to
  me not catching up as quickly on patch review than anything else.
  Overall it seems normal though, a few small changes to the core,
  mostly small non-critical fixes here and there as well as driver
  updates for new and existing hardware support.

  The biggest things are the TI clk driver rework to lay the groundwork
  for clkctrl support in the next merge window and the AmLogic
  audio/graphics clk support.

  Core:
   - clk_possible_parents debugfs file so we know which parents a clk
     could possibly have
   - Fix to make clk rate change notifiers stop on the first failure
     instead of continuing

  New Drivers:
   - Mediatek MT6797 SoCs
   - hi655x PMIC clks
   - AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
   - Allwinner H5 SoCs and PRCM hardware

  Updates:
   - Nvidia Tegra T210 cleanups and non-critical fixes
   - TI OMAP cleanups in preparation for clkctrl support
   - trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
   - ZTE zx296718 SoC VGA clks
   - Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
   - IDT VersaClock 5P49V5935 support
   - Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
     support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
  clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
  clk: ti: divider: try to fix ti_clk_register_divider
  clk: mvebu: Use kcalloc() in two functions
  clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
  clk: nomadik: Delete error messages for a failed memory allocation in two functions
  clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
  clk: Improve a size determination in two functions
  clk: Replace four seq_printf() calls by seq_putc()
  clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
  clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
  clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
  reset: mediatek: Add MT2701 ethsys reset controller include file
  clk: mediatek: add mt2701 ethernet reset
  clk: hi6220: Add the hi655x's pmic clock
  clk: ti: fix building without legacy omap3
  clk: ti: fix linker error with !SOC_OMAP4
  clk: hi3620: Fix a typo in one variable name
  clk: hi3620: Delete error messages for a failed memory allocation in two functions
  clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
  clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
  ...
2017-05-10 13:38:18 -07:00
John Crispin 7c2adaf110 reset: mediatek: Add MT2701 ethsys reset controller include file
Add the missing reset bits of the ethsys core to the mt2701-reset include
file, so that we can reference them from within a devicetree file.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:20:34 -07:00
Stephen Boyd 8062b4aafc Allwinner clock patches for 4.12
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
 well, plus the usual chunk of fixes and minor enhancements.
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Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches for 4.12 from Maxime Ripard:

Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.

* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Display index when clock registration fails
  clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
  clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
  clk: sunxi-ng: mult: Support PLL lock detection
  clk: sunxi-ng: add support for PRCM CCUs
  dt-bindings: update device tree binding for Allwinner PRCM CCUs
  clk: sunxi-ng: sun5i: Fix mux width for csi clock
  clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
  clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
  clk: sunxi-ng: gate: Support common pre-dividers
2017-04-19 09:02:00 -07:00
Icenowy Zheng cdb8b80b60 clk: sunxi-ng: add support for PRCM CCUs
SoCs after A31 has a clock controller module in the PRCM part.

Support the clock controller module on H3/5 and A64 now.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04 17:43:52 +02:00
Peter De Schrijver 68d724cedc clk: tegra: Add Tegra210 special resets
Tegra210 has 2 special resets which don't follow the normal pattern:
DVCO and ADSP. Add them in this patch.

Changelog:

v2: add DT bindings file

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20 14:20:42 +01:00
Thor Thayer 843fc75af8 dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets
The Arria10 System Resource Chip reset controller handles the
Arria10 peripheral PHYs. This patch adds the offsets for
these PHYs.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15 12:19:10 +01:00
Andrey Smirnov abf97755ae reset: Add i.MX7 SRC reset driver
Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.

Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15 12:18:49 +01:00
Icenowy Zheng 9be1c8afb4 clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.

Add its support in our existing H3 CCU driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 10:25:56 +01:00
Chen-Yu Tsai 783ab76ae5 clk: sunxi-ng: Add A80 Display Engine CCU
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.

One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.

Add support for the display engine clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:38:30 +01:00
Chen-Yu Tsai 439b65c4bb clk: sunxi-ng: Add A80 USB CCU
Add support for the USB clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:37:51 +01:00
Chen-Yu Tsai b8eb71dcdd clk: sunxi-ng: Add A80 CCU
Add support for the main clock unit found in the A80. Some clocks were
not documented in the released user manual, but were found in the
official kernel from Allwinner. These include controls for the I2S,
SPDIF, SATA, and eDP blocks.

Note that on the A80, some subsystems have separate clock controllers
downstream of the main clock unit. These include the MMC, USB, and
display engine subsystems.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:37:30 +01:00
Maxime Ripard 5e73761786 clk: sunxi-ng: Add sun5i CCU driver
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same
silicon, and all share the same clocks.

However, they're not packaged in the same way, and therefore not all the
controllers are actually available on all these SoCs.

Introduce a clock controller driver for all these SoCs with different
compatibles to take that into account.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23 11:45:29 +01:00
Icenowy Zheng d0f11d14b0 clk: sunxi-ng: add support for V3s CCU
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks
about CSI, are different, which makes it to need a new CCU driver.

Add such a new driver for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-20 21:39:03 +01:00
Linus Torvalds 991688bfc6 ARM: SoC driver updates for v4.10
Driver updates for ARM SoCs, including a couple of newly added drivers:
 
 - A new driver for the power management controller on TI Keystone
 - Support for the prerelease "SCPI" firmware protocol that ended up
   being shipped by Amlogic in their GXBB SoC.
 - A soc_device can now be matched using a glob from inside the
   kernel, when another driver wants to know the specific chip
   it is running on and cannot find out from DT, firmware or hardware.
 - Renesas SoCs now support identification through the soc_device
   interface, both in user space and kernel.
 - Renesas r8a7743 and r8a7745 gain support for their system controller
 - A new checking module for the ARM "PSCI" (not to be confused
   with "SCPI" mentioned above) firmware interface.
 - A new driver for the Tegra GMI memory interface
 - Support for the Tegra firmware interfaces with their
   power management controllers
 
 As usual, the updates for the reset controller framework are merged
 here, as they tend to touch multiple SoCs as well, including a new
 driver for the Oxford (now Broadcom) OX820 chip and the Tegra
 bpmp interface.
 
 The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and
 Rockchips SoCs see some further updates.
 
 Conflicts:
 - ARCH_RENESAS now selects SOC_BUS, but no longer needs GPIOLIB
 - drivers/soc/renesas/Makefile: multiple files got added, keep
   all in logical sorting
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "Driver updates for ARM SoCs, including a couple of newly added
  drivers:

   - A new driver for the power management controller on TI Keystone

   - Support for the prerelease "SCPI" firmware protocol that ended up
     being shipped by Amlogic in their GXBB SoC.

   - A soc_device can now be matched using a glob from inside the
     kernel, when another driver wants to know the specific chip it is
     running on and cannot find out from DT, firmware or hardware.

   - Renesas SoCs now support identification through the soc_device
     interface, both in user space and kernel.

   - Renesas r8a7743 and r8a7745 gain support for their system
     controller

   - A new checking module for the ARM "PSCI" (not to be confused with
     "SCPI" mentioned above) firmware interface.

   - A new driver for the Tegra GMI memory interface

   - Support for the Tegra firmware interfaces with their power
     management controllers

  As usual, the updates for the reset controller framework are merged
  here, as they tend to touch multiple SoCs as well, including a new
  driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp
  interface.

  The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and
  Rockchips SoCs see some further updates"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits)
  misc: sram: remove useless #ifdef
  drivers: psci: Allow PSCI node to be disabled
  drivers: psci: PSCI checker module
  soc: renesas: Identify SoC and register with the SoC bus
  firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails
  firmware: qcom: scm: Remove core, iface and bus clocks dependency
  dt-bindings: firmware: scm: Add MSM8996 DT bindings
  memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name()
  bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name()
  ARM: shmobile: Document DT bindings for Product Register
  soc: renesas: rcar-sysc: add R8A7745 support
  reset: Add Tegra BPMP reset driver
  dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
  dt-bindings: Add power domains to Tegra BPMP firmware
  firmware: tegra: Add BPMP support
  firmware: tegra: Add IVC library
  dt-bindings: firmware: Add bindings for Tegra BPMP
  mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
  mailbox: Add Tegra HSP driver
  firmware: arm_scpi: add support for pre-v1.0 SCPI compatible
  ...
2016-12-15 16:03:25 -08:00
Olof Johansson e40719dd01 firmware: Add Tegra IVC and BPMP support
IVC is an inter-processor communication protocol that uses shared memory
 to exchange data between processors. The BPMP driver makes use of this
 to communicate with the Boot and Power Management Processor (BPMP) and
 uses an additional hardware synchronization primitive from the HSP block
 to signal availability of new data (doorbell).
 
 Firmware running on the BPMP implements a number of services such as the
 control of clocks and resets within the system, or the ability to ungate
 or gate power partitions.
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Merge tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

firmware: Add Tegra IVC and BPMP support

IVC is an inter-processor communication protocol that uses shared memory
to exchange data between processors. The BPMP driver makes use of this
to communicate with the Boot and Power Management Processor (BPMP) and
uses an additional hardware synchronization primitive from the HSP block
to signal availability of new data (doorbell).

Firmware running on the BPMP implements a number of services such as the
control of clocks and resets within the system, or the ability to ungate
or gate power partitions.

* tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
  dt-bindings: Add power domains to Tegra BPMP firmware
  firmware: tegra: Add BPMP support
  firmware: tegra: Add IVC library
  dt-bindings: firmware: Add bindings for Tegra BPMP

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:28:14 -08:00
Joseph Lo d55865608f dt-bindings: firmware: Add bindings for Tegra BPMP
The Boot and Power Management Processor (BPMP) is a co-processor found
in Tegra SoCs. It is designed to handle the early stages of the boot
process as well as to offload power management tasks (such as clocks,
resets, powergates, ...).

The binding document defines the resources that are used by the BPMP
firmware, which implements the interprocessor communication (IPC)
between the CPU and the BPMP.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-18 14:33:41 +01:00
Maxime Ripard c6a0637460 clk: sunxi-ng: Add A64 clocks
Add the A64 CCU clocks set.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-03 09:06:18 +01:00
Neil Armstrong 8cc134a367 dt-bindings: reset: oxnas: Add include file with reset indexes
Add DT include file for Oxford Semiconductor OX810SE and OX820 reset
controller support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-10-20 11:55:09 +02:00
Stephen Boyd de64f5c87d Allwinner Clock changes for 4.9
Four more SoCs converted to the new clock framework (A31, A31s, A23 and
 A33).
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Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock driver changes from Maxime Ripard:

Four more SoCs converted to the new clock framework (A31, A31s, A23 and
A33).

* tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: Add hardware dependency
  clk: sunxi-ng: Add A23 CCU
  clk: sunxi-ng: Add A33 CCU support
  clk: sunxi-ng: Add N-class clocks support
  clk: sunxi-ng: mux: Add mux table macro
  clk: sunxi-ng: div: Allow to set a maximum
  clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure
  clk: sunxi-ng: div: Add mux table macros
  clk: sunxi-ng: Add A31/A31s clocks
  clk: sunxi-ng: mux: Add clk notifier functions
  clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
  clk: sunxi-ng: mux: Add support for mux tables
  clk: sunxi-ng: mux: Rename mux macro to be consistent
  clk: sunxi-ng: nkm: Add mux to support multiple parents
  clk: sunxi-ng: mux: Increase fixed pre-divider div size
2016-09-14 11:10:15 -07:00
Maxime Ripard d05c748bd7 clk: sunxi-ng: Add A33 CCU support
This commit introduces the clocks found in the Allwinner A33 CCU.

Since this SoC is very similar to the A23, and we share a significant share
of the DTSI, the clock IDs that are going to be used will also be shared
with the A23, hence the name of the various header files.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10 11:41:19 +02:00
Chen-Yu Tsai c6e6c96d8f clk: sunxi-ng: Add A31/A31s clocks
Add a new style driver for the clock control unit in Allwinner A31/A31s.

A few clocks are still missing:

    - MIPI PLL's HDMI mode support
    - EMAC clock

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-25 22:31:43 +02:00
Stephen Boyd 43d6912417 Merge branch 'clk-meson-gxbb-ao' into clk-next
* clk-meson-gxbb-ao:
  clk: meson: Add GXBB AO Clock and Reset controller driver
  dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
2016-08-19 12:51:14 -07:00
Neil Armstrong edb89f126f dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
Add documentations and dt-bindings headers for the AO clock and reset
controller.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:49:00 -07:00
Shunli Wang c3c5768346 reset: mediatek: Add MT2701 reset controller dt-binding file
Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.

Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:47:20 -07:00
Neil Armstrong f7508fedd8 dt-bindings: Add MDM9615 DT bindings include files for GCC and LCC
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15 15:51:18 -07:00
Linus Torvalds 43a0a98aa8 ARM: SoC driver updates for v4.8
Driver updates for ARM SoCs.
 
 A slew of changes this release cycle. The reset driver tree, that we merge
 through arm-soc for historical reasons, is also sizable this time around.
 
 Among the changes:
 
  - clps711x: Treewide changes to compatible strings, merged here for simplicity.
  - Qualcomm: SCM firmware driver cleanups, move to platform driver
  - ux500: Major cleanups, removal of old mach-specific infrastructure.
  - Atmel external bus memory driver
  - Move of brcmstb platform to the rest of bcm
  - PMC driver updates for tegra, various fixes and improvements
  - Samsung platform driver updates to support 64-bit Exynos platforms
  - Reset controller cleanups moving to devm_reset_controller_register() APIs
  - Reset controller driver for Amlogic Meson
  - Reset controller driver for Hisilicon hi6220
  - ARM SCPI power domain support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs.

  A slew of changes this release cycle.  The reset driver tree, that we
  merge through arm-soc for historical reasons, is also sizable this
  time around.

  Among the changes:

   - clps711x: Treewide changes to compatible strings, merged here for simplicity.
   - Qualcomm: SCM firmware driver cleanups, move to platform driver
   - ux500: Major cleanups, removal of old mach-specific infrastructure.
   - Atmel external bus memory driver
   - Move of brcmstb platform to the rest of bcm
   - PMC driver updates for tegra, various fixes and improvements
   - Samsung platform driver updates to support 64-bit Exynos platforms
   - Reset controller cleanups moving to devm_reset_controller_register() APIs
   - Reset controller driver for Amlogic Meson
   - Reset controller driver for Hisilicon hi6220
   - ARM SCPI power domain support"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits)
  ARM: ux500: consolidate base platform files
  ARM: ux500: move soc_id driver to drivers/soc
  ARM: ux500: call ux500_setup_id later
  ARM: ux500: consolidate soc_device code in id.c
  ARM: ux500: remove cpu_is_u* helpers
  ARM: ux500: use CLK_OF_DECLARE()
  ARM: ux500: move l2x0 init to .init_irq
  mfd: db8500 stop passing around platform data
  ASoC: ab8500-codec: remove platform data based probe
  ARM: ux500: move ab8500_regulator_plat_data into driver
  ARM: ux500: remove unused regulator data
  soc: raspberrypi-power: add CONFIG_OF dependency
  firmware: scpi: add CONFIG_OF dependency
  video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip
  input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip
  pwm: clps711x: Changing the compatibility string to match with the smallest supported chip
  serial: clps711x: Changing the compatibility string to match with the smallest supported chip
  irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip
  clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip
  clk: clps711x: Changing the compatibility string to match with the smallest supported chip
  ...
2016-08-01 18:36:01 -04:00
Maxime Ripard 0577e4853b clk: sunxi-ng: Add H3 clocks
Add the list of clocks and resets found in the H3 CCU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com
2016-07-08 18:05:12 -07:00
Andrew F. Davis a3828519c3 Documentation: dt: reset: Add TI syscon reset binding
Add TI syscon reset controller binding. This will hook to the reset
framework and use syscon/regmap to set reset bits. This allows reset
control of individual SoC subsytems and devices with memory-mapped
reset registers in a common register memory space.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-29 23:39:10 +02:00
Xinliang Liu 339d00cb17 arm64: dts: hi6220: Add media subsystem reset dts
Add media subsystem reset dts support.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-29 23:39:08 +02:00
Neil Armstrong 79795e20a1 dt-bindings: reset: Add bindings for the Meson SoC Reset Controller
Add DT bindings for the Meson SoC Reset Controller documentation and the
associated include file.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-01 08:21:12 +02:00
Damien Horsley 8a56736a2f reset: img: Add Pistachio reset controller driver
Add reset controller driver for Pistachio SoC

Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: James Hartley <james.hartley@imgtec.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-02-05 16:41:20 +01:00
Linus Torvalds 9638685e32 ARM: SoC driver updates for v4.5
Driver updates for ARM SoCs. Some for SoC-family code under drivers/soc,
 but also some other driver updates that don't belong anywhere else. We also
 bring in the drivers/reset code through arm-soc.
 
 Some of the larger updates:
 
 - Qualcomm support for SMEM, SMSM, SMP2P. All used to communicate with other
   parts of the chip/board on these platforms, all proprietary protocols that
   don't fit into other subsystems and live in drivers/soc for now.
 
 - System bus driver for UniPhier
 - Driver for the TI Wakeup M3 IPC device
 
 - Power management for Raspberry PI
 
 + Again a bunch of other smaller updates and patches.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs.  Some for SoC-family code under
  drivers/soc, but also some other driver updates that don't belong
  anywhere else.  We also bring in the drivers/reset code through
  arm-soc.

  Some of the larger updates:

   - Qualcomm support for SMEM, SMSM, SMP2P.  All used to communicate
     with other parts of the chip/board on these platforms, all
     proprietary protocols that don't fit into other subsystems and live
     in drivers/soc for now.

   - System bus driver for UniPhier

   - Driver for the TI Wakeup M3 IPC device

   - Power management for Raspberry PI

  + Again a bunch of other smaller updates and patches"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
  bus: uniphier: allow only built-in driver
  ARM: bcm2835: clarify RASPBERRYPI_FIRMWARE dependency
  MAINTAINERS: Drop Kumar Gala from QCOM
  bus: uniphier-system-bus: add UniPhier System Bus driver
  ARM: bcm2835: add rpi power domain driver
  dt-bindings: add rpi power domain driver bindings
  ARM: bcm2835: Define two new packets from the latest firmware.
  drivers/soc: make mediatek/mtk-scpsys.c explicitly non-modular
  soc: mediatek: SCPSYS: Add regulator support
  MAINTAINERS: Change QCOM entries
  soc: qcom: smd-rpm: Add existing platform support
  memory/tegra: Add number of TLB lines for Tegra124
  reset: hi6220: fix modular build
  soc: qcom: Introduce WCNSS_CTRL SMD client
  ARM: qcom: select ARM_CPU_SUSPEND for power management
  MAINTAINERS: Add rules for Qualcomm dts files
  soc: qcom: enable smsm/smp2p modular build
  serial: msm_serial: Make config tristate
  soc: qcom: smp2p: Qualcomm Shared Memory Point to Point
  soc: qcom: smsm: Add driver for Qualcomm SMSM
  ...
2016-01-20 18:42:30 -08:00
Philipp Zabel 967313e2ec ARM: mediatek: DT: Move reset controller constants into common location
By popular vote, the DT binding includes for reset controllers are located
in include/dt-bindings/reset/. Move the mediatek reset constants in there,
too, to avoid confusion.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-11-24 18:58:12 +01:00
Chen Feng 04d112690d reset: hisilicon: document hisi-hi6220 reset controllers bindings
Add DT bindings documentation for hi6220 SoC reset controller.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2015-11-20 15:41:28 +01:00
Lee Jones c9bfec0032 ARM: STi: Add DT defines for co-processor reset lines
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-16 09:23:47 +01:00
Linus Torvalds b3a5af435a ARM: DT updates for v4.3
This is the usual large batch of DT updates. Lots and lots of smaller
 changes, some of the larger ones to point out are:
 
 - Rockchip veyron (Chromebook) support, as well as several other new boards
 - DRM support on Atmel AT91SAM9N12EK
 - USB additions on some Allwinner platforms
 - Mediatek MT6580 support
 - Freescale i.MX6UL support
 - Cleanups for Renesas shmobile platforms
 - Lots of added devices on LPC18xx
 - Lots of added devices and boards on UniPhier
 
 There's also some dependent code added here, in particular some branches
 that are primarily merged through the clock tree.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "Ladies and gentlemen, we proudly announce to you the latest branch of
  ARM device tree contents for the mainline kernel.  Come and see, come
  and see!

  No less than twentythree thousand lines of additions! Just imagine the
  joy you will have of using your mainline kernel on newly supported
  hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
  UniPhier hardware!

  For those of you feeling less adventurous, added hardware support on
  platforms such as TI DM814x and Gumstix Overo platforms might be more
  of your liking.

  We've got something for everyone here!

  Ahem.  Cough.  So, anyway...

  This is the usual large batch of DT updates.  Lots and lots of smaller
  changes, some of the larger ones to point out are:

   - Rockchip veyron (Chromebook) support, as well as several other new boards
   - DRM support on Atmel AT91SAM9N12EK
   - USB additions on some Allwinner platforms
   - Mediatek MT6580 support
   - Freescale i.MX6UL support
   - cleanups for Renesas shmobile platforms
   - lots of added devices on LPC18xx
   - lots of added devices and boards on UniPhier

  There's also some dependent code added here, in particular some
  branches that are primarily merged through the clock tree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
  ARM: tegra: Add gpio-ranges property
  ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
  ARM: tegra: Add Tegra124 PMU support
  ARM: tegra: jetson-tk1: Add GK20A GPU DT node
  ARM: tegra: venice2: Add GK20A GPU DT node
  ARM: tegra: Add IOMMU node to GK20A
  ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
  ARM: tegra: Add entries for cpufreq on Tegra124
  ARM: tegra: Enable the DFLL on the Jetson TK1
  ARM: tegra: Add the DFLL to Tegra124 device tree
  ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
  ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
  ARM: dts: rockchip: correct regulator power states for suspend
  ARM: dts: rockchip: correct regulator PM properties
  ARM: dts: vexpress: Use assigned-clock-parents for sp810
  pinctrl: tegra: Only set the gpio range if needed
  arm: boot: dts: am4372: add ARM timers and SCU nodes
  ARM: dts: AM4372: Add the am4372-rtc compatible string
  ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
  ...
2015-09-01 13:09:20 -07:00
Linus Torvalds 102178108e ARM: SoC driver updates for v4.3
Some releases this branch is nearly empty, others we have more stuff. It
 tends to gather drivers that need SoC modification or dependencies such
 that they have to (also) go in through our tree.
 
 For this release, we have merged in part of the reset controller tree
 (with handshake that the parts we have merged in will remain stable),
 as well as dependencies on a few clock branches.
 
 In general, new items here are:
 
 - Qualcomm driver for SMM/SMD, which is how they communicate with the
   coprocessors on (some) of their platforms
 - Memory controller work for ARM's PL172 memory controller
 - Reset drivers for various platforms
 - PMU power domain support for Marvell platforms
 - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Some releases this branch is nearly empty, others we have more stuff.
  It tends to gather drivers that need SoC modification or dependencies
  such that they have to (also) go in through our tree.

  For this release, we have merged in part of the reset controller tree
  (with handshake that the parts we have merged in will remain stable),
  as well as dependencies on a few clock branches.

  In general, new items here are:

   - Qualcomm driver for SMM/SMD, which is how they communicate with the
     coprocessors on (some) of their platforms

   - memory controller work for ARM's PL172 memory controller

   - reset drivers for various platforms

   - PMU power domain support for Marvell platforms

   - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller
     per-SoC support"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
  ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze()
  ARM: tegra: Disable cpuidle if PSCI is available
  soc/tegra: pmc: Use existing pclk reference
  soc/tegra: pmc: Remove unnecessary return statement
  soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile
  memory: tegra: Add Tegra210 support
  memory: tegra: Add support for a variable-size client ID bitfield
  clk: shmobile: rz: Add CPG/MSTP Clock Domain support
  clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
  clk: shmobile: Add CPG/MSTP Clock Domain support
  ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
  reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
  docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
  MIPS: ath79: Add the reset controller to the AR9132 dtsi
  reset: Add a driver for the reset controller on the AR71XX/AR9XXX
  devicetree: Add bindings for the ATH79 reset controller
  reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
  doc: dt: add documentation for lpc1850-rgu reset driver
  ...
2015-09-01 13:00:04 -07:00
Olof Johansson f4be3c67ed ARM: tegra: Devicetree changes for v4.3-rc1
Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on
 Venice2 and Jetson TK1. This also enables support for the PMU hardware
 found on Tegra124, which among other things, can be used for performance
 measurements.
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Merge tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

ARM: tegra: Devicetree changes for v4.3-rc1

Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on
Venice2 and Jetson TK1. This also enables support for the PMU hardware
found on Tegra124, which among other things, can be used for performance
measurements.

* tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Add gpio-ranges property
  ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
  ARM: tegra: Add Tegra124 PMU support
  ARM: tegra: jetson-tk1: Add GK20A GPU DT node
  ARM: tegra: venice2: Add GK20A GPU DT node
  ARM: tegra: Add IOMMU node to GK20A
  ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
  ARM: tegra: Add entries for cpufreq on Tegra124
  ARM: tegra: Enable the DFLL on the Jetson TK1
  ARM: tegra: Add the DFLL to Tegra124 device tree
  pinctrl: tegra: Only set the gpio range if needed
  clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
  clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
  clk: tegra: Add Tegra124 DFLL clocksource platform driver
  clk: tegra: Add DFLL DVCO reset control for Tegra124
  clk: tegra: Introduce ability for SoC-specific reset control callbacks
  clk: tegra: Add functions for parsing CVB tables
  clk: tegra: Add closed loop support for the DFLL
  clk: tegra: Add library for the DFLL clock source (open-loop mode)
  clk: tegra: Add binding for the Tegra124 DFLL clocksource

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-21 10:15:29 -07:00
Dinh Nguyen 007bb689b3 dt-bindings: Add reset manager offsets for Arria10
The reset manager for is pretty similar to the one for SoCFPGA
cyclone5/arria5 except for a few offsets. This patch adds those offsets.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-09 21:58:33 -05:00
Philipp Zabel efdf5aa8f1 ARM: STi: DT: Move reset controller constants into common location
By popular vote, the DT binding includes for reset controllers are located
in include/dt-bindings/reset/. Move the STi reset constants in there, too,
to avoid confusion.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2015-08-03 13:13:44 +02:00
Paul Walmsley a3c83ff20c clk: tegra: Add DFLL DVCO reset control for Tegra124
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16 09:32:48 +02:00
Stephen Boyd f7b81d67d0 clk: qcom: Add support for NSS/GMAC clocks and resets
Add the NSS/GMAC clocks and the TCM clock and NSS resets.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-05-30 17:04:36 -07:00
Georgi Djakov a5408ec605 dt-bindings: Add #defines for MSM8916 clocks and resets
Add clocks/resets defines for the global clock controller
found on Qualcomm MSM8916 SoCs.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23 16:09:20 -07:00
Stephen Boyd e216ce60a9 clk: qcom: Add support for APQ8064 multimedia clocks
The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15 16:39:03 -07:00