Граф коммитов

2611 Коммитов

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Chanwoo Choi 1259feddd0 pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433
This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433
because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV
registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV.

Fixes: 3c5ecc9ed3 ("pinctrl: exynos: Add support for Exynos5433")
Cc: stable@vger.kernel.org
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30 14:27:42 +01:00
Neil Armstrong f24d311f92 pinctrl: meson: fix gpio request disabling other modes
The pinctrl_gpio_request is called with the "full" gpio number, already
containing the base, then meson_pmx_request_gpio is then called with the
final pin number.
Remove the base addition when calling meson_pmx_disable_other_groups.

Fixes: 6ac7309511 ("pinctrl: add driver for Amlogic Meson SoCs")
CC: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-29 21:04:45 +01:00
Shyam Sundar S K 2983f296f2 pinctrl/amd: Set the level based on ACPI tables
In the function amd_gpio_irq_set_type, read the values from
the ACPI table to set the level and drop the settings passed
by the client.

Cc: <stable@vger.kernel.org> # 4.8.x+
Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com>
Reviewed-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com>
Signed-off-by: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-29 21:04:44 +01:00
Linus Torvalds 786a72d791 ARM: DT updates for v4.10
Lots of changes as usual, so I'm trying to be brief here. Most of the
 new hardware support has the respective driver changes merged through
 other trees or has had it available for a while, so this is where things
 come together.
 
 We get a DT descriptions for a couple of new SoCs, all of them variants
 of other chips we already support, and usually coming with a new
 evaluation board:
 
 - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
 - Qualcomm MDM9615 LTE baseband
 - NXP imx6ull, the latest and smallest i.MX6 application processor variant
 - Renesas RZ/G (r8a7743 and r8a7745) application processors
 - Rockchip PX3, a variant of the rk3188 chip used in Android tablets
 - Rockchip rk1108 single-core application processor
 - ST stm32f746 Cortex-M7 based microcontroller
 - TI DRA71x automotive processors
 
 These are commercially available consumer platforms we now support:
 - Motorola Droid 4 (xt894) mobile phone
 - Rikomagic MK808 Android TV stick based on Rockchips rx3066
 - Cloud Engines PogoPlug v3 based on OX820
 - Various Broadcom based wireless devices:
   - Netgear R8500 router
   - Tenda AC9 router
   - TP-LINK Archer C9 V1
   - Luxul XAP-1510 Access point
 - Turris Omnia open hardware router based on Armada 385
 
 And a couple of new boards targeted at developers, makers
 or industrial integration:
 - Macnica Sodia development platform for Altera socfpga (Cyclone V)
 - MicroZed board based on Xilinx Zynq FPGA platforms
 - TOPEET itop/elite based on exynos4412
 - WP8548 MangOH Open Hardware platform for IOT, based on
   Qualcomm MDM9615
 - NextThing CHIP Pro gadget
 - NanoPi M1 development board
 - AM571x-IDK industrial board based on TI AM5718
 - i.MX6SX UDOO Neo
 - Boundary Devices Nitrogen6_SOM2 (i.MX6)
 - Engicam i.CoreM6
 - Grinn i.MX6UL liteSOM/liteBoard
 - Toradex Colibri iMX6 module
 
 Other changes:
 - added peripherals on renesas, davinci, stm32f429, uniphier, sti,
   mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
   mvebu, allwinner, broadcom, exynos, zynq
 
 - Continued fixes for W=1 dtc warnings
 
 - The old STiH415/416 SoC support gets removed, these never made it into
   products and have served their purpose in the kernel as a template
   for teh newer chips from ST
 
 - The exynos4415 dtsi file is removed as nothing uses it.
 
 - Intel PXA25x can now be booted using devicetree
 
 Conflicts:
 arch/arm/boot/dts/r8a*.dtsi: a node was added
 the clk tree, keep both sides and watch out for git
 dropping the required '};' at the end of each side.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Arnd Bergmann:
 "Lots of changes as usual, so I'm trying to be brief here. Most of the
  new hardware support has the respective driver changes merged through
  other trees or has had it available for a while, so this is where
  things come together.

  We get a DT descriptions for a couple of new SoCs, all of them
  variants of other chips we already support, and usually coming with a
  new evaluation board:

   - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
   - Qualcomm MDM9615 LTE baseband
   - NXP imx6ull, the latest and smallest i.MX6 application processor variant
   - Renesas RZ/G (r8a7743 and r8a7745) application processors
   - Rockchip PX3, a variant of the rk3188 chip used in Android tablets
   - Rockchip rk1108 single-core application processor
   - ST stm32f746 Cortex-M7 based microcontroller
   - TI DRA71x automotive processors

  These are commercially available consumer platforms we now support:

   - Motorola Droid 4 (xt894) mobile phone
   - Rikomagic MK808 Android TV stick based on Rockchips rx3066
   - Cloud Engines PogoPlug v3 based on OX820
   - Various Broadcom based wireless devices:
      - Netgear R8500 router
      - Tenda AC9 router
      - TP-LINK Archer C9 V1
      - Luxul XAP-1510 Access point
   - Turris Omnia open hardware router based on Armada 385

  And a couple of new boards targeted at developers, makers or
  industrial integration:

   - Macnica Sodia development platform for Altera socfpga (Cyclone V)
   - MicroZed board based on Xilinx Zynq FPGA platforms
   - TOPEET itop/elite based on exynos4412
   - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615
   - NextThing CHIP Pro gadget
   - NanoPi M1 development board
   - AM571x-IDK industrial board based on TI AM5718
   - i.MX6SX UDOO Neo
   - Boundary Devices Nitrogen6_SOM2 (i.MX6)
   - Engicam i.CoreM6
   - Grinn i.MX6UL liteSOM/liteBoard
   - Toradex Colibri iMX6 module

  Other changes:

   - added peripherals on renesas, davinci, stm32f429, uniphier, sti,
     mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
     mvebu, allwinner, broadcom, exynos, zynq

   - Continued fixes for W=1 dtc warnings

   - The old STiH415/416 SoC support gets removed, these never made it
     into products and have served their purpose in the kernel as a
     template for teh newer chips from ST

   - The exynos4415 dtsi file is removed as nothing uses it.

   - Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits)
  arm: dts: zynq: Add MicroZed board support
  ARM: dts: da850: enable high speed for mmc
  ARM: dts: da850: Add node for pullup/pulldown pinconf
  ARM: dts: da850: enable memctrl and mstpri nodes per board
  ARM: dts: da850-lcdk: Add ethernet0 alias to DT
  ARM: dts: artpec: add pcie support
  ARM: dts: add support for Turris Omnia
  devicetree: Add vendor prefix for CZ.NIC
  ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node
  ARM: dts: berlin2q-marvell-dmp: fix regulators' name
  ARM: dts: Add xo to sdhc clock node on qcom platforms
  ARM: dts: r8a7794: Add device node for PRR
  ARM: dts: r8a7793: Add device node for PRR
  ARM: dts: r8a7792: Add device node for PRR
  ARM: dts: r8a7791: Add device node for PRR
  ARM: dts: r8a7790: Add device node for PRR
  ARM: dts: r8a7779: Add device node for PRR
  ARM: dts: r8a73a4: Add device node for PRR
  ARM: dts: sk-rzg1e: add Ether support
  ARM: dts: sk-rzg1e: initial device tree
  ...
2016-12-15 15:50:24 -08:00
Linus Torvalds 20d5ba4928 Bulk pin control changes for the v4.10 kernel cycle:
No core changes this time. Mainly gradual improvement and
 feature growth in the drivers.
 
 New drivers:
 
 - New driver for TI DA850/OMAP-L138/AM18XX pinconf
 
 - The SX150x was moved over from the GPIO subsystem and
   reimagined as a pin control driver with GPIO support
   in a joint effort by three independent users of this
   hardware. The result was amazingly good!
 
 - New subdriver for the Oxnas OX820
 
 Improvements:
 
 - The sunxi driver now supports the generic pin control
   bindings rather than the sunxi-specific. Add debouncing
   support to the driver.
 
 - Simplifications in pinctrl-single adding a generic parser.
 
 - Two downstream fixes and move the Raspberry Pi BCM2835 over
   to use the generic GPIOLIB_IRQCHIP.
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Merge tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl updates from Linus Walleij:
 "Bulk pin control changes for the v4.10 kernel cycle:

  No core changes this time. Mainly gradual improvement and
  feature growth in the drivers.

  New drivers:

   - New driver for TI DA850/OMAP-L138/AM18XX pinconf

   - The SX150x was moved over from the GPIO subsystem and reimagined as
     a pin control driver with GPIO support in a joint effort by three
     independent users of this hardware. The result was amazingly good!

   - New subdriver for the Oxnas OX820

  Improvements:

   - The sunxi driver now supports the generic pin control bindings
     rather than the sunxi-specific. Add debouncing support to the
     driver.

   - Simplifications in pinctrl-single adding a generic parser.

   - Two downstream fixes and move the Raspberry Pi BCM2835 over to use
     the generic GPIOLIB_IRQCHIP"

* tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (92 commits)
  pinctrl: sx150x: use new nested IRQ infrastructure
  pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505
  pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced'
  pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147]
  pinctrl: mt8173: set GPIO16 to usb iddig mode
  pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP
  pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf
  devicetree: bindings: pinctrl: Add binding for ti,da850-pupd
  Documentation: pinctrl: palmas: Add ti,palmas-powerhold-override property definition
  pinctrl: intel: set default handler to be handle_bad_irq()
  pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507
  pinctrl: sx150x: sort chips by part number
  pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)
  pinctrl: imx: fix imx_pinctrl_desc initialization
  pinctrl: sx150x: support setting multiple pins at once
  pinctrl: sx150x: various spelling fixes and some white-space cleanup
  pinctrl: mediatek: use builtin_platform_driver
  pinctrl: stm32: use builtin_platform_driver
  pinctrl: sunxi: Testing the wrong variable
  pinctrl: nomadik: split up and comments MC0 pins
  ...
2016-12-13 07:59:10 -08:00
Linus Torvalds 061ad5038c Bulk GPIO changes for the v4.10 kernel cycle:
Core changes:
 
 - Simplify threaded interrupt handling: instead of passing
   numbed parameters to gpiochip_irqchip_add_chained() we
   create a new call: gpiochip_irqchip_add_nested() so the two
   types are clearly semantically different. Also make sure
   that all nested chips call gpiochip_set_nested_irqchip()
   which is necessary for IRQ resend to work properly if
   it happens.
 
 - Return error on seek operations for the chardev.
 
 - Clamp values set as part of gpio[d]_direction_output() so
   that anything != 0 will be send down to the driver as "1"
   not the value passed in.
 
 - ACPI can now support naming of GPIO lines, hogs and holes
   in the GPIO lists.
 
 New drivers:
 
 - The SX150x driver was deemed unfit for the GPIO subsystem
   and was moved over to a combined GPIO+pinctrl driver in the
   pinctrl subsystem.
 
 New features:
 
 - Various cleanups to various drivers.
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Merge tag 'gpio-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Luinus Walleij:
 "Bulk GPIO changes for the v4.10 kernel cycle:

  Core changes:

   - Simplify threaded interrupt handling: instead of passing numbed
     parameters to gpiochip_irqchip_add_chained() we create a new call:
     gpiochip_irqchip_add_nested() so the two types are clearly
     semantically different. Also make sure that all nested chips call
     gpiochip_set_nested_irqchip() which is necessary for IRQ resend to
     work properly if it happens.

   - Return error on seek operations for the chardev.

   - Clamp values set as part of gpio[d]_direction_output() so that
     anything != 0 will be send down to the driver as "1" not the value
     passed in.

   - ACPI can now support naming of GPIO lines, hogs and holes in the
     GPIO lists.

  New drivers:

   - The SX150x driver was deemed unfit for the GPIO subsystem and was
     moved over to a combined GPIO+pinctrl driver in the pinctrl
     subsystem.

  New features:

   - Various cleanups to various drivers"

* tag 'gpio-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (49 commits)
  gpio: merrifield: Implement gpio_get_direction callback
  gpio: merrifield: Add support for hardware debouncer
  gpio: chardev: Return error for seek operations
  gpio: arizona: Tidy up probe error path
  gpio: arizona: Remove pointless set of platform drvdata
  gpio: pl061: delete platform data handling
  gpio: pl061: move platform data into driver
  gpio: pl061: rename variable from chip to pl061
  gpio: pl061: rename state container struct
  gpio: pl061: use local state for parent IRQ storage
  gpio: set explicit nesting on drivers
  gpio: simplify adding threaded interrupts
  gpio: vf610: use builtin_platform_driver
  gpio: axp209: use correct register for GPIO input status
  gpio: stmpe: fix interrupt handling bug
  gpio: em: depnd on ARCH_SHMOBILE
  gpio: zx: depend on ARCH_ZX
  gpio: x86: update config dependencies for x86 specific hardware
  gpio: mb86s7x: use builtin_platform_driver
  gpio: etraxfs: use builtin_platform_driver
  ...
2016-12-13 07:54:57 -08:00
Linus Walleij f821444508 pinctrl: sx150x: use new nested IRQ infrastructure
Use the new gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip() calls to properly created
a nested irqchip and mark all child irqs properly with
their parent IRQ.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 16:02:55 +01:00
Peter Rosin 283dc0be75 pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505
This fixes a problem where sx150x_regmap_reg_width() returns 8 for the
data register (reg 0) for sx1504 where it should return 4, and return
a correct 8 for sx1505 but for the wrong reason (both chips lack the
'advanced' register). This is not a real problem, since nothing depends
on the function returning 4 or 8, and certainly not if it is returning
8 for the wrong reason. But fix this to avoid nasty surprises down the
line.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:03 +01:00
Peter Rosin c9d26f1aab pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced'
This matches the datasheets and is less confusing since the register
has nothing to with advancing anything.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:02 +01:00
Peter Rosin 6c4ef627d8 pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147]
The code assumes 8-bit or 16-bit width registers, but three of the
chips (sx1501/sx1504/sx1507) are 4-bit. So, try to handle 4-bit chips as
well, they leave the high part of each register unused.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:02 +01:00
Chunfeng Yun 222ed59e8d pinctrl: mt8173: set GPIO16 to usb iddig mode
the default mode of GPIO16 pin is gpio, when set EINT16 to
IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be
fixed when set its default mode as usb iddig.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:01 +01:00
Linus Walleij 85ae9e512f pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP
It should be possible to use the GPIOLIB_IRQCHIP helper
library with the BCM2835 driver since it is a pretty straight
forward cascaded irqchip.

The only difference from other drivers is that the BCM2835
has several banks for a single gpiochip, and each bank has
a separate IRQ line. Instead of creating one gpiochip per
bank, a single gpiochip covers all banks GPIO lines. This
makes it necessary to resolve the bank ID in the IRQ
handler.

The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off
the same gpiochip by calling gpiochip_set_chained_irqchip()
repeatedly, but we have been a bit short on examples
for how this should be handled in practice, so this is intended
as an example of how this can be achieved.

The old code did not model the chip as a chained interrupt
handler, but this patch also rectifies that situation.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:01 +01:00
David Lechner 1ff91f0ae3 pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf
This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These
SoCs have a separate controller for controlling pullup/pulldown groups.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:27:00 +01:00
Andy Shevchenko 3ae02c14d9 pinctrl: intel: set default handler to be handle_bad_irq()
We switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07 15:26:59 +01:00
Arnd Bergmann bb986384d1 This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10,
please pull the following:
 
 - Rafal adds support for the Netgear R8500 routers, adds basic support
   for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex
   A7). He also enables the UART on the Netgear R8000 and restructures the
   include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes
   which enables USB 3.0 on BCM5301X devices that support it. Finally he adds
   support for the TP-LINK Archer C9 V1 router.
 
 - Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates
   the bcm958625k reference board to have it enabled
 
 - Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using
   a BCM47094)
 
 - Scott fixes the pinctrl names in the Cygnus DTS files
 
 - Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc
   SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds
   the node for the OTP controller found on Cygnus SoCs
 
 - Dhananjay enables the GPIO B controller on Norstarh Plus SoCs
 
 - Eric defines standard pinctrl groups in the BCM2835 GPIO node
 
 - Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
   to use their appropriate pinctrl functions
 
 - Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
 
 - Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
 
 - Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
   Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally
   adds names for the Raspberry Zero GPIO lines
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Merge tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux into next/dt

Pull "Broadcom devicetree changes for 4.10" from Florian Fainelli:

This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10,
please pull the following:

- Rafal adds support for the Netgear R8500 routers, adds basic support
  for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex
  A7). He also enables the UART on the Netgear R8000 and restructures the
  include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes
  which enables USB 3.0 on BCM5301X devices that support it. Finally he adds
  support for the TP-LINK Archer C9 V1 router.

- Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates
  the bcm958625k reference board to have it enabled

- Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using
  a BCM47094)

- Scott fixes the pinctrl names in the Cygnus DTS files

- Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc
  SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds
  the node for the OTP controller found on Cygnus SoCs

- Dhananjay enables the GPIO B controller on Norstarh Plus SoCs

- Eric defines standard pinctrl groups in the BCM2835 GPIO node

- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
  to use their appropriate pinctrl functions

- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet

- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block

- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
  Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally
  adds names for the Raspberry Zero GPIO lines

* tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux: (29 commits)
  ARM: bcm2835: Add names for the RPi Zero GPIO lines
  ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines
  ARM: dts: enable GPIO-b for Broadcom NSP
  ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1
  ARM: dts: Add node for Broadcom OTP controller driver
  ARM: dts: Enable interrupt support for cygnus crmu gpio driver
  ARM: dts: Enable Broadcom iProc mailbox controller
  ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
  ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
  dt: bindings: add thermal device driver for bcm2835
  ARM: dts: bcm283x: fix typo in mailbox address
  DT: binding: bcm2835-mbox: fix address typo in example
  ARM: dts: cygnus: fix naming of pinctrl node
  ARM: BCM53573: Specify PMU and its ILP clock in the DT
  ARM: BCM5301X: Add DT for Luxul XWR-3100
  ARM: BCM5301X: Add DT for Luxul XAP-1510
  ARM: BCM5301X: Specify USB 3.0 PHY in DT
  ARM: BCM5301X: Enable UART on Netgear R8000
  ARM: BCM5301X: Add separated DTS include file for BCM47094
  ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes
  ...
2016-11-30 17:53:03 +01:00
Peter Rosin 4f5ac8cf0a pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507
Untested, register offsets carefully copied from datasheets.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25 14:44:08 +01:00
Peter Rosin bba709bd7a pinctrl: sx150x: sort chips by part number
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25 14:40:59 +01:00
Peter Rosin 1663682cf0 pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)
All other registers on these chips are 8-bit, but reg_sense is 16-bits
and therefore needs to be moved down one notch.
This was apparently overlooked in the conversion to regmap, which only
updated the register locations for the 16-bit chips.

Fixes: 6489677f86 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API")
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25 14:40:06 +01:00
Gary Bisson 8f5983ad6b pinctrl: imx: fix imx_pinctrl_desc initialization
Fixes: 6e408ed8be ("pinctrl: imx: fix initialization of imx_pinctrl_desc")
Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25 14:09:21 +01:00
Peter Rosin ec61168bc0 pinctrl: sx150x: support setting multiple pins at once
If the chip does not have an oscio pin, all pins are configured in
the same regmap register making it trivial to update all pins at
once, so do that. If an oscio pin is present, there needs to be
more locking in place to handle all cases correctly, so this is
skipped.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-24 15:07:44 +01:00
Peter Rosin 7bd474963a pinctrl: sx150x: various spelling fixes and some white-space cleanup
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-23 14:33:00 +01:00
Geliang Tang 4ecb65fb87 pinctrl: mediatek: use builtin_platform_driver
Use builtin_platform_driver() helper to simplify the code.

Signed-off-by: Geliang Tang <geliangtang@gmail.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22 10:17:28 +01:00
Geliang Tang 5b209efa3f pinctrl: stm32: use builtin_platform_driver
Use builtin_platform_driver() helper to simplify the code.

Signed-off-by: Geliang Tang <geliangtang@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22 09:57:39 +01:00
Dan Carpenter b3cde198b1 pinctrl: sunxi: Testing the wrong variable
Smatch complains that we dereference "map" before testing it for NULL
which is true.  We should be testing "*map" instead.  Also on the error
path, we should free *map and set it to NULL.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22 09:55:33 +01:00
Linus Walleij 04d02c7a5e pinctrl: nomadik: split up and comments MC0 pins
When debugging it helps to see exactly which pin goes where,
so make it very detailed.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-18 09:54:32 +01:00
Dan Carpenter 712778d02d pinctrl: single: Fix a couple error codes
We should return -ENOMEM instead of success if pcs_add_function() fails.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-16 20:56:19 +01:00
Arnd Bergmann d8a2221273 pinctrl: sunxi: fix theoretical uninitialized variable access
gcc warns about a  way that it could use an uninitialized variable:

drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init':
drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]

This cannot really happen except if 'freq' is UINT_MAX and 'clock' is
zero, and both of these are forbidden. To shut up the warning anyway,
this changes the logic to initialize the return code to the first
divider value before looking at the others.

Fixes: 7c926492d3 ("pinctrl: sunxi: Add support for interrupt debouncing")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-16 20:53:48 +01:00
Linus Walleij d278dae884 pinctrl: sh-pfc: Updates for v4.10 (take two)
- DU and EtherAVB pin groups for R-Car M3-W,
   - Bias handling cleanups and bug fixes,
   - Drive-strength for non-GPIO pins for R-Car H3,
   - EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
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Merge tag 'sh-pfc-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.10 (take two)

  - DU and EtherAVB pin groups for R-Car M3-W,
  - Bias handling cleanups and bug fixes,
  - Drive-strength for non-GPIO pins for R-Car H3,
  - EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
2016-11-16 20:50:49 +01:00
Andy Yan 688daf234f pinctrl: rockchip: add support for rk1108
This add pinctrl support for Rockchip RK1108 Soc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Series-changes: 2
- add pull and drive-strength functionality

Series-changes: 3
- two minor CodingStyle fixes adviced by Heiko
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-16 20:34:00 +01:00
Niklas Söderlund 1fa1522f61 pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pins
Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc
drivers. The pins can not be muxed between functions other than QSPI,
but their drive strength can be controlled.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:14 +01:00
Niklas Söderlund b25719eb93 pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins
Group the AVB pins into similar groups found in other sh-pfc drivers.
The pins can not be muxed between functions other then AVB but their
drive strength can be controlled.

The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs
called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:13 +01:00
Niklas Söderlund ea9c740583 pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength
There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.

The pins can now be referred to in DT by function names and their
drive-strength modified.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:12 +01:00
Niklas Söderlund 1ce56aea7c pinctrl: sh-pfc: Support named pins with custom configuration
Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.

The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:12 +01:00
Niklas Söderlund 5c296f69ab pinctrl: sh-pfc: r8a7778: Use lookup function for bias data
Change the data structure and use the generic sh_pfc_pin_to_bias_info()
function to get the register offset and bit information.

Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:11 +01:00
Niklas Söderlund d3b861bccd pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.

 # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins

 WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
 [..]
 Call trace:
 [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
 [<ffff0000081fe3bc>] seq_read+0x16c/0x420
 [<ffff00000831a110>] full_proxy_read+0x58/0x88
 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
 [<ffff0000081d8874>] vfs_read+0x84/0x148
 [<ffff0000081d9d64>] SyS_read+0x44/0xa0
 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4

This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.

Fixes: 560655247b ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:10 +01:00
Niklas Söderlund 42831cf965 pinctrl: sh-pfc: r8a7795: Simplify get bias logic
The last else statement is missing braces, and the indentation level can
be reduced.

Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:28:58 +01:00
Niklas Söderlund c314c9f15a pinctrl: sh-pfc: Add helper to handle bias lookup table
On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.

Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:09 +01:00
Niklas Söderlund 5d7400c4ac pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE
Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() is implemented but the pin is not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin has bias control
support.

Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if their particular implementation of {set,get}_bias() is called with a
pin it does not know about.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:09 +01:00
Niklas Söderlund cccc618a0b pinctrl: sh-pfc: r8a7796: Add DU support
Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups. Based on a similar patch from Laurent
Pinchart for the r8a7795 PFC driver.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:08 +01:00
Takeshi Kihara 9c99a63ec7 pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions
This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS,
AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:07 +01:00
Maxime Ripard 7c926492d3 pinctrl: sunxi: Add support for interrupt debouncing
The pin controller found in the Allwinner SoCs has support for interrupts
debouncing.

However, this is not done per-pin, preventing us from using the generic
pinconf binding for that, but per irq bank, which, depending on the SoC,
ranges from one to five.

Introduce a device-wide property to deal with this using a microsecond
resolution. We can re-use the per-pin input-debounce property for that, so
let's do it!

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 10:23:02 +01:00
Chen-Yu Tsai 5181482719 pinctrl: sunxi: Make sunxi_pconf_group_set use sunxi_pconf_reg helper
The sunxi_pconf_reg helper introduced in the last patch gives us the
chance to rework sunxi_pconf_group_set to have it match the structure
of sunxi_pconf_(group_)get and make it easier to understand.

For each config to set, it:

    1. checks if the parameter is supported.
    2. checks if the argument is within limits.
    3. converts argument to the register value.
    4. writes to the register with spinlock held.

As a result the function now blocks unsupported config parameters,
instead of silently ignoring them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 10:21:49 +01:00
Chen-Yu Tsai c5fda170e8 pinctrl: sunxi: Add support for fetching pinconf settings from hardware
The sunxi pinctrl driver only caches whatever pinconf setting was last
set on a given pingroup. This is not particularly helpful, nor is it
correct.

Fix this by actually reading the hardware registers and returning
the correct results or error codes. Also filter out unsupported
pinconf settings. Since this driver has a peculiar setup of 1 pin
per group, we can support both pin and pingroup pinconf setting
read back with the same code. The sunxi_pconf_reg helper and code
structure is inspired by pinctrl-msm.

With this done we can also claim to support generic pinconf, by
setting .is_generic = true in pinconf_ops.

Also remove the cached config value. The behavior of this was never
correct, as it only cached 1 setting instead of all of them. Since
we can now read back settings directly from the hardware, it is no
longer required.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 10:20:27 +01:00
Chen-Yu Tsai 223dba00b4 pinctrl: sunxi: Fix PIN_CONFIG_BIAS_PULL_{DOWN,UP} argument
According to pinconf-generic.h, the argument for
PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled
with a pull up/down resistor, zero if it is directly connected
to VDD or ground.

Since Allwinner hardware uses a weak pull resistor internally,
the argument should be 1.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 10:17:45 +01:00
Chen-Yu Tsai 88f01a1bd0 pinctrl: sunxi: Free configs in pinctrl_map only if it is a config map
In the recently refactored sunxi pinctrl library, we are only allocating
one set of pin configs for each pinmux setting node. When the pinctrl_map
structure is freed, the pin configs should also be freed. However the
code assumed the first map would contain the configs, which actually
never happens, as the mux function map gets added first.

The proper way to do this is to look through all the maps and free the
first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP.

Also slightly expand the comment explaining this.

Fixes: f233dbca62 ("pinctrl: sunxi: Rework the pin config building code")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 10:15:04 +01:00
Paul Gortmaker 23d511f6fe pinctrl: vt8500: make bool drivers explicitly non-modular
None of the Kconfigs for any of these drivers are tristate, meaning
that they currently are not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only.  All
drivers get the exact same change, so they are handled in batch.

Changes are (1) use builtin_platform_driver, (2) use init.h header
(3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE,
(5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags and (6)
drop ".remove" code and prevent sysfs unbind attempts to call ".remove".

Once this is done, the shared remove function in wmt.[ch] is no longer
used and hence it is removed as well.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE etc. tags since all that information
is already contained at the top of each file in the comments.

Cc: Tony Prisk <linux@prisktech.co.nz>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 10:04:20 +01:00
Chanwoo Choi ac8130e94c pinctrl: samsung: Add GPF support for Exynos5433
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 09:42:44 +01:00
Chanwoo Choi 8b1bd11c1f pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank
This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
In the pre-existing Exynos series, the registers of the gpio bank are included
in the one memory map. But, some gpio bank need to support the one more memory
map (IORESOURCE_MEM) because the registers of gpio bank are separated into
the different memory map.

For example,
The both ALIVE and IMEM domain have the different memory base address.
The GFP[1-5] of exynos5433 are composed as following:
- ALIVE domain : WEINT_* registers
- IMEM domain  : CON/DAT/PUD/DRV/CONPDN/PUDPDN register

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 09:41:35 +01:00
Phil Elwell ccca1ad5db pinctrl: bcm2835: Return pins to inputs when freed
When dynamically unloading overlays, it is important that freed pins are
restored to being inputs to prevent functions from being enabled in
multiple places at once.

Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 00:14:14 +01:00
Phil Elwell 00445b5d58 pinctrl: bcm2835: Fix ints for GPIOs 28-31 & 46-53
Contrary to the documentation, the BCM2835 GPIO controller actually
has four interrupt lines - one each for the three IRQ groups and one
common. Confusingly, the GPIO interrupt groups don't correspond
directly with the GPIO control banks. Instead, GPIOs 0-27 generate IRQ
GPIO0, 28-45 IRQ GPIO1 and 46-53 IRQ GPIO2.

Awkwardly, the GPIOs for IRQ GPIO1 straddle two 32-entry GPIO banks,
so split out a function to process the interrupts for a single GPIO
bank.

Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-15 00:13:52 +01:00