Battery power levels are shared between spitz and corgi, rename
variable to reflect it.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This fixes checkpatch/style problems in sharpsl_pm.c, allowing me to
submit real fixes next.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Because original macro can only judge whether current CPU is pxa93x,
rename the macro to correct name.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
CONFIG_CPU_PXA{300,310,320,930,935,950} are really platform dependent
and should be made into selectable hidden options.
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
MACH_COLIBRI300 is supposed to support both PXA300 and PXA310, select
the missing CPU_PXA310.
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Acked-by: Daniel Mack <daniel@caiaq.de>
For some platforms, it is inappropriate to register all PXA UARTs.
In some cases, the UARTs may not be used, and in others we may want
to avoid registering the UARTs to allow other drivers (eg, FICP) to
make use of the UART.
In addition, a while back there was a request to be able to pass
platform data to the UART driver.
This patch enables all of this by providing functions platforms can
call to register each individual UART.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Mike Rapoport <mike@compulab.co.il>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This should be eventually moved to somewhere closer to the U2D driver,
but is kept here atm so it's easier for USB configuration code to work.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Due to the naming mess in Kconfig and Makefile, I'd like to get them sorted
in the following order:
1. By category:
Intel/Marvell Dev Platforms, followed by 3rd party platforms, followed
by end-user products (this is to ensure the commonly referenced platforms
will appear first)
2. By vendor name in alphabetic within each category
(this is to ensure code reuse and similar platforms can be grouped as
much as possible)
VENDOR BOARD
Intel/Marvell Lubbock
Intel/Marvell Mainstone
Intel/Marvell Zylonite
Intel/Marvell Littleton
Intel/Marvell TavorEVB
Intel/Marvell SAAR
Accelent IDP
Arcom/Eurotech VIPER
Community Balloon3
Cogent CSB726
CompuLab EM_X270
CompuLab EXEDA
CompuLab ARMCORE
CompuLab CM_X300
Gumstix Gumstix
Intel Research MOTE2
Intel research Stargate2
Iskratel XCEP
Keith and Koep Trizeps4
LogicPD LPD270
Phytec PCM027
Toradex Colibri
HP HX4700
HP H5000
HTC Himalaya
HTC Magician
Mitac MioA701
Motorola EZX
NEC MP900C
Palm Palm PDA
Palm Palm GSM
Sharp Zaurus
Toshiba E-Series
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Since flash structure is changed from flash_platform_data to
onenand_platform_data in generic driver. Update the struct in saar
and ttc platform driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Since the same nand controller is shared between ARCH_PXA and ARCH_MMP. Move
the pxa3xx_nand.h from mach directory to plat directoy.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Cc: David Woodhouse <david.woodhouse@intel.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
MTD_NAND_PXA3xx module is shared between ARCH_PXA and ARCH_MMP. Update
this configuration according to it.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Support samsung 2GbX8 and 32GbX8 nand flash.
Support micron 4GbX8 and 4GbX16 nand flash.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
In some bootloader, IRQ is enabled. Writing nand triggers unexpected
interrupts. So disable nand irq in initialization. After nand
initialized and in working state, irq is controlled by nand driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Nand driver uses IRQ_NAND as hardcode irq number. In ARCH_MMP, the irq
number is different. So get irq resource from platform device structure
and use it in initialization and deinitialization code.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Although nand controller is same between PXA3xx and MMP, the register space
is different. Remove the hardcode register address setting in pxa3xx_nand.h.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Slow down the tRp of Micron NAND flash timing.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Initialize the read buffer content to 0xFF.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
When fetch nand data with non-DMA mode, we should align info->data_size to
32bit, not 8bit.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Set default WLED output current in saar. Otherwise, LCD backlight won't be
effective.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Some SPI host drivers do not change chip select betwen transfers unless
.cs_chnage field is explicitly set. The LCD spec requires chip select
change between consecuitive transfers, so ensure it at the SPI driver
level.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Along with more processor supporting 26MHz mode (including pxa935),
introduce an individual macro mmc_has_26mhz() for this.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This allows to select either RGB565 (transparency 0) or RGBT555
(transparency 1) from the mode info
Signed-off-by: Pieter Grimmerink <p.grimmerink@inepro.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
pxafb_pan_display() used to ignore the fb_var_screeninfo parameter. Now
pass it to setup_base_frame() instead of pulling default values out of
fb_info.
And the original patch has an issue of pxafb_pan_display() paying only
attention to the 'var' parameter passed in, and Ville Syrjälä pointed
out, this is potentially dangerous as user could pass in any other
screeninfo parameters as well, and not only such that are relevant for
display panning. This is fixed by limiting the arguments actually used
to .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP.
Signed-off-by: Sven Neumann <s.neumann@raumfeld.com>
Cc: Ville Syrjälä <syrjala@sci.fi>
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* 'bugfixes' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6:
SUNRPC: Address buffer overrun in rpc_uaddr2sockaddr()
NFSv4: Fix a cache validation bug which causes getcwd() to return ENOENT
As this struct is exposed to user space and the API was added for this
release it's a bit of a pain for the C++ world and we still have time to
fix it. Rename the fields before we end up with that pain in an actual
release.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Reported-by: Olivier Goffart
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Commit 86cf898e1d ("intel-iommu: Check for
'DMAR at zero' BIOS error earlier.") was supposed to work by pretending
not to detect an IOMMU if it was actually being reported by the BIOS at
physical address zero.
However, the intel_iommu_init() function is called unconditionally, as
are the corresponding functions for other IOMMU hardware.
So the patch only worked if you have RAM above the 4GiB boundary. It
caused swiotlb to be initialised when no IOMMU was detected during early
boot, and thus the later IOMMU init would refuse to run.
But if you have less RAM than that, swiotlb wouldn't get set up and the
IOMMU _would_ still end up being initialised, even though we never
claimed to detect it.
This patch also sets the dmar_disabled flag when the error is detected
during the initial detection phase -- so that the later call to
intel_iommu_init() will return without doing anything, regardless of
whether swiotlb is used or not.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq:
[CPUFREQ] Fix stale cpufreq_cpu_governor pointer
[CPUFREQ] Resolve time unit thinko in ondemand/conservative govs
[CPUFREQ] speedstep-ich: fix error caused by 394122ab14
[CPUFREQ] Fix use after free on governor restore
[CPUFREQ] acpi-cpufreq: blacklist Intel 0f68: Fix HT detection and put in notification message
[CPUFREQ] powernow-k8: Fix test in get_transition_latency()
[CPUFREQ] longhaul: select Longhaul version 2 for capable CPUs
Doing the strcmp return value as
signed char __res = *cs - *ct;
is wrong for two reasons. The subtraction can overflow because __res
doesn't use a type big enough. Moreover the compared bytes should be
interpreted as unsigned char as specified by POSIX.
The same problem is fixed in strncmp.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* 'agp-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/agp-2.6:
agp/intel-agp: Set dma_mask for capable chipsets before agp_add_bridge()
We should set this before calling agp_add_bridge() so that it's done
before we map the scratch page too.
This should probably fix the regression reported as k.o. bug #14627.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Antonio Ospite
Pavel Machek
Haojian Zhuang
Mike Rapoport
Eric Miao
Russell King
Igor Grinberg
Haojian Zhuang
Tomáš Čech
Jun Nie
Pieter Grimmerink
Sven Neumann
Jonathan Cameron
Linus Torvalds
Alan Cox
David Woodhouse